CN106847699B

CN106847699B - Based on Ga2O3Cap layer composite double-gate NMOSFET of material and preparation method thereof

Info

Publication number: CN106847699B
Application number: CN201611123674.6A
Authority: CN
Inventors: 元磊; 张弘鹏; 贾仁需; 张玉明
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2016-12-08
Filing date: 2016-12-08
Publication date: 2020-02-14
Anticipated expiration: 2036-12-08
Also published as: CN106847699A

Abstract

The invention relates to a Ga-based alloy₂O₃The method comprises selecting semi-insulating substrate, and growing P type β -Ga by molecular beam epitaxy₂O₃Forming a mesa by dry etching, forming a source region and a drain region at both sides of the mesa by ion implantation, growing a source electrode and a drain electrode, and growing a source electrode and a drain electrode at β -Ga₂O₃Sputtering the inclined plane positions on the other two sides of the table top to form a first gate dielectric layer and a second gate dielectric layer at the side close to the source region and the side close to the drain region respectively to form a composite double-gate dielectric layer; forming a cap layer on the surface of the composite double-gate dielectric layer; and forming a gate electrode on the surface of the cap layer, and finally forming the NMOSFET. The invention adopts two materials with different dielectric constants as a composite gate oxide layer to transmit electrons and block holes so as to improve the transmission rate, adopts a thinner cap layer and adopts a high-temperature process to form a gate oxide layer/Ga₂O₃And a dipole layer is formed at the interface, so that the adjustment of the band edge work function is realized, and the reliability of the device is improved.

Description

Based on Ga2O3Cap layer composite double-gate NMOSFET of material and preparation method thereof

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a Ga-based semiconductor device₂O₃A cap layer of the material is compounded with a dual-gate NMOSFET and a preparation method thereof.

Background

The structure and performance of an MOS device, i.e., a metal-oxide-semiconductor field effect transistor, are completely different from those of an earlier bipolar integrated circuit since the time comes, and the MOS integrated circuit has the advantages of high input impedance, strong anti-interference capability, low power consumption, high integration level, and the like, so that the MOS device becomes the mainstream of the super-large-scale integrated circuit era. The MOS devices are divided into NMOS, PMOS and CMOS according to different substrates and different conductive channels, wherein the MOS device adopting the P-type substrate to form the N-type channel is the NMOS.

The NMOS is conducted after Vgs is larger than a fixed value, and a carrier depended by current transmission of the device is an electron, so that the device is suitable for the condition that a source electrode is grounded.

The third generationWide bandgap semiconductor material Ga₂O₃MOSFETs of materials are emerging as semiconductor integrated circuit power devices and optoelectronic devices, but β -Ga is used₂O₃When the substrate is applied to a high-speed device, the defects of insufficient electron transmission rate, low heat conductivity compared with other wide bandgap materials and the like exist, and in addition, the metal gate/high-k gate dielectric structure is applied to Ga₂O₃The more serious Fermi pinning effect occurs when the substrate is used, and the Ga is greatly influenced₂O₃Device performance of NMOSFETs.

Therefore, how to produce high-performance Ga-based₂O₃The NMOSFET of the material becomes extremely important.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a Ga-based alloy₂O₃A cap layer of the material is compounded with a dual-gate NMOSFET and a preparation method thereof.

An embodiment of the present invention provides a Ga-based₂O₃The preparation method of the material cap layer composite double-gate NMOSFET comprises the following steps:

step 1, selecting a semi-insulating substrate, and growing P-type β -Ga on the surface of the semi-insulating substrate by adopting a molecular beam epitaxy method₂O₃Layer, and forming P-type β -Ga by dry etching₂O₃A table top;

step 2, preparing the β -Ga₂O₃Forming a source region and a drain region on two sides of the surface of the table board by adopting an ion implantation process;

step 3, adopting a first mask to grow a source electrode and a drain electrode on the inclined planes of the source region side and the drain region side respectively;

step 4, adopting a second mask to carry out the step of β -Ga₂O₃Sputtering the inclined planes on the other two sides of the table top on the source region side by using a magnetron sputtering process to form a first gate dielectric layer;

step 5, adopting a third mask to carry out the step of β -Ga₂O₃Sputtering the inclined planes on the other two sides of the table top on the side of the drain region by using a magnetron sputtering process to form a second gate dielectric layer;

step 6, forming a cap layer on the surface of the composite double-gate dielectric layer;

and 7, forming a gate electrode on the surface of the cap layer by adopting a fourth mask, and finally forming the NMOSFET.

In one embodiment of the present invention, β -Ga is used as the carrier₂O₃The two sides of the surface of the table top form a source region and a drain region by adopting an ion implantation process, and the method comprises the following steps:

in said β -Ga₂O₃Forming source and drain lightly doped regions at two opposite sides of the surface of the table top by adopting an ion implantation process;

and forming a source-drain heavily doped region at the edge of the source-drain lightly doped region by adopting an ion implantation process.

In one embodiment of the present invention, a second reticle is used, at β -Ga₂O₃The inclined planes on the other two sides of the table top are sputtered on the source region side by utilizing a magnetron sputtering process to form a first gate dielectric layer, and the method comprises the following steps:

adopting the second mask, selecting Al material as sputtering target material, introducing argon and oxygen as sputtering gas into a sputtering cavity, and performing sputtering by using β -Ga₂O₃Al is sputtered on the side of the inclined planes on the other two sides of the table top close to the source region₂O₃And (3) forming the first gate dielectric layer.

In one embodiment of the present invention, a third reticle is used, at β -Ga₂O₃And sputtering the inclined planes on the other two sides of the table top on the side of the drain region by using a magnetron sputtering process to form a second gate dielectric layer, wherein the second gate dielectric layer comprises:

adopting the third mask plate and selecting Y₂O₃The material is used as a sputtering target material, argon and oxygen are used as sputtering gases and are introduced into a sputtering cavity, and β -Ga is added₂O₃Sputtering Y from the side of the inclined plane at the other two sides of the table top close to the drain region₂O₃And forming the second gate dielectric layer by using the material.

In one embodiment of the present invention, forming a cap layer on the surface of the composite dual-gate dielectric layer includes:

and forming the cap layer on the surface of the composite double-gate dielectric layer by using a La source and plasma oxygen as precursor gases by using an ALD (atomic layer deposition) process.

Another embodiment of the present invention provides a Ga-based alloy₂O₃And compounding the double-gate NMOSFET with a cap layer of the material, wherein the NMOSFET is prepared by any one of the methods in the embodiments.

Yet another embodiment of the present invention provides a Ga-based₂O₃The preparation method of the material cap layer composite double-gate NMOSFET comprises the following steps:

step 1, growing P type β -Ga on P type substrate of SiC or sapphire by molecular beam epitaxy method₂O₃Layer, and forming P-type β -Ga by dry etching process₂O₃A mesa to prepare an active region of the NMOSFET;

step 3, preparing the β -Ga₂O₃The inclined planes on the other two sides of the table top form a cap layer;

step 4, forming a first gate dielectric layer on the surface of the cap layer on the side close to the source region and forming a second gate dielectric layer on the side close to the drain region to form a composite double-gate dielectric layer;

and 5, forming a gate electrode on the surface of the composite double-gate dielectric layer, and finally forming the NMOSFET.

In one embodiment of the present invention, β -Ga is used as the carrier₂O₃After the source region and the drain region are formed on the two sides of the surface of the table board by adopting an ion implantation process, the method also comprises the following steps:

and respectively growing a source electrode and a drain electrode on the surfaces of the source region and the drain region.

Yet another embodiment of the present invention provides a Ga-based₂O₃And compounding the double-gate NMOSFET with a cap layer of the material, wherein the NMOSFET is prepared by any one of the methods in the embodiments.

Compared with the prior art, the composite double-gate high-speed NMOSFET provided by the embodiment of the invention at least has the following advantages:

1. the NMOSFET adopts two materials with different dielectric constants as the composite gate oxide layer to transmit electrons and block holes, thereby effectively improving the transmission rate of electrons along the channel direction, further effectively reducing the short channel effect and the hot carrier effect, increasing the breakdown voltage, overcoming the defect that the electron transmission rate in the traditional double-gate structure is not high enough, adjusting the threshold voltage by selecting the two materials with different combinations as the gate dielectric layer, and further playing the advantages of high transconductance, high carrier mobility and good subthreshold slope characteristic of the double-gate structure.

2. The NMOSFET of the invention introduces a thin cap layer between the gate oxide layer and the metal gate electrode, or Ga₂O₃Introducing a thin cap layer between the substrate and the gate oxide layer, and forming the gate oxide layer/Ga by subsequent high-temperature process₂O₃Elements such as Mg, La, Dy, Al, Ba, Cs and the like are provided at the interface to form a dipole layer, so that the adjustment of the band edge work function is realized, the adjustment of the threshold value is further better realized by changing the thickness of the cap layer and the annealing condition, the lamination effect of the multilayer metal gate electrode can be avoided, the serious Fermi pinning effect between the metal gate and the high-k gate medium is effectively relieved, and the reliability of the device is further improved.

Drawings

FIG. 1 shows a Ga-based material according to an embodiment of the present invention₂O₃A cap layer of material is combined with a first cross section schematic diagram of the double-gate NMOSFET;

FIG. 2 shows a Ga-based semiconductor device according to an embodiment of the present invention₂O₃A cap layer of material is combined with a second cross section schematic diagram of the double-gate NMOSFET;

FIG. 3 shows a Ga-based semiconductor device according to an embodiment of the present invention₂O₃A cap layer of material is combined with a third cross section schematic diagram of the double-gate NMOSFET;

FIG. 4 shows a Ga-based semiconductor device according to an embodiment of the present invention₂O₃A top view schematic diagram of a material cap layer compounded double-gate NMOSFET;

FIG. 5 shows a Ga-based semiconductor device according to an embodiment of the present invention₂O₃Manufacture of composite double-gate NMOSFET (N-channel Metal-oxide-semiconductor field Effect transistor) with cap layer made of materialPreparing a flow schematic diagram of the method;

FIGS. 6a to 6l are schematic views showing a Ga-based semiconductor device according to an embodiment of the present invention₂O₃The preparation method of the material cap layer composite double-gate NMOSFET is schematically shown;

FIG. 7 shows another Ga-based alloy according to an embodiment of the present invention₂O₃A cap layer of material is combined with a first cross section schematic diagram of the double-gate NMOSFET;

FIG. 8 shows another Ga-based alloy according to an embodiment of the present invention₂O₃A cap layer of material is combined with a second cross section schematic diagram of the double-gate NMOSFET;

FIG. 9 shows another Ga-based alloy according to an embodiment of the present invention₂O₃A cap layer of material is combined with a third cross section schematic diagram of the double-gate NMOSFET;

FIG. 10 shows another Ga-based alloy according to an embodiment of the present invention₂O₃A top view schematic diagram of a material cap layer compounded double-gate NMOSFET;

FIG. 11 shows another Ga-based alloy according to an embodiment of the present invention₂O₃The process schematic diagram of the preparation method of the material cap layer composite double-grid NMOSFET;

FIGS. 12 a-12 k show another Ga-based semiconductor device according to an embodiment of the present invention₂O₃The preparation method of the material cap layer composite double-gate NMOSFET is schematically shown;

fig. 13 a-13 b are schematic structural diagrams of a first reticle set according to an embodiment of the present invention;

fig. 14 a-14 b are schematic structural views of a second reticle set according to an embodiment of the present invention;

fig. 15 a-15 b are schematic structural diagrams of a third reticle set according to an embodiment of the present invention; and

fig. 16a to fig. 16b are schematic structural diagrams of a fourth mask set according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

Please refer toReferring to fig. 1, 2, 3 and 4, fig. 1 is a Ga-based semiconductor device according to an embodiment of the present invention₂O₃A first cross-sectional schematic of a cap layer of material composited dual gate NMOSFET (taken along the plane formed by the XY axes); FIG. 2 shows a Ga-based semiconductor device according to an embodiment of the present invention₂O₃A second cross-sectional schematic view of the cap layer of material composited dual-gate NMOSFET (taken along the plane formed by the ZY axis, the viewing angle is in the direction of drain electrode → source electrode); FIG. 3 shows a Ga-based semiconductor device according to an embodiment of the present invention₂O₃A third cross-sectional schematic diagram of the material cap layer compounded double-gate NMOSFET (taken along a plane formed by a ZY axis, and the viewing angle is in the direction of source electrode → drain electrode); FIG. 4 shows a Ga-based semiconductor device according to an embodiment of the present invention₂O₃A cap layer of material is composited with a top view schematic of a dual gate NMOSFET. The cap layer composite double-gate NMOSFET comprises a gallium oxide table top 1, a composite gate dielectric layer consisting of a gate oxide layer 2 close to a source end region and a gate oxide layer 3 close to a drain end region, a cap layer 4, a bimetallic gate electrode 9, source and drain lightly

doped regions

7 and 8, source and drain heavily doped

regions

11 and 12, source and

drain electrodes

5 and 6 and a semi-insulating substrate 10.

The substrate is a P-type semi-insulating substrate SiC or sapphire, and the gallium oxide mesa is P-type β -Ga undoped or doped with Cu, Al and other elements₂O₃(-201), P type β -Ga₂O₃(010) Or P-type β -Ga₂O₃(001) Material with thickness of 20-35nm and doping concentration of 10¹⁷cm^-3Magnitude; the area of the gate dielectric layer close to the drain end is TiO₂Or Y₂O₃Or HfO₂A material; the region of the gate dielectric layer close to the source end is Al₂O₃Or SiO₂Or Si₃N₄A material; the cap layer is MgO or La₂O₃Or Dy₂O₃And the like containing group IIA, IIIB elements; the double gate electrode is made of a metal material such as Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, Pb, an alloy containing 2 or more of these metals, or a conductive compound such as ITO. In addition, it may have a 2-layer structure composed of 2 or more different metals, for example, Al/Ti. Doping the source/drain heavily doped regionThe element can be Sn, Si or Al; the source/drain electrodes are made of a metal material such as Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, Pb, an alloy containing 2 or more of these metals, or an electrically conductive compound such as ITO. In addition, it may have a 2-layer structure composed of different 2 or more metals, for example, Al/Ti.

Referring to fig. 5, fig. 5 shows a Ga-based semiconductor device according to an embodiment of the present invention₂O₃The process schematic diagram of the preparation method of the material cap layer composite double-gate NMOSFET. The method comprises the following steps:

step 1, selecting a substrate SiC or sapphire substrate, and growing P-type β -Ga on the P-type semi-insulating substrate SiC or sapphire by adopting a molecular beam epitaxy method₂O₃Layer, and forming P-type β -Ga by dry etching₂O₃A mesa to prepare an active region of the NMOSFET;

step 2, forming a source region and a drain region on two sides of the surface of the active region by adopting an ion implantation process;

step 3, adopting a first mask to perform surface treatment on β -Ga₂O₃Growing a source electrode and a drain electrode on the inclined plane on the table surface side respectively;

step 4, adopting a second mask to carry out the step of β -Ga₂O₃Sputtering the inclined planes on the other two sides of the table top by using a magnetron sputtering process to form a first gate dielectric layer on the side close to the source region;

step 5, adopting a third mask to carry out the step of β -Ga₂O₃Sputtering the inclined planes on the other two sides of the table top by utilizing a magnetron sputtering process to form a second gate dielectric layer on the side close to the drain region so as to form a composite double-gate dielectric layer;

For step 2, it may include:

step 21 in the β -Ga₂O₃Forming source and drain lightly doped regions at two opposite sides of the surface of the table top by adopting an ion implantation process;

and step 22, forming a source-drain heavily doped region at the edge of the source-drain lightly doped region by adopting an ion implantation process.

For step 4, it may include:

adopting the second mask, selecting Al material as sputtering target material, introducing argon and oxygen as sputtering gas into a sputtering cavity, and performing sputtering by using β -Ga₂O₃The inclined planes on the other two sides of the table top are sputtered to form Al close to the source region₂O₃And (3) forming the first gate dielectric layer.

For step 5, it may include:

For step 7, it may include:

According to the embodiment of the invention, two materials with different dielectric constants are adopted as the composite gate oxide layer to transmit the electron blocking cavity, so that the transmission rate of electrons along the channel direction is effectively improved, a thinner cap layer is adopted between the gate oxide layer and the metal gate, and the subsequent high-temperature process is adopted to transmit the electron blocking cavity on the gate oxide layer/Ga₂O₃And a dipole layer is formed at the interface, so that the adjustment of the band edge work function is realized, the adjustment of the threshold value is further better realized by changing the thickness of the cap layer and the annealing condition, and the reliability of the device is improved.

Example two

Referring to fig. 6 a-6 l and fig. 13 a-13 b, fig. 14 a-14 b, fig. 15 a-15 b and fig. 16 a-16 b together, fig. 6 a-6 l are schematic diagrams illustrating a Ga-based semiconductor device according to an embodiment of the present invention₂O₃Fig. 13 a-13 b are schematic diagrams of a method for fabricating a cap layer composite dual gate NMOSFET according to an embodiment of the present inventionA schematic structural diagram of a mask group; fig. 14 a-14 b are schematic structural views of a second reticle set according to an embodiment of the present invention; fig. 15 a-15 b are schematic structural diagrams of a third reticle set according to an embodiment of the present invention; fig. 16a to fig. 16b are schematic structural diagrams of a fourth mask set according to an embodiment of the present invention. . This example is based on the above examples and is based on Ga of the present invention₂O₃The preparation method of the cap layer composite double-gate NMOSFET of the material is explained in detail as follows:

step 1: referring to fig. 6a, a P-type SiC or sapphire substrate 1 having a thickness of 350 μm is prepared and RCA cleaning is performed on the substrate.

Step 2, referring to fig. 6b and 6c, molecular beam epitaxy β -Ga is used for the semi-insulating substrate surface prepared in step 1₂O₃Layer 1 thickness 20-35nm doping concentration 1 x 10¹⁷cm^-3Then β -Ga is formed by dry etching₂O₃ A table top 1.

Step 3-please refer to FIG. 6d, β -Ga prepared in step 2₂O₃Ion implantation is carried out on two sides of the table board 1, so that the two side regions are source-drain lightly

doped regions

7 and 8, and the doping concentration is 1 multiplied by 10¹⁴～1×10¹⁶cm^-3The implanted ions may be Sn, Si, or Al.

Referring to fig. 6e, the source and drain heavily doped

regions

11 and 12 are formed at the edge of the source and drain lightly doped region by using an ion implantation process. The concentration of the heavily doped region is, for example, 1X 10¹⁸～1×10²⁰cm^-3The implanted ions may be Cu or N, Zn co-doped.

Step 4, please refer to FIG. 6f and FIGS. 13 a-13 b, heavily doping β -Ga on the left and right sides prepared in step 2₂O₃And forming source and

drain electrodes

5 and 6 by using a first mask on the region through magnetron sputtering Au, and annealing to form ohmic contact. In fig. 13a, a drain electrode mask and a source electrode mask, the entire surface of the substrate is mesa-shaped, so that the masks are prevented from being bent, and the small-sized masks are used in the inclined surface portions, and the regions not covered by the masks are pasted with dust-free paper.

Selecting mass ratio purity of sputtering target material>99.99 percent of gold and Ar with the mass percentage purity of 99.999 percent are used as sputtering gas to be introduced into a sputtering cavity, and before sputtering, the cavity of the magnetron sputtering equipment is cleaned for 5 minutes by high-purity argon gas and then is vacuumized. Under vacuum degree of 6X 10^-4-1.3×10^-3Pa, argon flow is 20-30cm³Preparing source and drain electrode gold under the conditions of a target base distance of 10cm per second and a working power of 20W-100W, wherein the thickness of the electrode is 40nm-100 nm. And (4) carrying out rapid thermal annealing after the sputtering is finished, and annealing for 3min at 500 ℃ in a nitrogen or argon environment.

The metal of the source and

drain electrodes

5 and 6 can be selected from different elements such as Au, Al, Ti and the like and a 2-layer structure consisting of the same, the source and drain electrodes can be replaced by metals such as Al, Ti, Ni, Ag, Pt and the like, and all process parameters of magnetron sputtering need to be changed after the replacement. Wherein Au, Ag and Pt have stable chemical properties; the cost of Al, Ti and Ni is low.

Step 5, please refer to FIG. 6g and FIGS. 14 a-14 b, the P-type β -Ga prepared in step 1₂O₃The inclined planes on the other two sides of the table top use a second mask plate, and Al close to the source end is sputtered by magnetron sputtering₂O₃The gate oxide layer forms a first gate dielectric layer 2. FIG. 14a shows one of the slanted reticles, FIG. 14b shows the other slanted reticle, and the mesa is also treated with a dust-free paper on the top flat surface.

Selecting mass ratio purity of sputtering target material>99.99 percent of aluminum target material, argon gas with the purity of 99.999 percent by mass and oxygen are taken as sputtering gas to be introduced into a sputtering cavity, the cavity of the magnetron sputtering equipment is cleaned for 5 minutes by high-purity argon gas before sputtering, and then the sputtering equipment is vacuumized. Under vacuum degree of 6X 10^-4-1.3×10^-3The flow rates of Pa, argon and oxygen are 20-30cm³Preparing Al close to the source end under the conditions of a target base distance of 10cm per second, a target base distance of 250W-350W and working power of 250W-350W₂O₃And the thickness of the gate oxide layer 2 is 5nm-15 nm.

The gate oxide layer near the source end can be SiO₂Or Si₃N₄And (4) replacing materials. But the effect of improving the electron transmission rate after replacement becomes worse, and the target material is replaced and various items are modified by magnetron sputteringAnd (4) process parameters.

Step 6, please refer to FIG. 6h and FIGS. 15 a-15 b, the P type β -Ga prepared in step 1₂O₃The inclined planes on the other two sides of the table top use a third mask plate, and TiO near the drain end is sputtered by magnetron sputtering₂The gate oxide layer is used as a second gate dielectric layer 3. FIG. 15a shows one of the slanted reticles, FIG. 15b shows the other slanted reticle, and the top flat surface of the mesa is treated with the same dust-free paper.

Selecting mass ratio purity of sputtering target material>99.99% of Y₂O₃And the ceramic target is formed by introducing oxygen and argon with the mass percentage purity of 99.999% into a sputtering cavity as sputtering gases, cleaning the cavity of the magnetron sputtering equipment for 5 minutes by using high-purity argon before sputtering, and then vacuumizing. Under vacuum degree of 6X 10^-4-1.3×10^-3Pa, oxygen and argon flow rate of 20-30cm³Preparing a gate oxide TiO layer close to a drain end under the conditions of a target material base distance of 10cm per second and a working power of 40W-70W₂The thickness of the gate oxide layer is the same as that of the step 3.

The gate oxide layer near the source end can be TiO₂Or HfO₂And (4) replacing materials. But the effect of improving the electron transmission rate becomes worse after replacement, and the target material is replaced and various process parameters are modified through magnetron sputtering.

And 7: referring to fig. 6i and 6j, a layer of La is deposited on the composite gate oxide layer by atomic layer deposition₂O₃Material forming the cap layer 4.

And (3) depositing on the composite gate oxide obtained in the step (6) by adopting an Atomic Layer Deposition (ALD) process, preparing a cap layer by taking a La source and plasma oxygen as precursors, and performing chemical mechanical polishing to enable the surface to be smooth, wherein the thickness of the cap layer is 0.5-3 nm.

The cap layer can be selected from MgO or Dy₂O₃And the like, can be realized by adopting an MBE process, and the thickness of the cap layer 4 is relatively accurately controlled. Of course, magnetron sputtering, PVD, MOCVD, etc. processes may be used, but the thickness of the cap layer cannot be precisely controlled.

And 8: referring to fig. 6k, fig. 6l and fig. 16 a-fig. 16b, a gate electrode gold material 9 is magnetron sputtered on the cap layer 4 by using a fourth mask. FIG. 16a shows one of the slanted reticles, FIG. 16b shows the other slanted reticle, and the mesa is also treated with dust-free paper on the top flat surface.

Growing a gate electrode Au on the cap layer 4 obtained in the step 6 by magnetron sputtering by using a fourth mask plate on the magnetron sputtering process, wherein the sputtering target material is selected from a material with mass ratio and purity>99.99 percent of gold and Ar with the mass percentage purity of 99.999 percent are used as sputtering gas to be introduced into a sputtering cavity, and before sputtering, the cavity of the magnetron sputtering equipment is cleaned for 5 minutes by high-purity argon gas and then is vacuumized. Under vacuum degree of 6X 10^-4-1.3×10^-3Pa, argon flow is 20-30cm³And preparing gate electrode gold under the conditions of a target base distance of 10cm per second, a working power of 20W-100W, wherein the thickness of the electrode is 40nm-100 nm.

The metal of the gate electrode can be selected from different elements such as Au, Al, Ti and the like and a 2-layer structure consisting of the elements, and the gate electrode can be replaced by metals such as Al \ Ti \ Ni \ Ag \ Pt and the like. Wherein Au \ Ag \ Pt has stable chemical properties; the cost of Al \ Ti \ Ni is low.

EXAMPLE III

Referring to fig. 7, 8, 9 and 10, fig. 7 shows another Ga-based semiconductor device according to an embodiment of the present invention₂O₃A first cross-sectional schematic of a cap layer of material composited dual gate NMOSFET (taken along the plane formed by the XY axes); FIG. 8 shows another Ga-based alloy according to an embodiment of the present invention₂O₃A second cross-sectional schematic view of the cap layer of material composited dual-gate NMOSFET (taken along the plane formed by the ZY axis, the viewing angle is in the direction of drain electrode → source electrode); FIG. 9 shows another Ga-based alloy according to an embodiment of the present invention₂O₃A third cross-sectional schematic diagram of the material cap layer compounded double-gate NMOSFET (taken along a plane formed by a ZY axis, and the viewing angle is in the direction of source electrode → drain electrode); FIG. 10 shows another Ga-based alloy according to an embodiment of the present invention₂O₃A cap layer of material is composited with a top view schematic of a dual gate NMOSFET. The composite dual gate NNMOSFET includes: a gallium oxide table-board 1, a composite gate dielectric layer consisting of a gate oxide layer 2 close to a source end region and a gate oxide layer 3 close to a drain end region, a cap layer 4, and a pair of double-gateThe semiconductor device comprises a metal gate electrode 9, source and drain heavily doped

regions

7 and 8, source and drain heavily doped

regions

11 and 12, source and

drain electrodes

5 and 6 and a substrate 10. The detailed description of the components is consistent with the above embodiments, and is not repeated here.

Referring to fig. 11, fig. 11 shows another Ga-based semiconductor device according to an embodiment of the present invention₂O₃The process schematic diagram of the preparation method of the material cap layer composite double-gate NMOSFET. The preparation method comprises the following steps:

Wherein, after the step 2, the method further comprises the following steps:

in said β -Ga₂O₃And growing a source electrode on the surface of the mesa close to the side surface of the source region and growing a drain electrode on the side surface close to the drain region.

Wherein, step 4 may include:

step 41, forming a first gate dielectric layer on the surface of the cap layer by sputtering on the side close to the source region by using a magnetron sputtering process by using a second mask;

and 42, forming a second gate dielectric layer on the surface of the cap layer by sputtering on the side close to the drain region by using a magnetron sputtering process by using a third mask to form a composite double-gate dielectric layer.

According to the embodiment of the invention, two materials with different dielectric constants are adopted as the composite gate oxide layer to transmit the electron blocking cavity, so that the transmission rate of electrons along the channel direction is effectively improved, and Ga is doped₂O₃A thinner cap layer is adopted between the substrate and the gate oxide layer, and the subsequent high-temperature process is carried out on the gate oxide layer/Ga₂O₃And a dipole layer is formed at the interface, so that the adjustment of the band edge work function is realized, the adjustment of the threshold value is further better realized by changing the thickness of the cap layer and the annealing condition, the electron transmission rate is improved, and the reliability of the device is improved.

Example four

Referring to fig. 12 a-12 k and fig. 13 a-13 b, fig. 14 a-14 b, fig. 15 a-15 b and fig. 16 a-16 b, fig. 12 a-12 k are schematic views of another Ga-based semiconductor device according to an embodiment of the present invention₂O₃The preparation method of the cap layer composite double-gate NMOSFET of the material is schematically illustrated in this embodiment, the preparation of the invention is explained in detail based on the third embodiment as follows:

step 1: referring to FIG. 12a, a P-type sapphire or SiC substrate 1 having a thickness of 350 μm was prepared and RCA cleaning was performed on the substrate. This step is similar to step 1 in the second embodiment, and is not described herein again.

Step 2, referring to fig. 12b and 12c, molecular beam epitaxy β -Ga is used for the semi-insulating substrate surface prepared in step 1₂O₃Layer 1 thickness 20-35nm doping concentration 1 x 10¹⁷cm^-3Then β -Ga is formed by dry etching₂O₃ A table top 1.

Step 3, please refer to FIG. 12d and FIG. 12e, the P type β -Ga prepared in step 2₂O₃Ion implantation is carried out on two sides of the surface of the table board 1, and doping is carried out to ensure that areas on two sides are source drain lightly doped

areas

7 and 8, the doping concentration is 1 multiplied by 10¹⁴～1×10¹⁶cm^-3The implanted ions may be Sn, Si, or Al.

And forming source and drain

heavy dopings

11 and 12 at the edge of the source and drain lightly doped region by adopting an ion implantation process. The concentration of the heavily doped region is, for example, 1X 10¹⁸～1×10²⁰cm^-3The implanted ions may be Sn, Si, or Al.

Step 4, please refer to FIG. 12f and FIGS. 13 a-13 b, heavily doping β -Ga on the left and right sides prepared in step 3₂O₃And a first mask is used on the region, Au source and

drain electrodes

5 and 6 are subjected to magnetron sputtering, and ohmic contact is formed by annealing. This step is similar to step 4 in the second embodiment, and is not described again here.

Step 5-please refer to FIG. 12g, β -Ga prepared in step 2₂O₃Depositing a layer of La on the inclined atomic layer at the other two sides of the table-board 1₂O₃The material is then subjected to chemical mechanical polishing to form the cap layer 4.

An Atomic Layer Deposition (ALD) process is adopted, a La source and plasma oxygen are used as precursors to prepare a cap layer 4, the surface is smooth through chemical mechanical polishing, and the thickness of the cap layer is 0.5-2 nm. This step is similar to step 7 in the second embodiment, and is not described again here.

Step 6: referring to fig. 12i and fig. 14 a-14 b, a second mask is used on the cap layer 4 prepared in step 4 to magnetron sputter Al near the source end₂O₃The gate oxide layer is used as a first gate dielectric layer 2. This step is similar to step 5 in the second embodiment, and is not described herein again.

And 7: referring to FIG. 12h and FIGS. 15 a-15 b, a third mask is used on the cap layer prepared in step 4 by magnetron sputtering TiO near the drain end₂The gate oxide layer is used as a second gate dielectric layer 3, and the surface is smooth by chemical mechanical polishing after growth. This step is similar to step 6 in the second embodiment, and is not described again here.

And 8: referring to fig. 12j and fig. 16 a-16 b, a fourth mask is used to form a gate electrode 9 on the composite gate oxide layer by magnetron sputtering gold material. This step is similar to step 7 of example 8, and is not described again here.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. Based on Ga₂O₃The preparation method of the material cap layer composite double-gate NMOSFET is characterized by comprising the following steps:

step 5, adopting a third mask to carry out the step of β -Ga₂O₃Sputtering the inclined planes on the other two sides of the table top on the drain region side by using a magnetron sputtering process to form a second gate dielectric layer so as to form a composite double-gate dielectric layer, wherein the dielectric constants of the second gate dielectric layer and the first gate dielectric layer are different;

2. The method of claim 1, wherein β -Ga is added₂O₃The two sides of the surface of the table top form a source region and a drain region by adopting an ion implantation process, and the method comprises the following steps:

in said β -Ga₂O₃Forming source and drain at two opposite sides of the mesa surface by ion implantationA lightly doped region;

3. The method of claim 1, wherein a second reticle is used to mask the β -Ga₂O₃The inclined planes on the other two sides of the table top are sputtered on the source region side by utilizing a magnetron sputtering process to form a first gate dielectric layer, and the method comprises the following steps:

4. The method of claim 1, wherein a third reticle is used to mask β -Ga₂O₃And sputtering the inclined planes on the other two sides of the table top on the side of the drain region by using a magnetron sputtering process to form a second gate dielectric layer, wherein the second gate dielectric layer comprises:

5. The method of claim 1, wherein forming a cap layer on the surface of the composite double gate dielectric layer comprises:

6. Based on Ga₂O₃A capped composite double-gated NMOSFET, characterized in that said NMOSFET is formed by the method as claimed in any one of claims 1-5.

7. Based on Ga₂O₃The preparation method of the material cap layer composite double-gate NMOSFET is characterized by comprising the following steps:

step 4, forming a first gate dielectric layer on the surface of the cap layer close to the source region side and forming a second gate dielectric layer on the surface of the cap layer close to the drain region side to form a composite double-gate dielectric layer, wherein the dielectric constants of the second gate dielectric layer and the first gate dielectric layer are different;

8. The method of claim 7, wherein β -Ga is added₂O₃After the source region and the drain region are formed on the two sides of the surface of the table board by adopting an ion implantation process, the method also comprises the following steps:

9. Based on Ga₂O₃A cap layer composite double-gate NMOSFET of a material, characterized in that the cap layer composite double-gate NMOSFET is prepared by the method of any one of claims 7-8.