CN106847699B - Based on Ga2O3Cap layer composite double-gate NMOSFET of material and preparation method thereof - Google Patents

Abstract

The invention relates to a Ga-based alloy₂O₃The method comprises selecting semi-insulating substrate, and growing P type β -Ga by molecular beam epitaxy₂O₃Forming a mesa by dry etching, forming a source region and a drain region at both sides of the mesa by ion implantation, growing a source electrode and a drain electrode, and growing a source electrode and a drain electrode at β -Ga₂O₃Sputtering the inclined plane positions on the other two sides of the table top to form a first gate dielectric layer and a second gate dielectric layer at the side close to the source region and the side close to the drain region respectively to form a composite double-gate dielectric layer; forming a cap layer on the surface of the composite double-gate dielectric layer; and forming a gate electrode on the surface of the cap layer, and finally forming the NMOSFET. The invention adopts two materials with different dielectric constants as a composite gate oxide layer to transmit electrons and block holes so as to improve the transmission rate, adopts a thinner cap layer and adopts a high-temperature process to form a gate oxide layer/Ga₂O₃And a dipole layer is formed at the interface, so that the adjustment of the band edge work function is realized, and the reliability of the device is improved.

Description

Cap layer compound double-gate NMOSFET based on Ga2O3 material and preparation method thereof

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to a cap-layer compound double-gate NMOSFET based on Ga ₂ O ₃ material and a preparation method thereof.

Background technique

MOS devices, that is, metal-oxide-semiconductor field effect transistors, have been completely different in structure and performance from earlier bipolar integrated circuits since their inception. MOS integrated circuits have high input impedance, strong anti-interference ability, low power consumption, Due to the advantages of large integration, it has become the mainstream in the era of VLSI. MOS devices are classified into NMOS, PMOS, and CMOS according to different substrates and different conductive channels. Among them, a MOS device using a P-type substrate to form an N-type channel is an NMOS.

NMOS is turned on after Vgs is greater than a fixed value. The carriers on which the current transmission of the device relies are electrons, so it is suitable for the case where the source is grounded. The drive between the control and the ground is smaller than the PMOS on-resistance and generates less heat.

At present, the third-generation wide-bandgap semiconductor material Ga ₂ O ₃ MOSFET is an emerging research direction for semiconductor integrated circuit power devices and optoelectronic devices. However, due to the insufficient electron transfer rate when the β-Ga ₂ O ₃ substrate is applied to high-speed devices , Compared with other wide-bandgap materials, the thermal conductivity is not high. In addition, when the metal gate/high-k gate dielectric structure is applied to the Ga ₂ O ₃ substrate, there is a serious Fermi pinning effect, which greatly affects the Ga ₂ O ₃ Device performance of NMOSFETs.

Therefore, how to fabricate high-performance NMOSFETs based on Ga ₂ O ₃ materials becomes extremely important.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap layer and a preparation method thereof.

An embodiment of the present invention provides a preparation method of a Ga ₂ O ₃ material-based cap layer composite double-gate NMOSFET, including:

Step 1. Select a semi-insulating substrate, grow a P-type β-Ga ₂ O ₃ layer on the surface of the semi-insulating substrate by molecular beam epitaxy, and form a P-type β-Ga ₂ O ₃ mesa by dry etching ;

Step 2, using an ion implantation process to form a source region and a drain region on both sides of the β-Ga ₂ O ₃ mesa surface;

Step 3. Using a first mask, grow source electrodes and drain electrodes on the slopes on the sides of the source and drain regions, respectively;

Step 4. Using a second mask, a first gate dielectric layer is formed by magnetron sputtering on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa on the side of the source region;

Step 5. Using a third mask, a second gate dielectric layer is formed by magnetron sputtering process on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa on the side of the drain region;

Step 6, forming a cap layer on the surface of the composite double gate dielectric layer;

Step 7: Using a fourth mask, a gate electrode is formed on the surface of the cap layer, and finally the NMOSFET is formed.

In an embodiment of the present invention, an ion implantation process is used to form a source region and a drain region on both sides of the β-Ga ₂ O ₃ mesa surface, including:

Using an ion implantation process to form source-drain lightly doped regions at opposite sides of the β-Ga ₂ O ₃ mesa surface;

An ion implantation process is used to form a heavily doped source and drain region at the edges of the lightly doped source and drain regions.

In one embodiment of the present invention, a second mask is used to form a first gate dielectric by magnetron sputtering on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa on the side of the source region. layers, including:

The second mask is used, Al material is selected as the sputtering target, argon and oxygen are used as the sputtering gas to pass into the sputtering chamber, and the slopes on the other two sides of the β-Ga ₂ O ₃ mesa are close to the sputtering chamber. Al ₂ O ₃ material is sputtered on the side of the source region to form the first gate dielectric layer.

In an embodiment of the present invention, a third mask is used, and a second gate dielectric is formed by magnetron sputtering on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa on the side of the drain region by sputtering layers, including:

_{The third} mask is used, Y ₂ O ₃ material is selected as the sputtering target, and argon and oxygen are used as sputtering gases to pass into the sputtering chamber. The second gate dielectric layer is formed by sputtering Y ₂ O ₃ material on the side of the inclined plane close to the drain region.

In an embodiment of the present invention, forming a cap layer on the surface of the composite double gate dielectric layer includes:

Using an ALD process, the cap layer is formed on the surface of the composite double gate dielectric layer with La source and plasma oxygen as precursor gases.

Another embodiment of the present invention provides a Ga ₂ O ₃ material-based compound double-gate NMOSFET, wherein the NMOSFET is formed by the method described in any of the above embodiments.

Yet another embodiment of the present invention provides a method for preparing a Ga ₂ O ₃ material-based compound double-gate NMOSFET, comprising:

Step 1. Use molecular beam epitaxy to grow a P-type β-Ga ₂ O ₃ layer on a P-type substrate of SiC or sapphire, and form a P-type β-Ga ₂ O ₃ mesa by a dry etching process to prepare an NMOSFET active area;

Step 2, using an ion implantation process to form a source region and a drain region on both sides of the β-Ga ₂ O ₃ mesa surface;

Step 3, forming a cap layer on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa;

Step 4, forming a first gate dielectric layer on the surface of the cap layer near the source region and forming a second gate dielectric layer on the side near the drain region to form a composite double gate dielectric layer;

Step 5, forming a gate electrode on the surface of the composite double gate dielectric layer, and finally forming the NMOSFET.

In an embodiment of the present invention, after the source region and the drain region are formed by ion implantation on both sides of the surface of the β-Ga ₂ O ₃ mesa, the method further includes:

A source electrode and a drain electrode are grown on the surfaces of the source region and the drain region, respectively.

Yet another embodiment of the present invention provides a Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap layer, wherein the NMOSFET is fabricated by the method described in any one of the above embodiments.

Compared with the prior art, the composite dual-gate high-speed NMOSFET of the embodiment of the present invention has at least the following advantages:

1. The NMOSFET of the present invention uses two materials with different dielectric constants as the compound gate oxide layer to transmit electrons and block holes, thereby effectively improving the transmission rate of electrons along the channel direction, and further effectively reducing the short channel effect and thermal load. The carrier effect increases the breakdown voltage and overcomes the shortcoming that the electron transfer rate is not high enough in the traditional double gate structure. The threshold voltage can be adjusted by selecting two materials in different combinations as the gate dielectric layer, which further exerts the inherent advantages of the double gate structure. The advantages of high transconductance, high carrier mobility, and good subthreshold slope characteristics.

2. In the NMOSFET of the present invention, a thin cap layer is introduced between the gate oxide layer and the metal gate electrode, or a thin cap layer is introduced between the Ga ₂ O ₃ substrate and the gate oxide layer. The high temperature process provides Mg, La, Dy, Al, Ba, Cs and other elements at the gate oxide layer/Ga ₂ O ₃ interface to form a dipole layer to realize the adjustment of the band edge work function. By changing the thickness of the cap layer and annealing conditions Further better adjustment of the threshold value can avoid the stack effect of the multi-layer metal gate electrode, and effectively alleviate the serious Fermi pinning effect between the metal gate and the high-k gate dielectric, and further improve the reliability of the device.

Description of drawings

FIG. 1 is a first schematic cross-sectional view of a Ga ₂ O ₃ material-based cap-layer composite double-gate NMOSFET according to an embodiment of the present invention;

FIG. 2 is a second schematic cross-sectional view of a Ga ₂ O ₃ material-based cap-layer compound double-gate NMOSFET according to an embodiment of the present invention;

3 is a third schematic cross-sectional view of a Ga ₂ O ₃ material-based cap-layer compound double-gate NMOSFET according to an embodiment of the present invention;

4 is a schematic top view of a Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap layer according to an embodiment of the present invention;

5 is a schematic flowchart of a method for preparing a Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap layer according to an embodiment of the present invention;

6a-61 are schematic diagrams of a method for preparing a Ga ₂ O ₃ material-based cap-layer composite double-gate NMOSFET according to an embodiment of the present invention;

FIG. 7 is a first schematic cross-sectional view of another Ga ₂ O ₃ material-based cap-layer compound double-gate NMOSFET according to an embodiment of the present invention;

8 is a second cross-sectional schematic diagram of another Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap layer provided by an embodiment of the present invention;

9 is a third schematic cross-sectional view of another Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap layer provided by an embodiment of the present invention;

10 is a schematic top view of another Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap layer according to an embodiment of the present invention;

11 is a schematic flowchart of another method for preparing a Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap layer according to an embodiment of the present invention;

12a-12k are schematic diagrams of another method for preparing a Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap according to an embodiment of the present invention;

13a-13b are schematic structural diagrams of a first mask set according to an embodiment of the present invention;

14a-14b are schematic structural diagrams of a second mask set according to an embodiment of the present invention;

15a-15b are schematic structural diagrams of a third reticle set according to an embodiment of the present invention; and

16a-16b are schematic structural diagrams of a fourth mask set according to an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Example 1

1, FIG. 2, FIG. 3 and FIG. 4, FIG. 1 is a first cross-sectional schematic diagram of a Ga ₂ O ₃ material-based compound double-gate NMOSFET according to an embodiment of the present invention (a plane formed along the XY axis) intercepted); Fig. 2 is a kind of second cross-sectional schematic diagram of a kind of Ga ₂ O ₃ material-based compound double-gate NMOSFET provided in the embodiment of the present invention (intercepted along the plane formed by the ZY axis, the viewing angle is: drain electrode→source electrode 3 is a third schematic cross-sectional view of a Ga ₂ O ₃ material-based cap-layer composite double-gate NMOSFET (taken along the plane formed by the ZY axis, the viewing angle is: source electrode→leakage current) provided by an embodiment of the present invention direction of the pole); FIG. 4 is a schematic top view of a Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap layer provided by an embodiment of the present invention. The cap layer compound double gate NMOSFET includes a gallium oxide mesa 1, a compound gate dielectric layer composed of a gate oxide layer 2 near the source end region and a gate oxide layer 3 near the drain end region, a cap layer 4, a double metal gate electrode 9, a source The drain lightly doped regions 7 and 8 , the source and drain heavily doped regions 11 and 12 , the source and drain electrodes 5 and 6 and the semi-insulating substrate 10 are composed.

The substrate is a P-type semi-insulating substrate SiC or sapphire, and the gallium oxide mesa is P-type β-Ga ₂ O ₃ (-201), P-type β-Ga 2 O 3 (-201), undoped or doped with elements such as Cu and Al. -Ga ₂ O ₃ (010) or P-type β-Ga ₂ O ₃ (001) material, with a thickness of 20-35 nm and a doping concentration of 10 ¹⁷ cm ^-3 level; the gate dielectric layer near the drain region is TiO ₂ Or Y ₂ O ₃ or HfO ₂ material; the gate dielectric layer close to the source region is Al ₂ O ₃ or SiO ₂ or Si ₃ N ₄ material; the capping layer is MgO or La ₂ O ₃ or Dy ₂ O ₃ and other materials containing group IIA, IIIB elements; the double gate electrode is Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, Pb and other metal materials, including these metals Two or more kinds of alloys or conductive compounds such as ITO are formed. In addition, it may have a two-layer structure composed of two or more different metals, such as Al/Ti. The source and drain heavily doped region doping elements can be Sn, Si or Al; the source and drain electrodes are Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, Metal materials such as Pb, alloys of two or more of these metals, or conductive compounds such as ITO are formed. In addition, it may have a two-layer structure composed of two or more different metals, such as Al/Ti.

Please refer to FIG. 5 , which is a schematic flowchart of a method for fabricating a Ga ₂ O ₃ material-based compound double-gate NMOSFET according to an embodiment of the present invention. The method includes the following steps:

Step 1. Select substrate SiC or sapphire substrate, use molecular beam epitaxy to grow P-type β-Ga ₂ O ₃ layer on P-type semi-insulating substrate SiC or sapphire, and form P-type β-Ga 2 O 3 layer by dry etching Ga ₂ O ₃ mesa to prepare the active region of NMOSFET;

Step 2, forming a source region and a drain region on both sides of the surface of the active region by using an ion implantation process;

Step 3, using a first mask, respectively growing a source electrode and a drain electrode on the slope of the β-Ga ₂ O ₃ mesa side;

Step 4. Using a second mask, a magnetron sputtering process is used to form a first gate dielectric layer on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa near the source region;

Step 5. Using a third mask, a second gate dielectric layer is formed by magnetron sputtering on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa near the drain region to form a composite double gate dielectric layer. gate dielectric layer;

Step 6, forming a cap layer on the surface of the composite double gate dielectric layer;

Step 7: Using a fourth mask, a gate electrode is formed on the surface of the cap layer, and finally the NMOSFET is formed.

For step 2, you can include:

Step 21 , forming lightly doped source and drain regions by ion implantation at the opposite sides of the β-Ga ₂ O ₃ mesa surface;

Step 22 , using an ion implantation process to form heavily doped source and drain regions at the edges of the lightly doped source and drain regions.

For step 4, you can include:

The second mask is used, Al material is selected as the sputtering target, argon and oxygen are used as the sputtering gas to pass into the sputtering chamber, and the slopes on the other two sides of the β-Ga ₂ O ₃ mesa are close to the sputtering chamber. The source region side is sputtered to form Al ₂ O ₃ material to form the first gate dielectric layer.

For step 5, you can include:

_{The third} mask is used, Y ₂ O ₃ material is selected as the sputtering target, and argon and oxygen are used as sputtering gases to pass into the sputtering chamber. The second gate dielectric layer is formed by sputtering Y ₂ O ₃ material on the side of the inclined plane close to the drain region.

For step 7, you can include:

Using an ALD process, the cap layer is formed on the surface of the composite double gate dielectric layer with La source and plasma oxygen as precursor gases.

In the embodiment of the present invention, two materials with different dielectric constants are used as the composite gate oxide layer to transport electrons and block holes, thereby effectively improving the transmission rate of electrons along the channel direction, and between the gate oxide layer and the metal gate A thinner cap layer is used in between, and a dipole layer is formed at the gate oxide layer/Ga ₂ O ₃ interface through a subsequent high-temperature process to realize the adjustment of the band-edge work function, and it is further improved by changing the thickness of the cap layer and annealing conditions. It can realize the adjustment of the threshold value and improve the reliability of the device.

Embodiment 2

Please refer to FIGS. 6a-6l and 13a-13b, 14a-14b, 15a-15b and 16a-16b together. Schematic diagram of the preparation method of the cap layer compound double-gate NMOSFET of ₂ O ₃ material, FIG. 13a-FIG. 13b is a schematic structural diagram of a first mask set provided by an embodiment of the present invention; FIG. 14a-FIG. 14b are an embodiment of the present invention Provided is a schematic structural diagram of a second reticle set; FIGS. 15a-15b are schematic structural diagrams of a third reticle set provided by an embodiment of the present invention; and FIGS. 16a-16b are provided by an embodiment of the present invention. A schematic diagram of the structure of a fourth mask group. . In this embodiment, on the basis of the above-mentioned embodiments, the preparation method of the Ga ₂ O ₃ material-based cap layer composite double-gate NMOSFET of the present invention is described in detail as follows:

Step 1: Referring to Figure 6a, prepare a P-type SiC or sapphire substrate 1 with a thickness of 350 μm, and perform RCA cleaning on the substrate.

Step 2: Referring to Figure 6b and Figure 6c, on the surface of the semi-insulating substrate prepared in Step 1, use molecular beam epitaxy to grow a β-Ga ₂ O ₃ layer 1 with a thickness of 20-35 nm and a doping concentration of 1×10 ¹⁷ cm ^-3 , Then, a β-Ga ₂ O ₃ mesa 1 is formed by dry etching.

Step 3: Referring to FIG. 6d, ion implantation is performed on both sides of the β-Ga ₂ O ₃ mesa 1 prepared in step 2, so that the regions on both sides are lightly doped source and drain regions 7 and 8, and the doping concentration is 1×10 ¹⁴ to 1×10 ¹⁶ cm ^-3 , and the implanted ions can be Sn, Si or Al.

Referring to FIG. 6e , heavily doped source and drain regions 11 and 12 are formed at the edges of the lightly doped source and drain regions using an ion implantation process. The concentration of the heavily doped region is, for example, 1×10 ¹⁸ to 1×10 ²⁰ cm ⁻³ , and the implanted ions can be Cu or N and Zn co-doped.

Step 4: Referring to Figure 6f and Figure 13a-13b, use a first mask on the heavily doped β-Ga ₂ O ₃ regions on the left and right sides prepared in Step 2 to form source-drain electrodes by magnetron sputtering of Au 5, 6, and annealing to form ohmic contacts. Among them, Figure 13a is the mask of the drain electrode, and Figure 13b is the mask of the source electrode. Since the entire substrate surface is a mesa structure, the mask is prevented from bending, and the small size as shown in the figure is used in the slope part. Mask, use clean paper on the area not covered by mask.

The sputtering target is made of gold with a mass ratio of purity > 99.99%, and Ar with a mass percentage purity of 99.999% is used as the sputtering gas to pass into the sputtering chamber. Rinse for 5 minutes and then vacuum. Under the conditions of vacuum degree of 6×10 ^-4 -1.3×10 ^-3 Pa, argon flow rate of 20-30cm ³ /sec, target base distance of 10cm and working power of 20W-100W, source-drain electrode gold was prepared , the electrode thickness is 40nm-100nm. After the sputtering is completed, rapid thermal annealing is performed at 500 °C for 3 min in a nitrogen or argon atmosphere.

The metal of the source and drain electrodes 5 and 6 can be selected from different elements such as Au, Al, Ti and its 2-layer structure. The source and drain electrodes can be replaced by metals such as Al, Ti, Ni, Ag, Pt, etc., but the magnetic field needs to be changed after replacement. Control sputtering process parameters. Among them, Au, Ag, and Pt have stable chemical properties; Al, Ti, and Ni have low cost.

Step 5: Referring to Figure 6g and Figure 14a-14b, use a second mask on the slopes on the other two sides of the P-type β-Ga ₂ O ₃ mesa prepared in Step 1, and use a second mask to sputter Al near the source end by magnetron sputtering The ₂ O ₃ gate oxide layer forms the first gate dielectric layer 2 . Fig. 14a is a mask with one of the slopes, and Fig. 14b is a mask with another slope. The top plane of the mesa-like structure is also treated with clean paper.

The sputtering target is an aluminum target with a mass ratio of purity > 99.99%, and argon and oxygen with a mass percentage purity of 99.999% are used as the sputtering gas to pass into the sputtering chamber. Before sputtering, high-purity argon is used for magnetron sputtering. The cavity of the injection device was cleaned for 5 minutes, and then vacuumed. ^{Prepare close to} The Al ₂ O ₃ gate oxide layer 2 at the source end has a thickness of 5nm-15nm.

The gate oxide layer near the source can be replaced by SiO ₂ or Si ₃ N ₄ material. However, after the replacement, the effect of improving the electron transmission rate becomes poor, and the magnetron sputtering has to replace the target and modify various process parameters.

Step 6: Referring to Figure 6h and Figure 15a-15b, use a third mask on the slopes on the other two sides of the P-type β-Ga ₂ O ₃ mesa prepared in Step 1 to sputter TiO near the drain end by magnetron sputtering ₂ The gate oxide layer is used as the second gate dielectric layer 3. Fig. 15a is a mask of one of the inclined planes, and Fig. 15b is a mask of the other inclined plane. The top plane of the mesa-like structure is also treated with clean paper.

The sputtering target is a Y ₂ O ₃ ceramic target with a mass ratio of purity > 99.99%, and oxygen and argon with a mass percentage purity of 99.999% are used as the sputtering gas to pass into the sputtering chamber. The chamber of the magnetron sputtering equipment was cleaned for 5 minutes, and then evacuated. Under the conditions of vacuum degree of 6×10 ^-4 -1.3×10 ^-3 Pa, oxygen and argon flow rates of 20-30cm ³ /sec, target base distance of 10cm, and working power of 40W-70W, the near leakage was prepared. The gate oxide layer at the end is TiO ₂ , and the thickness of the gate oxide layer is the same as that in step 3.

The gate oxide layer near the source can be replaced by TiO ₂ or HfO ₂ material. However, after the replacement, the effect of improving the electron transmission rate becomes poor, and the magnetron sputtering has to replace the target and modify various process parameters.

Step 7: Referring to FIG. 6i and FIG. 6j, atomically deposit a layer of La ₂ O ₃ material on the compound gate oxide layer to form a cap layer 4 .

The atomic layer deposition (ALD) process is used to deposit on the composite gate oxide layer obtained in step 6. La source and plasma oxygen are used as precursors to prepare a cap layer. After chemical mechanical polishing, the surface is smoothed, and the thickness of the cap layer is 0.5-3nm.

The cap layer can be selected from materials containing Group IIA and IIIB elements such as MgO or Dy ₂ O ₃ , which can be realized by the MBE process, which controls the thickness of the cap layer 4 relatively accurately. Of course, it can also be realized by magnetron sputtering, PVD, MOCVD and other processes, but the thickness of the cap layer cannot be precisely controlled.

Step 8: Referring to FIG. 6k, FIG. 6l, and FIGS. 16a-16b, using a fourth mask, magnetron sputtering gate electrode gold material 9 on the cap layer 4. Fig. 16a is a mask with one of the slopes, and Fig. 16b is a mask with another slope. The top plane of the mesa structure is also treated with clean paper.

A fourth mask is used on the cap layer 4 obtained in step 6 by the magnetron sputtering process, and the gate electrode Au is grown by magnetron sputtering. The sputtering target is selected from gold with a mass ratio of purity > 99.99%, and the mass percentage purity is 99.999% Ar was passed into the sputtering chamber as a sputtering gas. Before sputtering, the chamber of the magnetron sputtering equipment was cleaned with high-purity argon gas for 5 minutes, and then evacuated. Under the conditions of vacuum degree of 6×10 ^-4 -1.3×10 ^-3 Pa, argon flow rate of 20-30cm ³ /sec, target base distance of 10cm and working power of 20W-100W, the gate electrode gold was prepared, The electrode thickness is 40nm-100nm.

The metal of the gate electrode can be selected from different elements such as Au, Al, Ti and the 2-layer structure of its composition, and the gate electrode can be replaced by metal such as Al\Ti\Ni\Ag\Pt. Among them, Au\Ag\Pt has stable chemical properties; Al\Ti\Ni has low cost.

Embodiment 3

Please refer to FIGS. 7 , 8 , 9 and 10 . FIG. 7 is a first cross-sectional schematic diagram of another Ga ₂ O ₃ material-based compound double-gate NMOSFET (formed along the XY axis) according to an embodiment of the present invention. Plane interception); FIG. 8 is a second cross-sectional schematic diagram of another kind of Ga ₂ O ₃ material-based compound double-gate NMOSFET provided by the embodiment of the present invention (taken along the plane formed by the ZY axis, the viewing angle is: drain electrode→ The direction of the source electrode); Fig. 9 is the third cross-sectional schematic diagram of another kind of Ga ₂ O ₃ material-based compound double gate NMOSFET provided by the embodiment of the present invention (taken along the plane formed by the ZY axis, the viewing angle is: source direction of electrode→drain electrode); FIG. 10 is a schematic top view of another Ga ₂ O ₃ material-based compound double-gate NMOSFET provided in an embodiment of the present invention. The compound double gate NNMOSFET includes: a gallium oxide mesa 1, a compound gate dielectric layer composed of a gate oxide layer 2 near the source end region and a gate oxide layer 3 near the drain end region, a cap layer 4, a double metal gate electrode 9, source and drain The heavily doped regions 7 and 8 , the heavily doped source and drain regions 11 and 12 , the source and drain electrodes 5 and 6 and the substrate 10 are composed. The specific description of each component should be consistent with the above-mentioned first embodiment, and will not be repeated here.

Referring to FIG. 11 , FIG. 11 is a schematic flowchart of another method for fabricating a Ga ₂ O ₃ material-based compound double-gate NMOSFET with a cap layer according to an embodiment of the present invention. The preparation method comprises the following steps:

Step 1. Select substrate SiC or sapphire substrate, use molecular beam epitaxy to grow P-type β-Ga ₂ O ₃ layer on P-type semi-insulating substrate SiC or sapphire, and form P-type β-Ga 2 O 3 layer by dry etching Ga ₂ O ₃ mesa to prepare the active region of NMOSFET;

Step 2, using an ion implantation process to form a source region and a drain region on both sides of the β-Ga ₂ O ₃ mesa surface;

Step 3, forming a cap layer on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa;

Step 4, forming a first gate dielectric layer on the surface of the cap layer near the source region and forming a second gate dielectric layer on the side near the drain region to form a composite double gate dielectric layer;

Step 5, forming a gate electrode on the surface of the composite double gate dielectric layer, and finally forming the NMOSFET.

Wherein, after step 2, it can also include:

A source electrode is grown on the side of the β _{- Ga2O3} mesa surface near the source region and a drain electrode is grown on the side near the drain region.

Wherein, step 4 may include:

Step 41 , using a second mask to form a first gate dielectric layer on the surface of the cap layer by using a magnetron sputtering process near the source region by sputtering;

Step 42: Using a third mask, a magnetron sputtering process is used on the surface of the cap layer to form a second gate dielectric layer on the side close to the drain region to form a composite double gate dielectric layer.

In the embodiment of the present invention, by using two materials with different dielectric constants as the compound gate oxide layer to transport electrons and block holes, the electron transport rate along the channel direction is effectively improved, and the electrons are transported between the Ga ₂ O ₃ substrate and the gate. A thinner cap layer is used between the oxide layers, and a dipole layer is formed at the gate oxide layer/Ga ₂ O ₃ interface through a subsequent high-temperature process to adjust the band-edge work function, and by changing the thickness of the cap layer and annealing conditions The adjustment of the threshold value is further better realized and the electron transfer rate is improved, and the reliability of the device is improved.

Embodiment 4

Please refer to FIGS. 12a-12k, 13a-13b, 14a-14b, 15a-15b, and 16a-16b. Schematic diagram of the preparation method of the Ga ₂ O ₃ material cap-layer composite double-gate NMOSFET In this embodiment, the preparation of the present invention is described in detail on the basis of the above-mentioned third embodiment:

Step 1: Referring to Figure 12a, prepare a P-type sapphire or SiC substrate 1 with a thickness of 350 μm, and perform RCA cleaning on the substrate. This step is similar to step 1 corresponding to the second embodiment, and will not be repeated here.

Step 2: Referring to Figure 12b and Figure 12c, on the surface of the semi-insulating substrate prepared in Step 1, use molecular beam epitaxy to grow a β-Ga ₂ O ₃ layer 1 with a thickness of 20-35 nm and a doping concentration of 1×10 ¹⁷ cm ^-3 , Then, a β-Ga ₂ O ₃ mesa 1 is formed by dry etching.

Step 3: Referring to Figure 12d and Figure 12e, ion implantation is performed on both sides of the surface of the P-type β-Ga ₂ O ₃ mesa 1 prepared in Step 2, and the two sides are doped so that the regions on both sides are lightly doped source and drain regions 7 and 8 , the doping concentration is 1×10 ¹⁴ to 1×10 ¹⁶ cm ^-3 , and the implanted ions can be Sn, Si or Al.

The heavily doped source and drain 11 and 12 are formed at the edges of the lightly doped source and drain regions by using an ion implantation process. The concentration of the heavily doped region is, for example, 1×10 ¹⁸ to 1×10 ²⁰ cm ⁻³ , and the implanted ions can be Sn, Si or Al.

Step 4: Referring to Figure 12f and Figure 13a-13b, use a first mask on the heavily doped β-Ga ₂ O ₃ regions on the left and right sides prepared in Step 3 to sputter Au source-drain electrodes 5 by magnetron , 6, and annealing to form ohmic contacts. This step is similar to step 4 corresponding to the second embodiment, and will not be repeated here.

Step 5: Referring to FIG. 12g, a layer of La ₂ O ₃ material is deposited on the other two sides of the inclined plane atomic layer of the β-Ga ₂ O ₃ mesa 1 prepared in step 2, and then chemical mechanical polishing is performed to form a cap layer 4.

An atomic layer deposition (ALD) process is used to prepare a cap layer 4 with La source and plasma oxygen as precursors. The surface is smoothed by chemical mechanical polishing, and the thickness of the cap layer is 0.5-2 nm. This step is similar to step 7 corresponding to the second embodiment, and will not be repeated here.

Step 6: Please refer to Fig. 12i and Fig. 14a-Fig. 14b, use a second mask on the capping layer 4 prepared in step 4, and use the Al ₂ O ₃ gate oxide layer close to the source end by magnetron sputtering as the first gate dielectric layer 2. This step is similar to step 5 corresponding to the second embodiment, and will not be repeated here.

Step 7: Please refer to Figure 12h and Figure 15a-15b, use a third mask on the cap layer prepared in Step 4, and use the TiO ₂ gate oxide layer close to the drain end by magnetron sputtering as the second gate dielectric layer 3 , the surface was smoothed by chemical mechanical polishing after growth. This step is similar to step 6 corresponding to the second embodiment, and will not be repeated here.

Step 8: Referring to FIG. 12j and FIG. 16a-FIG. 16b, using a fourth mask, magnetron sputtering gold material on the composite gate oxide layer to form gate electrode 9. This step is similar to step 7 corresponding to Embodiment 2 to 8, and is not repeated here.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (9)

1. a preparation method based on Ga ₂ O ₃ material of the cap layer compound double gate NMOSFET, is characterized in that, comprises: Step 1. Select a semi-insulating substrate, grow a P-type β-Ga ₂ O ₃ layer on the surface of the semi-insulating substrate by molecular beam epitaxy, and form a P-type β-Ga ₂ O ₃ mesa by dry etching ; Step 2, using an ion implantation process to form a source region and a drain region on both sides of the β-Ga ₂ O ₃ mesa surface; Step 3. Using a first mask, grow source electrodes and drain electrodes on the slopes on the sides of the source and drain regions, respectively; Step 4. Using a second mask, a first gate dielectric layer is formed by magnetron sputtering on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa on the side of the source region; Step 5. Using a third mask, use a magnetron sputtering process on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa to form a second gate dielectric layer on the side of the drain region to form a compound double gate a dielectric layer, wherein the dielectric constant of the second gate dielectric layer is different from that of the first gate dielectric layer; Step 6, forming a cap layer on the surface of the composite double gate dielectric layer; Step 7: Using a fourth mask, a gate electrode is formed on the surface of the cap layer, and finally the NMOSFET is formed. 2. The method according to claim 1, wherein the source region and the drain region are formed by an ion implantation process on both sides of the β-Ga ₂ O ₃ mesa surface, comprising: Using an ion implantation process to form source-drain lightly doped regions at opposite sides of the β-Ga ₂ O ₃ mesa surface; An ion implantation process is used to form a heavily doped source and drain region at the edges of the lightly doped source and drain regions. 3 . The method according to claim 1 , wherein a second mask is used to sputter on the source region side by a magnetron sputtering process on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa. 4 . forming a first gate dielectric layer by injection, including: The second mask is used, Al material is selected as the sputtering target, argon and oxygen are used as the sputtering gas to pass into the sputtering chamber, and the slopes on the other two sides of the β-Ga ₂ O ₃ mesa are close to the sputtering chamber. Al ₂ O ₃ material is sputtered on the side of the source region to form the first gate dielectric layer. 4 . The method according to claim 1 , wherein a third mask is used to sputter on the side of the drain region by a magnetron sputtering process on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa. 5 . forming a second gate dielectric layer by injection, including: _{The third} mask is used, Y ₂ O ₃ material is selected as the sputtering target, and argon and oxygen are used as sputtering gases to pass into the sputtering chamber. The second gate dielectric layer is formed by sputtering Y ₂ O ₃ material on the side of the inclined plane close to the drain region. 5. The method according to claim 1, wherein forming a cap layer on the surface of the composite double gate dielectric layer comprises: Using an ALD process, the cap layer is formed on the surface of the composite double gate dielectric layer with La source and plasma oxygen as precursor gases. 6 . A compound double-gate NMOSFET with a cap layer based on Ga ₂ O ₃ material, wherein the NMOSFET is prepared by the method according to any one of claims 1-5. 7 . 7. a preparation method based on Ga ₂ O ₃ material cap layer compound double gate NMOSFET, is characterized in that, comprising: Step 1. A P-type β-Ga ₂ O ₃ layer is grown on a SiC or sapphire P-type substrate by molecular beam epitaxy, and a P-type β-Ga ₂ O ₃ mesa is formed by a dry etching process to prepare an NMOSFET active area; Step 2, using an ion implantation process to form a source region and a drain region on both sides of the β-Ga ₂ O ₃ mesa surface; Step 3, forming a cap layer on the slopes on the other two sides of the β-Ga ₂ O ₃ mesa; Step 4, forming a first gate dielectric layer on the surface of the cap layer near the source region and forming a second gate dielectric layer on the side near the drain region to form a composite double gate dielectric layer, wherein the second gate dielectric layer is The dielectric constant of the gate dielectric layer is different from that of the first gate dielectric layer; Step 5, forming a gate electrode on the surface of the composite double gate dielectric layer, and finally forming the NMOSFET. 8 . The method according to claim 7 , wherein after the source region and the drain region are formed by an ion implantation process on both sides of the β-Ga ₂ O ₃ mesa surface, the method further comprises: A source electrode and a drain electrode are grown on the surfaces of the source region and the drain region, respectively. 9 . A cap-layer compound double-gate NMOSFET based on Ga ₂ O ₃ material, characterized in that, the cap-layer compound double-gate NMOSFET is formed by the method of any one of claims 7-8. 10 .

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