CN106847332B - SRAM (static random Access memory) storage unit SEL (self-adaptive selection) reinforcing method with low resource consumption - Google Patents
SRAM (static random Access memory) storage unit SEL (self-adaptive selection) reinforcing method with low resource consumption Download PDFInfo
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- CN106847332B CN106847332B CN201611203359.4A CN201611203359A CN106847332B CN 106847332 B CN106847332 B CN 106847332B CN 201611203359 A CN201611203359 A CN 201611203359A CN 106847332 B CN106847332 B CN 106847332B
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- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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Abstract
A low-resource-consumption SRAM memory cell SEL reinforcing method comprises the steps of firstly, isolating an NMOS (N-channel metal oxide semiconductor) tube and a PMOS (P-channel metal oxide semiconductor) tube by using a trap contact of the SRAM memory cell, reinforcing the PMOS tube by using an unsealed protection ring, connecting a source level of the PMOS tube by using the unsealed protection ring, reinforcing the NMOS tube in the SRAM memory cell by using a non-U-shaped protection belt, and punching a plurality of contact holes on the unsealed protection ring and the non-U-shaped protection belt on the premise of meeting process rules; adjusting the distance between an unsealed protection ring adopted by a PMOS tube and a non-U-shaped protection belt adopted by an NMOS tube in an SRAM memory unit, and finally optimizing the distance between the PMOS tube and the NMOS tube active area; and adding an NC layer in an NMOS tube region in the SRAM memory cell to improve the threshold voltage of the NMOS tube. Compared with the prior art, the method has the advantages of low area overhead and low wiring resource consumption, reduces the resource consumption of the storage array formed by the storage units in the SRAM, and has good use value.
Description
Technical Field
The invention relates to the technical field of CMOS integrated circuit space single event effect protection, in particular to a method for reinforcing an SRAM (static random access memory) storage unit SEL with low resource consumption.
Background
The single-particle latch-up effect (SEL) is caused by that high-energy particles are incident into a CMOS integrated circuit to cause the potential in a well to change, so that a parasitic triode with an n-p-n-p structure as shown in fig. 1 and 2 is turned on, and a latch-up path with a positive feedback loop is turned on, so that the local current is continuously increased to cause locking. Due to the high density layout of SRAM memory arrays, embedded SRAMs are more prone to SEL than standard cells in ASIC chips.
At present, SEL layout reinforcement aiming at an SRAM memory cell is usually realized by adopting a protection belt or a protection ring, the protection belt is realized by respectively using U-shaped P-well contact and N-well contact for NMOS and PMOS areas of the memory cell, the area of the reinforcement method is usually increased to about 50% of that of a non-reinforced memory cell, although the memory cell does not need additional metal wires, the memory array is complicated to splice due to the influence of the protection belt, the realization of the additional metal wires is needed, the wiring complexity of the whole SRAM is increased, the internal crosstalk of the SRAM is increased, the performance such as speed and reliability is reduced, the resource consumption is increased, and the protection effect of the method is limited; the protection ring is realized by wrapping the NMOS and PMOS regions of the memory unit by the P-well contact ring and the N-well contact ring, the strengthening method has strong SEL resistance, but for the protection ring design of the memory unit, the area overhead generally reaches about 100% of that of the non-strengthened memory unit, and the memory unit needs additional metal wires, so that the SRAM strengthened by the protection ring is more complex than the SRAM whole layout wires strengthened by the protection belt, the crosstalk is larger, the performances such as speed, reliability and the like are reduced more, and the larger resource consumption is brought. Since the bank of memory cells occupies most of the area of the SRAM, the area of the memory cells directly determines the area of the SRAM. With the increasing area of the SRAM in the ASIC chip, the performance of the whole chip is directly determined by the area, speed, reliability and other performances of the SRAM.
Disclosure of Invention
The technical problem solved by the invention is as follows: the method overcomes the defects of the prior art, provides the SRAM memory cell SEL reinforcing method with low resource consumption, and solves the problems that the area of the conventional reinforcing method is increased more, splicing is complex, extra metal wires are needed for realization, the wiring complexity of the whole SRAM is increased, the internal crosstalk of the SRAM is increased, and the performances such as speed and reliability are reduced.
The technical solution of the invention is as follows: a low-resource-consumption SRAM memory cell SEL reinforcing method comprises the following steps:
(1) well contact is used for isolating an NMOS tube and a PMOS tube for an SRAM memory unit, an unsealed protection ring is used for reinforcing the PMOS tube, and the unsealed protection ring is used for connecting the source level of the PMOS tube;
(2) reinforcing an NMOS tube in an SRAM memory unit by adopting a non-U-shaped guard band method, and punching a plurality of contact holes on an unsealed guard ring and the non-U-shaped guard band on the premise of meeting process rules;
(3) setting the distance between an unsealed protection ring adopted by a PMOS tube and a non-U-shaped protection belt adopted by an NMOS tube in an SRAM memory unit to be 3.9 um;
(4) the distance between the PMOS tube and the NMOS tube active area is larger than 1.3 um;
(5) and adding an NC layer in an NMOS tube region in the SRAM memory cell to improve the threshold voltage of the NMOS tube.
In the step (1), the trap contact is used for isolating the NMOS tube and the PMOS tube, and the DRC (design rule check) rule is required to be met.
Under the condition of meeting the process rule and not influencing normal wiring, contact holes are punched on the unsealed protection ring and the non-U-shaped protection belt as many as possible.
And (5) adding an NC layer to an NMOS tube area in the SRAM memory unit so as to increase the threshold voltage of the NMOS tube by 0.1V.
Compared with the prior art, the invention has the advantages that:
(1) the SEL reinforcing method combining the protection ring, the protection belt and the high-threshold voltage NMOS tube is provided by analyzing the SEL generation mechanism, the SEL reinforcing method is used for carrying out SEL reinforcing on the embedded SRAM storage unit of the 0.13um commercial bulk silicon CMOS process, and the SEL reinforcing method has the advantages of small storage unit area, easiness in splicing, strong SEL resistance and high reliability;
(2) compared with the prior art, the SRAM storage unit SEL reinforcing method has the advantages of low area overhead, low wiring resource consumption and reduced SRAM storage unit resource consumption.
Drawings
FIG. 1 is a parasitic latch-up structure in a bulk silicon CMOS process;
FIG. 2 is an equivalent circuit diagram of a parasitic latch-up structure in a bulk silicon CMOS process;
FIG. 3 is a layout of SRAM memory cells;
FIG. 4 is a 0.13um CMOS process standard cell layout;
FIG. 5 is a SRAM memory cell layout after SEL reinforcement;
FIG. 6 is a simulation result of high energy particle transport in the nmos region;
FIG. 7 is a result of a pmos high energy particle transport simulation;
FIG. 8 is a flow chart of a method for reinforcing an SRAM memory cell SEL with low resource consumption.
Detailed Description
In order to design an aerospace SRAM which meets the SEL resistance index of aerospace application and has low resource consumption, the invention provides a storage unit reinforcing method which has strong SEL resistance, low area overhead and no extra wiring and is convenient to splice, the SEL resistance and the area overhead are reasonably analyzed, the SEL sensitivity of different parts of the SRAM storage unit is combined with splicing of an SRAM array, the SEL reinforcement of the storage unit is realized by combining a protection ring, a protection belt and a high threshold voltage NMOS tube, the storage unit designed by the design method has small area, easy splicing, strong SEL resistance and high reliability, and the method comprises the following steps as shown in figure 8:
(1) analyzing the intrinsic SEL capability of an NMOS tube and a PMOS tube of the storage unit, and combining array splicing to realize a well contact reinforcement (protective belt and protective ring) scheme for designing a storage unit layout;
because the parasitic resistivity of the PMOS tube region is high, the voltage drop caused by the incidence of high-energy particles is large, so that the SEL circuit is easier to open relative to the NMOS tube region, and the SEL is easier to occur in the region, and therefore, a well contact design with a larger area is needed for the PMOS tube region to reduce the parasitic resistance. Considering the area of the layout and the high-density array splicing, the PMOS tube is reinforced by the unsealed protection ring shown in the figure 3, on the premise of meeting DRC (Design Rule Check) rules (Design Rule Check), the NMOS tube and the PMOS tube are isolated by using well contact to the maximum extent, and meanwhile, the source level of the PMOS tube in the layout is connected with the unsealed protection ring, so that the current caused by high-energy particles entering the transistor can be effectively absorbed, and the risk of latch locking caused by single particle current is reduced; the NMOS tube is reinforced by the non-U-shaped protective belt shown in figure 3, the parasitic resistance value on the parasitic NPN tube is reduced by the protective belt, and meanwhile, the non-U-shaped protective belt structure enables the memory cells to be spliced into the memory array without extra metal layer routing. Under the condition of meeting the process rule and not influencing normal wiring, contact holes are formed in the unsealed protection ring and the non-U-shaped protection band, so that the substrate resistance and the trap resistance can be reduced, the contact holes are formed in dark gray squares in the graph 3, and the more the contact holes are, the smaller the parallel resistance value is. Compared with the traditional U-shaped protective belt, the effect of isolating the NMOS tube and the PMOS tube is better, and extra metal layer routing is not needed during layout splicing.
(2) The cell area is further compressed by combining the transistor size of the storage unit and the well contact reinforcement scheme of the layout, and the distance parameter between the protective bands is set, so that the SEL resistance is improved;
in fig. 3, the height H of the memory cell is 2 times of the distance between the protection rings of the PMOS transistor, and by reducing the distance, the energy of the high-energy particles incident into the MOS transistor can be effectively absorbed, so as to reduce the probability of triggering latch by the high-energy particles, and at the same time, the area of the active region in the protection ring can be reduced, thereby reducing the gain of the parasitic transistor. However, the performance influence of the increase of the cell area and the delay is brought by the too small distance of the protective band, and TCAD simulation shows that when the distance is less than 3.9um, SEL is easy to occur in CMOS with 0.13um technology. By combining the transistor size of the memory unit and the well contact reinforcement scheme of the layout, the layout design ensures that the distance between the unsealed protection ring adopted by the unit PMOS tube and the non-U-shaped protection band of the NMOS tube in the memory array spliced by the memory unit is less than 3.9um on the premise of not increasing the unit height.
(3) Setting parameters of the distance between the NMOS active region and the PMOS active region by combining a protection band of an SRAM storage unit, a protection ring scheme, an array layout structure and the size of a peripheral circuit, so that the SEL resistance can meet the aerospace index;
fig. 3 shows the distance between the active regions of the PMOS and NMOS transistors, and increasing the distance is equivalent to increasing the base width of the lateral parasitic NPN transistor, thereby reducing the gain of the parasitic transistor and reducing the probability of latch-up. However, the larger the distance between the active regions of the MOS transistors is, the performance influence such as the increase of the layout width, the increase of the area, the increase of the delay, and the like of the memory cell can be caused, and TCAD simulation finds that when the distance is smaller than 0.7um, the CMOS of the 0.13um process is prone to SEL. According to the SRAM unit corresponding to the invention, by combining the layout size of the peripheral circuit, the layout of the storage array and the size of the storage body pull-down tube, on the premise of not influencing the function and the working speed of the SRAM, the distance is larger than 1.3um through smaller area loss, and the protection effect is enhanced.
(4) The anti-SEL capability is further improved by adopting an NMOS transistor with high threshold voltage, and the aerospace anti-SEL index is met;
all NMOS tubes in the SRAM memory unit use NMOS tubes with high threshold voltage, and the threshold voltage is changed by substrate doping, because the NMOS tubes are P-type substrates, the higher the substrate doping concentration is, the higher the concentration of majority carriers is, so that the higher the voltage required by substrate surface depletion and inversion is, namely, the threshold voltage is increased. The higher doping concentration reduces the parasitic resistance added in front of the parasitic transistor, increases the starting voltage of the parasitic transistor and reduces the occurrence probability of single event latch-up. The NMOS (the threshold voltage is increased by 0.1V compared with the normal value) transistor with high threshold voltage is realized by adding an NC (high threshold voltage layer) layer in the area of the NMOS transistor during layout design.
The SEL reinforcing method adopts a method of combining the protection ring, the protection band and the NMOS transistor with high threshold voltage to realize SEL reinforcing, and compared with the traditional reinforcing method, the SEL reinforcing method reduces the unit area on the premise of meeting the aerospace SEL index, does not need to use extra wires to realize the splicing of the storage array, and improves the performance of the SEL reinforcing SRAM.
A0.13 um commercial bulk silicon CMOS process SRAM memory cell layout is shown in FIG. 4, the cell uses 4 layers of metal, the cell length is 3.005um, the cell width is 2.3um, and the latch-up effect is easy to occur under the condition of space single particle irradiation by the structural design of the cell layout.
The unit layout reinforced and protected by the method of the invention is shown in fig. 5, the memory unit of the invention uses 4 layers of metal, no additional metal wiring is needed when the layout is spliced, the unit length is 3.9 μm, the width is 2.3um, and the area increase is only more than 32% of that of a commercial SRAM.
Aiming at the SRAM memory cell which is designed by adopting the method and reinforced in the 0.13um CMOS process, TCAD modeling simulation analysis is carried out, the single event latch resistance of the SRAM memory cell is predicted, and the worst condition considered in simulation comprises the following steps:
temperature: high temperature 125 ℃;
working voltage: 1.4V (0.13 um);
normal incidence particle equivalent LET: 120MeV/mg/cm2；
For the NMOS transistor region, where the NMOS of a single memory cell is far from the well contact and the N-well P-well contact region, there are 5 particles with an equivalent LET of 120MeV/mg/cm2, and the simulation result of high energy particle transport at 125 ℃ and 1.4V is shown in fig. 6.
For the PMOS region of a single memory cell, latching is easy to occur far away from the well contact and near to nmos, so 2 particles with equivalent LET of 120MeV/mg/cm2 are hit at the PMOS part far away from the well contact, and the simulation result of high-energy particle transport at 1.4V and 125 ℃ is shown in FIG. 7.
The results of fig. 6 and fig. 7 show that, in the region where the memory cell is prone to latch-up, after the incidence of the high-energy particles, the transistor reinforced and designed by the method returns to normal after the occurrence of a short large current pulse, and no latch-up occurs.
The specific design flow of the standard unit for resisting the single event latch is as follows:
(1) analyzing the occurrence mechanism of single particle latch, summarizing the occurrence of single particle latch in CMOS circuit, and satisfying three conditions: a. the power supply provides a sustain voltage greater than or equal to a sustain latch-up. b. The potential change caused by the incidence of the energetic ions is sufficient to turn on the parasitic transistor. c. The gain product of the parasitic pnp and npn transistors is greater than 1.
(2) The study summarizes existing SEL hardening techniques and SEL hardening techniques for memory cells in SRAM.
(3) And (3) specifically analyzing the intrinsic SEL resistance of the NMOS area and the PMOS area by combining the process parameters of a commercial 0.13um bulk silicon CMOS process, and determining a protective band protection ring scheme and specific design parameters of the NMOS and the PMOS.
(4) And designing a storage array layout by combining array splicing, scheme parameters of a protective belt and a protective ring and distance parameters of the NMOS region and the PMOS region.
(5) And combining the transistor size of the storage unit and the well contact scheme of the layout, further compressing the unit area, setting distance parameters between protective strips, and improving the SEL resistance of the storage unit by using a high-threshold voltage NMOS tube to complete the layout design of the storage unit.
(6) And performing array splicing by using the designed unit layout, and performing post-simulation on functional performances such as read-write capability, noise tolerance and the like on the storage unit after determining that no DRC error exists.
(7) And respectively carrying out SEL simulation on the NMOS area and the PMOS area of the designed memory cell layout to prove the SEL resistance of the designed cell.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (3)
1. A method for reinforcing an SRAM memory unit SEL with low resource consumption is characterized by comprising the following steps:
(1) the method comprises the following steps of isolating an NMOS (N-channel metal oxide semiconductor) tube and a PMOS (P-channel metal oxide semiconductor) tube by using a well contact of an SRAM (static random access memory) storage unit, reinforcing the PMOS tube by using a G-shaped protection ring, and connecting the G-shaped protection ring with a source level of the PMOS tube to absorb current caused by high-energy particles incident to the PMOS tube so as to reduce the risk of latch-up caused by single-particle current; two adjacent G-shaped protection rings share one edge, and the two G-shaped protection rings are axially symmetrical along the shared edge;
(2) the NMOS tube in the SRAM memory cell is reinforced by a T-shaped protective belt method, the parasitic resistance value added on the parasitic NPN tube is reduced by the T-shaped protective belt, and meanwhile, no extra metal layer routing is needed when the memory cells are spliced into a memory array; under the premise of meeting the process rule, multiple contact holes are formed in the G-shaped protection ring and the T-shaped protection ring;
(3) setting the distance between a G-shaped protection ring adopted by a PMOS tube and a T-shaped protection band adopted by an NMOS tube in an SRAM memory unit to be 3.9 um;
(4) the distance between the PMOS tube and the NMOS tube active area is larger than 1.3 um;
(5) adding NC layer in NMOS tube area in SRAM memory unit makes threshold voltage of NMOS tube increase 0.1V.
2. The SRAM memory cell SEL strengthening method with low resource consumption as claimed in claim 1, wherein: in the step (1), the trap contact is used for isolating the NMOS tube and the PMOS tube, and the DRC (design rule check) rule is required to be met.
3. The SRAM memory cell SEL reinforcing method with low resource consumption as claimed in claim 1 or 2, wherein: under the condition of meeting the process rule and not influencing normal wiring, contact holes are punched on the G-shaped protection ring and the T-shaped protection ring as many as possible.
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| CN101707210B (en) * | 2009-11-27 | 2012-05-30 | 北京大学 | Anti-radiation field effect transistor, CMOS integrated circuit and preparation thereof |
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| Study of SEL and SEU in SRAM using different laser techniques;Dmitry V. Savchenkov;《2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS)》;20141030;全文 * |
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