CN106845583A - For improving the hyperfrequency card sender to label frequency deviation fault-tolerant ability - Google Patents
For improving the hyperfrequency card sender to label frequency deviation fault-tolerant ability Download PDFInfo
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- CN106845583A CN106845583A CN201710073787.8A CN201710073787A CN106845583A CN 106845583 A CN106845583 A CN 106845583A CN 201710073787 A CN201710073787 A CN 201710073787A CN 106845583 A CN106845583 A CN 106845583A
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- Prior art keywords
- group
- frequency
- zero crossing
- frequency deviation
- radio
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K17/00—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations
- G06K17/0003—Automatic card files incorporating selecting, conveying and possibly reading and/or writing operations
- G06K17/0006—Automatic card files incorporating selecting, conveying and possibly reading and/or writing operations with random access selection of a record carrier from the card-file, e.g. the carriers are suspended on the selection device which in part of the card magazine
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
- G06K7/14—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation using light without selection of wavelength, e.g. sensing reflected white light
- G06K7/1404—Methods for optical code recognition
- G06K7/146—Methods for optical code recognition the method including quality enhancement steps
Abstract
The invention provides a kind of hyperfrequency card sender for improving to label frequency deviation fault-tolerant ability, including body and the master control borad being located within the body, antenna plate, the master control borad includes CPU and the radio circuit being connected with CPU, the radio circuit connects antenna plate, the radio circuit includes radio-frequency forward link and radio frequency reverse link, the radio frequency reverse link includes the FPGA being connected with CPU, including wave filter and the demodulation module being connected with wave filter in the FPGA, the demodulation module includes shift register, current demand signal frequency is judged by the demodulation module and the determinating reference of follow-up data bit wide is adjusted.Beneficial effects of the present invention：Judgement and bit wide adjustment can be re-started to frequency deviation, card sender is distinguished the more serious electronic tag of frequency deviation, improve hair fastener success rate, reduced label and throw aside rate.
Description
Technical field
The invention belongs to technical field of RFID, more particularly, to a kind of for improving to label frequency deviation fault-tolerant ability
Hyperfrequency card sender.
Background technology
Card sender is important component when building RFID application systems, and it completes the behaviour to label particular content
Make, including setting up archives, reporting the loss, mend card, Information revision etc..Card sender is typically put together with terminal, by hair fastener personnel to list
Label is opened to be operated.Substantially, card sender is that a small-sized tag read device makes, it is necessary to coordinate with tag control software
With.
In the prior art, because the electronic tag produced in batches has inconsistency, in particular surroundings (such as high temperature and low temperature
Environment) under, can there is larger frequency departure (frequency deviation 20% in the signal that the relatively low electronic tag of indivedual qualities is returned to card sender
More than), general existing card sender can only be distinguished and reported an error, and can not recognize label of the frequency deviation more than 20%, and without regulation number
According to the mechanism of bit wide criterion, it is impossible to enter row information write-in to label.
The content of the invention
In view of this, the present invention is directed to propose a kind of hyperfrequency card sender for improving to label frequency deviation fault-tolerant ability,
With the weak point for solving the above problems, the electronic tag more serious to frequency deviation can also be distinguished and information write-in, improve hair
Card success rate, reduces label and throws aside rate.
To reach above-mentioned purpose, the technical proposal of the invention is realized in this way：
For improving the hyperfrequency card sender to label frequency deviation fault-tolerant ability, including body and the master control being located within the body
Plate, antenna plate, the master control borad include CPU and the radio circuit being connected with CPU, and the radio circuit connects antenna plate, described
Radio circuit includes radio-frequency forward link and radio frequency reverse link, and the radio frequency reverse link includes the FPGA being connected with CPU,
Including wave filter and the demodulation module being connected with wave filter in the FPGA, the demodulation module includes shift register, passes through
The demodulation module judges current demand signal frequency and adjusts the determinating reference of follow-up data bit wide.
Further, the radio-frequency forward link includes the phaselocked loop, frequency mixer, dielectric filter, the power that are sequentially connected
Amplifier and coupler, the power amplifier connect coupler by low pass filter, and the CPU connects phaselocked loop, and logical
Low pass filter connection frequency mixer is crossed, the coupler connects antenna plate, and the radio frequency reverse link also includes what is be sequentially connected
3dB electric bridges, diode, amplifier and analog-digital converter (ADC), the wave filter in the FPGA include the mean filter of connection
And bandpass filter, the ADC connections mean filter, the bandpass filter connection demodulation module, the coupler connection
3dB electric bridges, the phaselocked loop connects 3dB electric bridges.
Further, on the master control borad, the CPU connects SDRAM, ethernet PHY chip, level conversion core respectively
Piece, house dog, PSAM draw-in grooves, SD card interface, the electronics formula of erasing can make carbon copies read-only storage (EEPROM), the ethernet PHY
Chip is sequentially connected transformer, RJ-45 interfaces, the electrical level transferring chip connection serial ports RS232.
Further, the demodulation module judges current demand signal frequency and adjusts the step of the determinating reference of follow-up data bit wide
It is rapid as follows：
A. detection receives data zero crossing and reverses direction；
B. according to sampling period number between adjacent zero crossing, current frequency is calculated and judges, regulation follow-up number when having frequency deviation
According to bit wide criterion.
Further, the process of the step A is as follows：
A1. shift register is used, data will be received and moved into 26 groups of integrators, analog and digital signal is integrated, point
It is 26 groups；
A2. 3 groups of quadrature integrator differences and 1 group of noninverting integrator difference are taken, 3 groups of quadrature integrator differences are respectively the 19th
Group and the 3rd group of integration differential I1, the 18th group and the 2nd group of integration differential I2, the 17th group and the 1st group of integration differential I3,1 groups
Noninverting integrator difference is the integration differential S1 of the 26th group and the 10th group；
A3. positive negative judgement is carried out to this several groups of integrator differences and size compares, try to achieve zero crossing and signal reverses direction,
2nd group and the 18th group of integrator spacing are half signal period, when the 18th group and the 2nd group of integrated value is in zero crossing
Place,
Or the 18th group and the 2nd group of integrated value it is equal when, the symbol direction of I1 and I3 is negative for one positive one, now judges the
2 groups of integrated value position is zero crossing,
Or after absolute value of the absolute value of I1 and I3 more than I2, and the corresponding multiple of S1 diminutions, its absolute value is also necessarily greater than
The absolute value of I2, at this moment also can determine that out the 2nd group of integrated value position for zero crossing,
The reverses direction of sign bit and a preceding zero crossing according to S1, can determine whether out the reverses direction of this zero crossing.
Further, the process of the step B is：
Data acquisition and judgement are carried out at the preface information for receiving data, radio frequency reverse link uses FM0, preface information
It is 12 data ' 0 ' of rule, according to the zero crossing position that step A3 is detected, two adjacent zero crossings is calculated with the time
Spacing, under the spacing of adjacent zero crossing, calculates the number in the sampling period of system clock generation, you can judge current reception
The frequency of signal, if higher or relatively low situation, adjusts data bit width criterion, makes receipt of subsequent data according to regulation
Rear bit wide criterion is distinguished.
Relative to prior art, it is of the present invention for improving to the hyperfrequency card sender of label frequency deviation fault-tolerant ability and
Method has the advantage that：
It is of the present invention for improve can be to frequency deviation to the hyperfrequency card sender and method of label frequency deviation fault-tolerant ability
Judgement and bit wide adjustment are re-started, card sender is distinguished the electronic tag of frequency deviation more serious (± 25% or higher), carried
Hair fastener success rate high, reduces label and throws aside rate.
Brief description of the drawings
The accompanying drawing for constituting a part of the invention is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its illustrate, for explaining the present invention, not constitute inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is the hyperfrequency card sender structured flowchart for improving to label frequency deviation fault-tolerant ability of the present invention；
Fig. 2 is that radio circuit of the present invention connects block diagram；
Fig. 3 is logic process flow figure in FPGA of the present invention；
Fig. 4 is the sampling location schematic diagram of 6 groups of integrated values in waveform in step A of the present invention；
Fig. 5 is the FM0 preface informations position of radio frequency reverse link of the present invention；
Specific embodiment
It should be noted that in the case where not conflicting, the embodiment in the present invention and the feature in embodiment can phases
Mutually combination.
Describe the present invention in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
As shown in figure 1, for improving the hyperfrequency card sender to label frequency deviation fault-tolerant ability, including body and positioned at body
Interior master control borad, antenna plate, the master control borad includes CPU and the radio circuit being connected with CPU, and the radio circuit connects antenna
Plate, the radio circuit includes radio-frequency forward link and radio frequency reverse link, and the radio frequency reverse link includes being connected with CPU
FPGA, including wave filter and demodulation module be connected with wave filter in the FPGA, the demodulation module includes shift LD
Device, judges current demand signal frequency and adjusts the determinating reference of follow-up data bit wide by the demodulation module.
As shown in Fig. 2 the radio-frequency forward link includes the phaselocked loop, frequency mixer, dielectric filter, the power that are sequentially connected
Amplifier and coupler, the power amplifier connect coupler by low pass filter, and the CPU connects phaselocked loop, and logical
Low pass filter connection frequency mixer is crossed, the coupler connects antenna plate, and the radio frequency reverse link also includes what is be sequentially connected
3dB electric bridges, diode, amplifier and ADC, the wave filter in the FPGA include the mean filter and bandpass filtering of connection
Device, the ADC connects mean filter, and the bandpass filter connects demodulation module, and the coupler connects 3dB electric bridges, institute
Phaselocked loop connection 3dB electric bridges are stated, the phaselocked loop provides local oscillation signal, and the radio-frequency forward link realizes signal by frequency mixer
ASK modulation, signal is sent to electronic tag by power amplifier via antenna after modulation, and electronic tag is advised according to agreement
Surely the query signals of forward link transmitting are received, relevant information is returned into radio frequency reverse link, demodulated through diode, put
After big device amplifies signal, into ADC and FPGA, the demodulation recognition of the electronic tag more serious to indivedual frequency deviations is carried out.
On the master control borad, the CPU connects SDRAM, ethernet PHY chip, electrical level transferring chip, guards the gate respectively
Dog, PSAM draw-in grooves, SD card interface, EEPROM, the ethernet PHY chip are sequentially connected transformer, RJ-45 interfaces, the electricity
Flat conversion chip connection serial ports RS232.
In the present embodiment, CPU is LPC4357.
The electronic tag of (frequency deviation more than 20%) serious to frequency deviation carries out related deciphering and the process of identification is main in FPGA
In logical algorithm in realize, as shown in figure 3, the demodulation module judges current demand signal frequency and adjusts follow-up data bit wide
The step of determinating reference, is as follows：
A. detection receives data zero crossing and reverses direction；
B. according to sampling period number between adjacent zero crossing, current frequency is calculated and judges, regulation follow-up number when having frequency deviation
According to bit wide criterion.
The process of the step A is as follows：
A1. shift register is used, data will be received and moved into 26 groups of integrators, analog and digital signal is integrated, point
It is 26 groups；
A2. 3 groups of quadrature integrator differences and 1 group of noninverting integrator difference are taken, 3 groups of quadrature integrator differences are respectively the 19th
Group and the 3rd group of integration differential I1, the 18th group and the 2nd group of integration differential I2, the 17th group and the 1st group of integration differential I3,1 groups
Noninverting integrator difference is the integration differential S1 of the 26th group and the 10th group；
A3. positive negative judgement is carried out to this several groups of integrator differences and size compares, try to achieve zero crossing and signal reverses direction,
As shown in figure 3, the 2nd group and the 18th group of integrator spacing are half signal period, when the 18th group and the 2nd group of integration
It is worth at zero crossing,
Or the 18th group and the 2nd group of integrated value it is equal when, the symbol direction of I1 and I3 is negative for one positive one, now judges the
2 groups of integrated value position is zero crossing,
Or after absolute value of the absolute value of I1 and I3 more than I2, and the corresponding multiple of S1 diminutions, its absolute value is also necessarily greater than
The absolute value of I2, at this moment also can determine that out the 2nd group of integrated value position for zero crossing,
The reverses direction of sign bit and a preceding zero crossing according to S1, can determine whether out the reverses direction of this zero crossing.
The process of the step B is：Data acquisition and judgement, radio frequency reverse strand are carried out at the preface information for receiving data
Road uses FM0, such as Fig. 5 (TRext=1b, wherein V is the symbol for not meeting FM0 coding rules) shown in, preface information is rule
12 data ' 0 ', according to the zero crossing position that step A3 is detected, two spacing of adjacent zero crossing are calculated with the time,
Under the spacing of adjacent zero crossing, the number in the sampling period of system clock generation is calculated, you can judge current Received Signal
Frequency, if higher or relatively low situation, data bit width criterion is adjusted, after making receipt of subsequent data according to regulation
Bit wide criterion is distinguished, and during normal condition, does not adjust more data bit criterion wide, it is higher in the case of, adjust narrow follow-up
Data bit width criterion, it is relatively low in the case of, adjust follow-up data bit wide criterion wide, can thus distinguish out frequency deviation tighter
The electronic tag of weight, improves hair fastener efficiency.
The flow that logical process is carried out in the FPGA is：Reversely receive data by ADC process and mean filter,
The filtering of bandpass filter, obtains analog and digital signal, and the signal enters demodulation module, carries out step A and B.
The process of step B is illustrated below by specific embodiment：
It is 64KHz that reverse link receives signal frequency, and down-sampled (reduction of speed 1/10) is carried out by bandpass filter, and FPGA makes
It is 26MHz with clock frequency.
64KHz is reversely received in the preface information of signal, and the spacing of adjacent zero crossing is 7812ns (1/64KHz/2), is adopted
The sample cycle is 384.6ns (1*10/26MHz), then have 20 sampling periods (7812ns/384.6ns) between adjacent zero crossing.This
When logic judge if in adjacent zero crossing in preface information, there is 19 to 21 sampling periods, and by state machine continuous 5
All it is 19 to 21 sampling periods in the adjacent zero crossing that secondary judgement continues below, then judges that reversely receiving signal does not have frequency deviation,
Conversely, then there is frequency deviation.
If reverse receives frequency is 48KHz (with respect to 64KHz standard agreements frequency deviation -25%), the spacing of adjacent zero crossing
It is 10417ns, the sampling period is still 384.6ns, 27 sampling periods is had in adjacent zero crossing, and if pass through state machine
All it is if 21 to 30 sampling periods, then to judge that receiving signal has low in the adjacent zero crossing that continuous 5 judgements continue below
Frequency deviation, the now zero crossing spacing bit wide criterion to data ' 0 ' and data ' 1 ' is readjusted, with the phase after adjustment
Criterion to data ' 0 ' wider and ' 1 ' still suffers from the data of frequency deviation to distinguish behind preface information.It is same during frequency deviation high
Reason.
When following table is low frequency inclined 48KHz, the value before the adjustment of data ' 0 ' and ' 1 ' bit wide criterion and after adjustment：
In FM0 codings, the adjacent zero crossing width of data ' 1 ' is the twice of data ' 0 '.
After reversely data are received into FPGA next time, judgement and bit wide adjustment can be re-started to frequency deviation；So, send out
Card device can distinguish the electronic tag of frequency deviation more serious (± 25% or higher).
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Within god and principle, any modification, equivalent substitution and improvements made etc. should be included within the scope of the present invention.
Claims (6)
1. it is used to improve the hyperfrequency card sender to label frequency deviation fault-tolerant ability, it is characterised in that：Including body and positioned at body
Interior master control borad, antenna plate, the master control borad includes CPU and the radio circuit being connected with CPU, and the radio circuit connects antenna
Plate, the radio circuit includes radio-frequency forward link and radio frequency reverse link, and the radio frequency reverse link includes being connected with CPU
FPGA, including wave filter and demodulation module be connected with wave filter in the FPGA, the demodulation module includes shift LD
Device, judges current demand signal frequency and adjusts the determinating reference of follow-up data bit wide by the demodulation module.
2. the hyperfrequency card sender for improving to label frequency deviation fault-tolerant ability according to claim 1, it is characterised in that：
The radio-frequency forward link includes the phaselocked loop, frequency mixer, dielectric filter, power amplifier and the coupler that are sequentially connected, institute
State power amplifier and coupler is connected by low pass filter, the CPU connects phaselocked loop, and connects mixed by low pass filter
Frequency device, the coupler connects antenna plate, and the radio frequency reverse link also includes the 3dB electric bridges, diode, the amplification that are sequentially connected
Device and ADC, the wave filter in the FPGA include the mean filter and bandpass filter of connection.The ADC connections average filter
Ripple device, the bandpass filter connects demodulation module, and the coupler connects 3dB electric bridges, and the phaselocked loop connects 3dB electric bridges.
3. the hyperfrequency card sender for improving to label frequency deviation fault-tolerant ability according to claim 1, it is characterised in that：
On the master control borad, the CPU connects SDRAM, ethernet PHY chip, electrical level transferring chip, house dog, PSAM cards respectively
Groove, SD card interface, EEPROM, the ethernet PHY chip are sequentially connected transformer, RJ-45 interfaces, the electrical level transferring chip
Connection serial ports RS232.
4. the hyperfrequency card sender for improving to label frequency deviation fault-tolerant ability according to claim 1, it is characterised in that
The step of demodulation module judges current demand signal frequency and adjusts the determinating reference of follow-up data bit wide is as follows：
A. detection receives data zero crossing and reverses direction；
B. according to sampling period number between adjacent zero crossing, current frequency is calculated and is judged, more data bit is adjusted when having frequency deviation
Criterion wide.
5. the hyperfrequency card sender for improving to label frequency deviation fault-tolerant ability according to claim 4, it is characterised in that
The process of the step A is as follows：
A1. shift register is used, data will be received and moved into 26 groups of integrators, analog and digital signal is integrated, be divided into 26
Group；
A2. take 3 groups of quadrature integrator differences and 1 group of noninverting integrator difference, 3 groups of quadrature integrator differences be respectively the 19th group and
3rd group of integration differential I1, the 18th group and the 2nd group of integration differential I2, the 17th group and the 1st group of the integration differential same phase of I3,1 groups
Integrator difference is the integration differential S1 of the 26th group and the 10th group；
A3. positive negative judgement is carried out to this several groups of integrator differences and size compares, try to achieve zero crossing and signal reverses direction,
2nd group and the 18th group of integrator spacing are half signal period, when the 18th group and the 2nd group of integrated value is at zero crossing,
Or the 18th group and the 2nd group of integrated value it is equal when, the symbol direction of I1 and I3 is negative for one positive one, now judges the 2nd group
Integrated value position be zero crossing,
Or after absolute value of the absolute value of I1 and I3 more than I2, and the corresponding multiple of S1 diminutions, its absolute value is also necessarily greater than I2's
Absolute value, at this moment also can determine that out the 2nd group of integrated value position for zero crossing,
The reverses direction of sign bit and a preceding zero crossing according to S1, can determine whether out the reverses direction of this zero crossing.
6. the hyperfrequency card sender for improving to label frequency deviation fault-tolerant ability according to claim 4, it is characterised in that
The process of the step B is：Data acquisition and judgement are carried out at the preface information for receiving data, radio frequency reverse link is used
FM0, preface information is 12 data ' 0 ' of rule, according to the zero crossing position that step A3 is detected, two is calculated with the time
The spacing of adjacent zero crossing, under the spacing of adjacent zero crossing, calculates the number in the sampling period of system clock generation, you can
Judge the frequency of current Received Signal, if higher or relatively low situation, adjust data bit width criterion, make receipt of subsequent
Data are distinguished according to the bit wide criterion after regulation.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710073787.8A CN106845583A (en) | 2017-02-10 | 2017-02-10 | For improving the hyperfrequency card sender to label frequency deviation fault-tolerant ability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710073787.8A CN106845583A (en) | 2017-02-10 | 2017-02-10 | For improving the hyperfrequency card sender to label frequency deviation fault-tolerant ability |
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| CN106845583A true CN106845583A (en) | 2017-06-13 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006197092A (en) * | 2005-01-12 | 2006-07-27 | National Institute Of Information & Communication Technology | Optical communication system |
| CN101169817A (en) * | 2006-10-27 | 2008-04-30 | 财团法人工业技术研究院 | Radio frequency identification label system and its data stream |
| CN102810164A (en) * | 2011-05-30 | 2012-12-05 | 中兴通讯股份有限公司 | RFID (radio frequency identification) card issuing equipment and processing method thereof |
| CN104463277A (en) * | 2014-12-12 | 2015-03-25 | 威海北洋电气集团股份有限公司 | Overlapped label carrier wave self-adaptation adjustment and number pre-estimation method and system |
| CN105791193A (en) * | 2016-02-19 | 2016-07-20 | 苏州沿芯微电子科技有限公司 | Code element recovery system and method based on multimode reader-writer |
| CN106059975A (en) * | 2016-07-11 | 2016-10-26 | 天津中兴智联科技有限公司 | New method for inhibiting carrier synchronization and costas ring |
-
2017
- 2017-02-10 CN CN201710073787.8A patent/CN106845583A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006197092A (en) * | 2005-01-12 | 2006-07-27 | National Institute Of Information & Communication Technology | Optical communication system |
| CN101169817A (en) * | 2006-10-27 | 2008-04-30 | 财团法人工业技术研究院 | Radio frequency identification label system and its data stream |
| CN102810164A (en) * | 2011-05-30 | 2012-12-05 | 中兴通讯股份有限公司 | RFID (radio frequency identification) card issuing equipment and processing method thereof |
| CN104463277A (en) * | 2014-12-12 | 2015-03-25 | 威海北洋电气集团股份有限公司 | Overlapped label carrier wave self-adaptation adjustment and number pre-estimation method and system |
| CN105791193A (en) * | 2016-02-19 | 2016-07-20 | 苏州沿芯微电子科技有限公司 | Code element recovery system and method based on multimode reader-writer |
| CN106059975A (en) * | 2016-07-11 | 2016-10-26 | 天津中兴智联科技有限公司 | New method for inhibiting carrier synchronization and costas ring |
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