CN106844926A - The design of dynamic reconfigurable hardware circuit, execution method and system - Google Patents
The design of dynamic reconfigurable hardware circuit, execution method and system Download PDFInfo
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- CN106844926A CN106844926A CN201710024495.5A CN201710024495A CN106844926A CN 106844926 A CN106844926 A CN 106844926A CN 201710024495 A CN201710024495 A CN 201710024495A CN 106844926 A CN106844926 A CN 106844926A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The present invention provides the method for designing and system of dynamic reconfigurable hardware circuit, performs method and system.Design process includes：The operation that counts containing constant in identification application, the value of the constant changes within the specific limits；Adjust the span of the constant according to accuracy requirement, the span is made up of at least one parameter that counts；Redundancy section in the operation that counts counted according to the accuracy requirement removes each corresponding to parameter, customizes the hardware circuit according to this.Implementation procedure includes：Application performance model is set up, selects performance highest hardware circuit to perform according to this.The present invention reduces the use of hardware resource by reducing the useless operation in general arithmetic units, so as to lift hardware circuit performance.
Description
Technical field
The present invention relates to the hardware circuit design field of FPGA, the optimization of more particularly to dynamic reconfigurable hardware circuit sets
Meter, execution method and system.
Background technology
Logic programmable array (FPGA) is a kind of programmable integrated circuit chip after manufacture, and circuit is provided in chip
Programmable node, can redefine circuit logic according to user's setting.Pin can be provided compared to conventional process chip CPU, FPGA
To the height optimization circuit of particular problem, hundred times of level calculation performances are lifted；Compared to traditional integrated circuit chip ASIC, FPGA
More flexible numerical procedure can be provided.
FPGA hardware circuit performance is primarily limited to hardware resource：The hardware resource of each computing unit consumption is fewer, firmly
The overall calculation unit degree of parallelism that part chip to be provided is higher, so as to support process performance higher.Fig. 1 shows one kind
The regular situation that hardware resource is used is reduced by reducing computational accuracy：CPU often uses the bit of double precision 64 with computing unit
And the bit of single precision 32, wherein, double precision uses 1 bit storage symbolic information, 11 bit storage index informations, 52 bit storages
Decimal information, single precision uses 1 bit storage symbolic information, 8 bit storage index informations, 23 bit storage decimal information.So
And, CPU custom calculations unit uses 1 bit storage symbolic information, 4 bit storage number index informations, 8 bit storage decimals letter
Breath, compared to traditional double precision and single precision computing unit, the computational accuracy of 13 bits significantly reduces hardware consumption.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide setting for dynamic reconfigurable hardware circuit
Meter, execution method and system, the process performance for solving optimization FPGA in the prior art can cause asking for computational accuracy reduction
Topic.The present invention reduces the resource consumption of arithmetic units by removing the redundant computation in general arithmetic units, is counted without sacrificing
Precision is calculated, so that circuit of more efficiently optimizing hardware.
In order to achieve the above objects and other related objects, the present invention provides a kind of design side of dynamic reconfigurable hardware circuit
Method, including：The operation that counts containing constant in identification application, the value of the constant changes within the specific limits；According to precision
Demand adjusts the span of the constant, and the span is made up of at least one parameter that counts；According to the precision need
The redundancy section in the operation that counts for removing and being counted described in each corresponding to parameter is sought, the hardware circuit is customized according to this.
In one embodiment of the invention, the accuracy requirement includes：Using accuracy requirement and arithmetic accuracy demand.
In one embodiment of the invention, the determination of the arithmetic accuracy demand, including：It is determined that default adjusting range, and
Numerical value is randomly selected in the default adjusting range as algorithm parameter value, according to formula
ε (t, s)=a (t, s)-f (t, s)
Convergency factor g is calculated, wherein, t, s represent position of the adjusting parameter in time, spatial domain respectively, and ε (t, s) is represented
Algorithm calculates the difference that actual value a (t, s) and algorithm are calculated between actual value f (t, s)；If | g | ＞ 1, by the default tune
Whole scope halves, and the so-called algorithm parameter value of numerical value is chosen again and is calculated, until convergency factor | g |≤1 for calculating, so that
To final adjusting range.
In one embodiment of the invention, the calculation counted according to the accuracy requirement removes each corresponding to parameter
Redundancy section in number operation, including：The parameter that will be counted described in each is expressed as binary number；Meeting the accuracy requirement
On the basis of, it is the bit of " 0 " to remove the binary value before required precision.
It is described to customize the hardware circuit according to this and also include in one embodiment of the invention：The hardware circuit is made to support
The calculating of different constants during using operation, realizes especially by the mode of static arithmetic units or dynamic arithmetic units：It is described quiet
State arithmetic units, different constant computings are supported using the different stacked systems of same hardware cell；The dynamic arithmetic units,
Different hardware cells are reconstructed for different constants to support different constant computings.
In one embodiment of the invention, also include after completion is customized：The static arithmetic units and institute are estimated respectively
The hardware resource consumption of dynamic arithmetic units is stated, and calculates corresponding degree of parallelism, choose degree of parallelism mode high.
In order to achieve the above objects and other related objects, the present invention provides a kind of design department of dynamic reconfigurable hardware circuit
System, including：Identification module, for the operation that counts containing constant in identification application, the value of the constant is within the specific limits
Change；Adjusting module, the span for adjusting the constant according to accuracy requirement, the span is calculated by least one
Number parameter composition；Module is rejected, for the operation that counts counted corresponding to parameter described in removing each according to the accuracy requirement
In redundancy section, the hardware circuit is customized according to this.
In order to achieve the above objects and other related objects, the present invention provides a kind of dynamic reconfigurable hardware circuit, by the above
The method for designing of any described dynamic reconfigurable hardware circuit is designed.
In order to achieve the above objects and other related objects, a kind of execution dynamic reconfigurable as described above of present invention offer is hard
The method of part circuit, the execution method includes：Application performance model T is set up, and selects performance highest hardware circuit to perform；
Wherein, ds represents the size for calculating data volume, fknlRepresent hardware clock frequency, P represent arithmetic units degree of parallelism,
OrHardware reconstruction cost is represented,Nr* φ represent reconstruct hardware file size, by Cell Reconstruction file size φ with
Hardware cell number N need to be reconstructedrProduct constitute, θ represents reconstruct bandwidth.
In order to achieve the above objects and other related objects, a kind of execution dynamic reconfigurable as described above of present invention offer is hard
The system of part circuit, the execution system includes：Processing module, for setting up application performance model T, and selects performance highest
Hardware circuit is performed；
Wherein, ds represents the size for calculating data volume, fknlRepresent hardware clock frequency, P represent arithmetic units degree of parallelism,
OrHardware reconstruction cost is represented,Nr* φ represent reconstruct hardware file size, by Cell Reconstruction file size φ with
Hardware cell number N need to be reconstructedrProduct constitute, θ represents reconstruct bandwidth.
As described above, the method for designing of dynamic reconfigurable hardware circuit of the invention and be, perform method and system, pass through
Reduce the useless operation in general arithmetic units to reduce the use of hardware resource, efficiently improve hardware circuit performance.
Brief description of the drawings
Fig. 1 is shown as the present invention and reduces the signal that hardware resource is used using reduction computational accuracy mode in the prior art
Figure.
Fig. 2 is shown as the method for designing flow chart of the dynamic reconfigurable hardware circuit of one embodiment of the invention.
Fig. 3 is shown as the corresponding different hardware structure design diagram of different constant values of one embodiment of the invention.
Fig. 4 is shown as the schematic diagram that redundant computation is removed according to accuracy requirement of one embodiment of the invention.
Fig. 5 A~5B is shown as the design process schematic diagram of the depth custom hardware unit of one embodiment of the invention.
Fig. 6 is shown as the design system module map of the dynamic reconfigurable hardware circuit of one embodiment of the invention.
Fig. 7 is shown as the method flow diagram of the execution dynamic reconfigurable hardware circuit of one embodiment of the invention.
Fig. 8 is shown as the system module figure of the execution dynamic reconfigurable hardware circuit of one embodiment of the invention.
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages of the invention and effect easily.The present invention can also be by specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under spirit of the invention.It should be noted that, in the case where not conflicting, following examples and implementation
Feature in example can be mutually combined.
It should be noted that the diagram provided in following examples only illustrates basic structure of the invention in a schematic way
Think, component count, shape and size when only display is with relevant component in the present invention rather than according to actual implementation in schema then
Draw, it is actual when the implementing kenel of each component, quantity and ratio can be a kind of random change, and its assembly layout kenel
It is likely more complexity.
In order to ensure the flexibility of numerical procedure, and optimal hardware precision is provided, the present invention proposes a kind of based on dynamic
The arithmetic units optimization method of state restructural (FPGA), arithmetic units refer to the basic computational ele- ments such as addition subtraction multiplication and division exponent arithmetic.Firmly
Support using reconfigurable hardware logic to customize arithmetic units in part framework, during hardware customization is by reducing general arithmetic units
Useless operation reduces the use of hardware resource, so as to lift hardware circuit performance.
Fig. 2 is referred to, the method for designing of the dynamic reconfigurable hardware circuit that the present invention is provided mainly comprises the following steps：
Step S201：Identification object element, wherein, object element is the operation that counts containing constant in.Such as Fig. 3 institutes
Show, one of object element is that constant multiplication operates ft,s+1* α, the occurrence of constant α fluctuates within the specific limits, with
It is lower that each occurrence is referred to as algorithm parameter.The corresponding hardware structures of different α are different：α=0.75 uses and is represented in binary as
0.11, α=0.76, using being represented in binary as 0.110000101, for same 32 bits multiplication unit, α=0.76 needs
32*9 full adder (f [0]~f [31], α [0]~α [8]), α=0.75 item only need to 32*2 full adder (f [0]~f [31],
α [0]~α [1]).In algorithm aspect, each multiplier ft-1,s*δ、ft,s*β、ft,s-1* the operation that γ is completed is identical.
Step S202：Optimization space is set up, wherein, the optimization space of the operation that counts is in the adjustable of algorithm aspect parameter
Scope, that is, algorithm parameter value set.The optimization space is mainly determined by procedure below：
1) accuracy requirement is applied, is determined with reference to the precision of the operation that counts, it is also possible to according to user's request self-defining；
2) arithmetic accuracy demand, determines that the adjusting range of algorithm parameter advantageously ensures that the adjustment of parameter is not interfered with entirely
Count the stability of operation.Specifically, as shown in formula (1)~(3)：
ε (t, s)=a (t, s)-f (t, s) (1)
Wherein, t, s represent position of the adjusting parameter in time, spatial domain respectively, and it is true that ε (t, s) represents that algorithm is calculated
Value a (t, s) and algorithm calculate the interpolation between actual value f (t, s), and g represents the convergency factor that algorithm difference is changed over time, | g |
≤ 1 expression algorithm be it is convergent,And Δ t represent respectively adjustment after, the time parameter using original algorithm,And Δ s difference
After expression adjustment, using the spatial parameter of original algorithm, ξ represents the adjusting range of parameter.
For application-specific, can be true according to formula (3) access time spatial parameter using emulation tools such as Monte Carlos
Determine adjusting range ξ, and numerical value is randomly selected in scope ξ as algorithm parameter value, convergency factor is calculated according to formula (1)~(2)
g.If convergency factor g is more than 1, scope ξ is halved, repeat said process, until the convergency factor g stabilizations for calculating.
Step S203：Hardware model estimates that the computing unit of the corresponding constant parameter value of estimation algorithms of different parameter is disappeared
The hardware resource of consumption, and therefrom select that consumption figures is minimum to be configured.It is assumed that determining that application precision is needed
It is 10 bits to ask, then 3 selections of algorithms of different parameter can cause 3 difference α values, specifically, the two of α=1.749511719
System is expressed as 12 bits of being represented in binary as of 110111111111, α=1.750976563 of 12 bits
Be represented in binary as 12 bits the 111000000100 of 111000000010, α=1.751953125.Due to there was only non-zero
Binary numeral, i.e. numerical value are ' 1 ' bit, it is necessary to hardware supported, and numerical value is ' 0 ' the corresponding operation that counts of bit
It is redundant operation, it is not necessary to hardware supported, so in this example, under the application accuracy requirement of 10 bits, α=
1.749511719 corresponding hardware resource consumptions are first 10：1100111111, α=1.750976563 corresponding hardware resources
Consume is first 3：111 (0 of the 4th~10 bit is redundant computation, rejects), the corresponding hardware money in α=1.751953125
Source consumption is first 10：1110000001.
Step S204：Making arithmetic units can support constant calculations different during using operation, including two ways：It is static
Arithmetic units and dynamic reconfigurable unit：
1) static arithmetic units：Static arithmetic units support that different constant parameters are calculated using same hardware circuit, lead to
Cross using general-purpose computations framework shown in Fig. 3, same hardware cell can support different constant calculations.As shown in figure 4, for one group of ginseng
Number, chooses the minimum constant of non-zero values and sets, by formula (4), (5) computing hardware resource consumption：
Wherein, a is represented and is applied accuracy requirement, the number of non-zero values when b represents constant binary representation.Transported for plus-minus
Calculate, hardware resource takes the peak in the hardware resource of a, b consumption, for multiplying, hardware resource takes the hardware of a, b consumption
Product in resource.
2) dynamic arithmetic units：Dynamic arithmetic units customize mode for each constant computation unit using depth so that
Each constant calculations uses minimum hardware resource consumption.Operationally, it uses Dynamic Reconfigurable Technique to replace different hardware
Unit, supports different constant calculations, and as shown in Figure 5A, constant α=1.749511719 are expressed as α 0 by fixed-point representation,
The first ' 0 ' represents sign bit, and positive number is represented herein.α 0 is moved to right one and mends ' 0 ' in first place and forms α 1.Calculated according to α 0 and α 1
Tri- intermediate variables of c, s, m, computing formula corresponds to (6), (7), (8) respectively, and the binary representation of constant is converted to
canonical-signed-digit(CSD)：
ci+1=a0i*a1i+ci+a0i+ci*a1i (6)
si=a1i (7)
Finally, dynamic cell expression symbol CSD is calculated according to formula (9)：
Wherein, in CSD+- symbol operates generation to be customized for the depth of a constant value by hardwired shift and subtraction
Dynamic arithmetic units.As shown in Figure 5 B, constant a=1.749511719 is by the CSD "+00-0000000-0 " after conversion, wherein
" 0 ", without hardware operation, "+-- " three marks need to carry out shifting function according to its position according to formula (9).In this example,
"+" is located at first " 0 " left 1 position, it is necessary to move to left one, first "-" is located at its right 2 position, it is necessary to move to right two.Three
Determine that its is operated according to "+- " symbol for comparing position labeled as after the completion of displacement.In this example, "+" is combined with the right "-", due to
It is minus sign, and first operation is subtracter.Depth customized hardware unit includes three shifting functions and two subtractions
Operation, only supports a=1.749511719.When the constant value changes for needing to support, it is necessary to be new constant value by hardware reconstruction
Corresponding depth customized hardware unit.To support that all depth custom hardware units generated during application operation are referred to as one
Dynamic arithmetic units.
Step S205：Combined with hardware overall architecture, by estimating that it is (including quiet that hardware resource consumption calculates each arithmetic units
State, dynamic) degree of parallelism, hardware adaptations of the generation based on static arithmetic units and the hardware adaptations based on dynamic arithmetic units,
Applied from performance highest is chosen therebetween.
Fig. 6 is referred to, with above method embodiment principle similarly, the present invention provides a kind of dynamic reconfigurable hardware electricity
The design system 600 on road, including：Identification module 601, adjusting module 602, rejecting module 603.Due to the skill in previous embodiment
Art feature can be used for the present embodiment, thus it is no longer repeated.
The operation that counts containing constant in the identification application of identification module 601, the value of the constant becomes within the specific limits
Change；Adjusting module 602 adjusts the span of the constant according to accuracy requirement, and the span is counted ginseng by least one
Array into；It is superfluous in the counting operation that rejecting module 603 counts corresponding to parameter according to the accuracy requirement removes each
Remaining part point, customizes the hardware circuit according to this.
The present invention also provides a kind of dynamic reconfigurable hardware circuit designed by any of the above-described kind of method for designing, again
Do not repeat to repeat.
Fig. 7 is referred to, the present invention also provides a kind of dynamic reconfigurable hardware electricity for performing and being designed with above-mentioned method for designing
The method on road, the execution method is comprised the following steps：
Step S701：According to restructural optimizing application, application performance model is set up.Shown in performance model such as formula (10)：
Wherein, performance model is by calculating size ds, the hardware clock frequency f of data volumeknl, arithmetic units degree of parallelism P,
And hardware reconstruction cost OrEstimate hardware adaptations and calculate the time.Specifically, size of data ds is determined by application, can be retouched by algorithm
Directly extraction is stated, size of data ds is together determined with algorithm constant number and applied run time, and the number of constant determines to count
Unit general hardware is consumed, hardware clock frequency fknlExtracted by hardware compilation result, arithmetic units degree of parallelism P by optimizing after calculate
Counting unit resource consumption and hardware chip entirety resource are determined.Parameter is put into performance model after extraction, supports performance estimation.Hardware
Reconfiguration cost OrHardware weight when being the different constants of reconstruct corresponding depth optimization arithmetic units when being using dynamic arithmetic units
The structure time.Formula (11) describes hardware reconstruction cost OrComputation model：
Hardware reconstruction time cost OrIt is expressed as：Reconstruct hardware file size Nr* the ratio between φ and reconstruct bandwidth θ, wherein, weight
Structure hardware file size Nr* φ is：Cell Reconstruction file size φ with need to reconstruct hardware cell number NrProduct.
Step S702：Application of the contrast based on static cell precision optimizing and dynamic cell precision optimizing, according to performance
Model, size of data, number of parameters, prediction application performance highest is carried out using execution.If it should be noted that choosing base
In the application of dynamic cell precision optimizing, then bottom hardware is reconstructed in parameter change, perform the dynamic based on correspondence parameter single
The application of first precision optimizing.
Fig. 8 is referred to, similarly, the present invention provides a kind of dynamic reconfigurable hardware to above-mentioned execution embodiment of the method principle
The execution system 800 of circuit, including：Processing module 801, for setting up application performance model T, and selects performance highest hardware
Circuit is performed；
Wherein, ds represents the size for calculating data volume, fknlRepresent hardware clock frequency, P represent arithmetic units degree of parallelism,
OrHardware reconstruction cost is represented,Nr* φ represent reconstruct hardware file size, by Cell Reconstruction file size φ with
Hardware cell number N need to be reconstructedrProduct constitute, θ represents reconstruct bandwidth.Because the technical characteristic in previous embodiment can be used
In the present embodiment, thus it is no longer repeated.
Based on above-mentioned, application example of the method for the present invention presented below in two specific fields.
Option valuation is a kind of wide variety of financial option valuation algorithm, and Black-Scholes Option Pricing Model Black-Scholes is by considering estimated share price
Fluctuation assume the statistical distribution of Future price, thus estimate the various possibilities of Future price.Option valuation is related to partially micro-
Divide equation solution.As shown in Equation 12, wherein f is option premium to Option Pricing Equation, and s is assets value, and t is time variable, τ
It is interest rate, σ is assets value fluctuation.By solving partial differential equation, option valuation f is calculated by formula 13, and wherein α β γ are
Constant based on algorithm parameter, changes therewith according to time variable and the fluctuation of word length value：
ft,s=α ft-1,s+1+βft-1,s+γft-1,s-1 (13)
For option valuation application, Algorithms of Selecting parameter temporal variable t and assets value s build optimization space, are related to α β
Three multiplication operation of γ is objective optimization arithmetic units.Compared to the computing module using original arithmetic units, such as the institute of table 1
Show, the calculation module resource using static arithmetic units and dynamic arithmetic units after optimization consumes RknlIt is greatly reduced.For same
Hardware reconfiguration chip (Xilinx Virtex-6SX475T), its overall hardware adaptations degree of parallelism lifting is up to 8 times.Through surveying
Examination, for compared with small data quantity, due to reconfiguration cost, using static arithmetic units, option valuation application performance is promoted to 2 times.It is right
In larger data amount ds, using dynamic arithmetic units, option valuation application performance is promoted to 8 times.
Table 1
It is a kind of conventional geology imaging algorithm that the geology imaging inverse time combines, its reflection sound wave and simulation according to geology
Checking moves closer to the geologic structure imaging of ground end to reflection sound wave mutually, so as to be the offer information such as petroleum collection.It is fixed with option
Valency is similar to, and p (t, s) is address pressure parameter in its partial differential equation (formula 14), and dvv (s) is SVEL, and f (t, s) is defeated
Enter sound wave, partial differential equation include multiple constant c as shown in Equation 15 after launchingi,j, constant value relies on partial differential equation parameter
Time variable t and space variable s.Its optimum results as shown in table 2, constant c is contained by optimizationi,jArithmetic element, compared to
Original calculation module, the computing module resource consumption based on static arithmetic units reduces 30%, and is based on dynamic arithmetic units
Computing module resource consumption reduce 5.3 times.The total resources of objective chip is limited to, the computing module based on static cell
Degree of parallelism higher cannot be supported, and the computing module degree of parallelism for being based on dynamic cell improves 6 times, measuring and calculation performance boost
2.62 times.
Table 2
In sum, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
The personage for knowing this technology all can carry out modifications and changes under without prejudice to spirit and scope of the invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
Into all equivalent modifications or change, should be covered by claim of the invention.
Claims (10)
1. a kind of method for designing of dynamic reconfigurable hardware circuit, it is characterised in that including：
The operation that counts containing constant in identification application, the value of the constant changes within the specific limits；
Adjust the span of the constant according to accuracy requirement, the span is made up of at least one parameter that counts；
Redundancy section in the operation that counts counted according to the accuracy requirement removes each corresponding to parameter, customizes according to this
The hardware circuit.
2. the method for designing of dynamic reconfigurable hardware circuit according to claim 1, it is characterised in that the accuracy requirement
Including：Using accuracy requirement and arithmetic accuracy demand.
3. the method for designing of dynamic reconfigurable hardware circuit according to claim 2, it is characterised in that the arithmetic accuracy
The determination of demand, including：It is determined that default adjusting range, and numerical value is randomly selected in the default adjusting range as algorithm ginseng
Numerical value, according to formula
ε (t, s)=a (t, s)-f (t, s)
Convergency factor g is calculated, wherein, t, s represent position of the adjusting parameter in time, spatial domain respectively, and ε (t, s) represents algorithm
Calculate the difference that actual value a (t, s) and algorithm are calculated between actual value f (t, s)；If | g | ＞ 1, by the default adjustment model
Enclose and halve, the so-called algorithm parameter value of numerical value is chosen again and is calculated, until convergency factor | g |≤1 for calculating, so as to obtain most
Whole adjusting range.
4. the method for designing of dynamic reconfigurable hardware circuit according to claim 1, it is characterised in that described in the basis
Accuracy requirement removes the redundancy section in the operation that counts counted described in each corresponding to parameter, including：
The parameter that will be counted described in each is expressed as binary number；
On the basis of the accuracy requirement is met, binary value is the bit of " 0 " before precision point needed for removal.
5. the method for designing of dynamic reconfigurable hardware circuit according to claim 1, it is characterised in that described to customize according to this
The hardware circuit also includes：The calculating of the hardware circuit different constants when supporting that application runs is made, is calculated especially by static state
The mode of counting unit or dynamic arithmetic units is realized：
The static arithmetic units, different constant computings are supported using the different stacked systems of same hardware cell；
The dynamic arithmetic units, reconstruct different hardware cells to support different constant computings for different constants.
6. the method for designing of dynamic reconfigurable hardware circuit according to claim 5, it is characterised in that in customization completion
Also include afterwards：The hardware resource consumption of the static arithmetic units and the dynamic arithmetic units is estimated respectively, and calculates correspondence
Degree of parallelism, choose degree of parallelism mode high.
7. a kind of design system of dynamic reconfigurable hardware circuit, it is characterised in that including：
Identification module, for the operation that counts containing constant in identification application, the value of the constant changes within the specific limits；
Adjusting module, the span for adjusting the constant according to accuracy requirement, the span is calculated by least one
Number parameter composition；
Module is rejected, for the redundancy in operating that counts counted corresponding to parameter that removes each according to the accuracy requirement
Part, customizes the hardware circuit according to this.
8. a kind of dynamic reconfigurable hardware circuit, it is characterised in that by any described dynamic reconfigurable in claim 1 to 6
The method for designing of hardware circuit is designed.
9. a kind of method for performing dynamic reconfigurable hardware circuit as claimed in claim 8, wherein, the dynamic reconfigurable is hard
Part circuit is that the method for designing of the dynamic reconfigurable hardware circuit as described in claim 5 or 6 is designed, the execution method
Including：Application performance model T is set up, and selects performance highest hardware circuit to perform；
Wherein, ds represents the size for calculating data volume, fknlRepresent that hardware clock frequency, P represent arithmetic units degree of parallelism, OrRepresent
Hardware reconstruction cost,Nr* φ represent reconstruct hardware file size, by Cell Reconstruction file size φ with need reconstruct
Hardware cell number NrProduct constitute, θ represents reconstruct bandwidth.
10. a kind of system for performing dynamic reconfigurable hardware circuit as claimed in claim 8, wherein, the dynamic reconfigurable
Hardware circuit is that the method for designing of the dynamic reconfigurable hardware circuit as described in claim 5 or 6 is designed, described to perform system
System includes：Processing module, for setting up application performance model T, and selects performance highest hardware circuit to perform；
Wherein, ds represents the size for calculating data volume, fknlRepresent that hardware clock frequency, P represent arithmetic units degree of parallelism, OrRepresent
Hardware reconstruction cost,Nr* φ represent reconstruct hardware file size, by Cell Reconstruction file size φ with need reconstruct
Hardware cell number NrProduct constitute, θ represents reconstruct bandwidth.
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