CN106844101B - NVP performance optimization backup method and system based on Cache perception - Google Patents
NVP performance optimization backup method and system based on Cache perception Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1458—Management of the backup or restore process
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1438—Restarting or rejuvenating
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1448—Management of the data involved in backup or backup restore
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1448—Management of the data involved in backup or backup restore
- G06F11/1451—Management of the data involved in backup or backup restore by selection of backup contents
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Abstract
The invention discloses the NVP performance perceived based on Cache optimization backup method and systems；Slot tag is inserted into the candidate point in dis-assembling code as backup location；Dis-assembling code with slot tag is analyzed, the behavior of cache memory Cache is analyzed, under the premise of guaranteeing successfully to back up, farthest slot tag is selected to be inserted into backup label；Backup label position mark is carried out to every instruction, the instruction of energy alarm signal is received, starts to be backed up on the backup label position of respective markers, so that instruction, before starting backup, instruction operation reaches farthest advance step-length；When encountering energy alarm signal in program operation process, backup to main memory in the non-volatile memory NVP based on NVM, program, which continues to run until, just starts triggering backup at farthest backup label, can run maximum operation step-length after program receives energy alarm signal to realize.
Description
Technical field
The present invention relates to the fields embedded system (Embedded System), more particularly to the NVP based on Cache perception
Performance optimizes backup method and system.
Background technique
In recent years, we witnessed the embedded systems such as Internet of Things and wearable device Exponential growth and they
To a series of variations brought by our daily lifes.These intelligence systems generally use sensor to collect related data,
Then data are analyzed, and is transferred to information centre.Traditionally, embedded system is mostly battery powered.However now,
In many wearable health monitoring devices, the use of battery is no longer welcome, this is because 1) large scale and weight；
2) safety and health is paid close attention to；3) frequent charge.
Energy harvester is becoming the advantageous power supply of wearable device, because it is to obtain energy from the environment of surrounding
Amount, such as solar energy, electromagnetic radiation or heat source etc., and realized by using some energy conversion techniques and the capacitor of equipment is carried out
Charging, then electronic equipment is powered.Also because the charging modes of this environmental protection, provide better user experience.But it is possible to
It is exactly unstability that amount, which collects the generally existing disadvantage of power supply,.Due to unstability, program may be interrupted frequently, as making
With the volatibility processor based on CMOS, power-off will lead to result loss, cause program to need to execute from the beginning again, this meeting
A large amount of energy expense is brought, even more so that large-scale task can not be completed.
Nonvolatile memory (non-volatile memory, abbreviation NVM) refers to after power supply is turned off, and is stored
The computer storage that data will not disappear the, so non-volatile memory (non-volatile based on NVM
Processors, abbreviation NVP), just can solve each power down task in self-power supply system needs the problem of running from the beginning again.
As shown in Figure 1, when power down occurs every time, content in processor will all be saved in NVM and carry out backup, when power supply next time
When recovery, then from NVM by backup content copy into processor, state before recovery routine is then followed by and continues to execute
Go down.
NVP system design in, some researchers passed through research register file and on-chip memory backup/
Restore to realize instant open/close system.It the usual very little of register file and often updates, therefore the content backup of register can
To be designed as Yi Dan energy warning occurs with regard to full backup, this can be designed by the way that NVM cell to be attached on each trigger
Mixed type register cell is realized.The capacity of on-chip memory is bigger, and not usually all contents require to back up.Cause
This, reduces backup content by analysis program, system backup efficiency can be improved, reduce waste of the energy in backup.Due to
Energy limit, analysis dynamic can not carry out at runtime, therefore generally use the Static Analysis Method of off-line type.Although compiling
Device can report some useful information, instruct the memory content backup based on static analysis.However, the presence meeting pair of Cache
The analysis of program generates very big uncertainty.If not considering the information of Cache access hit/miss, it is assumed that use institute
The conservative analysis mode of some Cache access all miss will lead to the judgement of the generation excessively pessimism to Memory Backup, in turn
Cause the performance of whole system poor.
Summary of the invention
The purpose of the present invention is to solve the above-mentioned problems, and it is standby to provide a kind of NVP performance optimization based on Cache perception
Part method and system, it proposes that one is backed up (CAB) frame by the cache perception that off-line analysis and online management form, so that journey
Sequence analysis is more accurate.
To achieve the goals above, the present invention adopts the following technical scheme:
NVP performance based on Cache perception optimizes backup method, includes the following steps:
Off-line analysis step and online management step；
Wherein off-line analysis step includes:
Step (1): slot tag is inserted into the candidate point in dis-assembling code as backup location；
Step (2): the dis-assembling code with slot tag is analyzed, the behavior to cache memory Cache
It is analyzed, under the premise of guaranteeing successfully to back up, farthest slot tag is selected to be inserted into backup label；
Step (3): carrying out backup label position mark to every instruction, indicates the instruction for receiving energy alarm signal,
Start to be backed up on the backup label position of respective markers, so that instruction, before starting backup, instruction operation reaches farthest
Advance step-length；
The online management step includes:
Step (4): when encountering energy alarm signal in program operation process, to the non-volatile memory based on NVM
The backup of main memory in NVP, the internal storage data other than stack space by the way of full backup, and for stack space within
Data, program, which continues to run until, just starts triggering backup at farthest backup label, to realize that program receives energy alarm signal
After can run maximum operation step-length.
The reason of slot tag is inserted into dis-assembling code by the step (1) is to be inserted into the memory address instructed after slot tag
It is exactly fixed, so that it may position of the determine instruction in cache memory Cache, so that it may which that Cache is carried out to program
Behavioural analysis.
Position candidate point of the slot tag as backup label can finally use backup label or NOP operation replacement in a program
Slot tag.
Backup label instruction is executed, backup operation will be triggered.
The step of step (1), is as follows:
Step (11): analysis disassembler P, stack memory space needed for determining every instruction backup；
Step (12): dump energy distribution model is established；
Utilisable energy remaining first should meet subsequent program and execute, and meet the backup of stack again；
Position p is a feasible backup location, then remaining utilisable energy want can support program go to p and standby
All the elements in the stack of part p:
aveEne≥Ene(Ins)+Ene(backup) (1)
Wherein, aveEne indicates remaining utilisable energy, and Ene (Ins) expression executes instruction consumption energy, Ene
(backup) indicate that backup operation consumes energy；Ene (Ins) indicates each execution process instruction under cache miss situation
Energy balane instruction execution consumption ENERGY E ne (Ins_miss) of middle consumption or each instruction execution under cache hit situation
Energy balane instruction execution consumption ENERGY E ne (Ins_hit) consumed in the process；
Step (13): it calculates under cache miss situation, executes instruction consumption energy；
According to instruction set corresponding with the non-volatile memory based on NVM, and each finger under cache miss situation
The energy balane instruction execution consumed in implementation procedure is enabled to consume ENERGY E ne (Ins_miss), Ene (Ins_miss) includes all
Type instruction executes consumed energy under cache miss situation；
Step (14): it calculates backup operation and consumes energy；
According to Energy Expenditure Levels in different NVM backup procedures, and consumed during the content backup to be backed up
Energy is proportional to memory space occupied by the content to be backed up, and calculates backup operation consumption ENERGY E ne (backup)；
Step (15): P' indicates the disassembler after insertion slot tag, by disassembler P assignment into P', initially
Change P'；
Step (16): first instruction of program is put into queue Q by initialization directive queue Q；
Step (17): head of the queue is taken out from queue Q and instructs ins, to disassembler P, it is assumed that at instruction ins, receive
Energy caution signal is analyzed all possible path within the scope of remaining utilisable energy, is found farthest according to formula (1)
Can succeed the instruction ins ' backed up, and the instruction ins ' in P' is previously inserted into a slot tag and will instruct ins ' addition queue
Then Q deletes the instruction ins in Q；
Repeat step (17), until queue Q be sky, terminate and export insertion slot tag after disassembler P'.
The step of step (11), is as follows:
Step (111): successive according to being instructed in disassembler by former binary program dis-assembling at disassembler
Relationship establishes program control flow chart CFG；CFG is the abbreviation of control flow graph；
Step (112): stack analysis of version.
In the step (111):
Disassembler is divided into four major class: unconditional jump instruction, conditional jump instructions, function call instruction and sequence
It executes instruction；
The realization function of instructing according to every, that establishes every instruction enters line set and out line set, it is described enter line set
The set of all previous item instructions including present instruction；The previous item instruction of present instruction has one or more；The side out
Set includes the set of all latter item instructions of present instruction；The latter item instruction of present instruction has one or more.
Control flow chart CFG is a digraph, each point is exactly an instruction in control flow chart, is instructed according to every
It is preceding after with subsequent relationship, then successive dependence between instruction indicated by an arrow constructs the CFG of entire program.
The step of step (112), is as follows:
Step (1121): assuming that SVS indicates the version set of the stack of every instruction, SL indicates to store the stack version of entire program
This table, the cycle-index of lp representation program first carry out initialization of variable；
Step (1122): whether the storage size of stack is had an impact according to instruction, instruction is divided into stack-
Affected instruction and stack-unaffected instruction；It is big that stack-affected refers to that instruction execution will affect stack
Small instruction；Stack-unaffected refers to instruction execution but not influences the instruction of stack size；
Step (1123): the topological order list Seq of entire program is established according to CFG；
Step (1124): the topological order according to topological order list Seq analyzes each instruction；If present instruction
Be stack-unaffected instruction, directly after brought forward after the stack of instruction version set SVS；If present instruction is stack-
Affected instruction further analyzes the stack that influences and whether can generate new version of the execution to stack of present instruction, if generating
Corresponding modification then is made to the SVS of the stack version table SL and present instruction that store entire program；It is entered step if not generating
(1125)；
Step (1125): repeating step (1124), executes lp times, terminates；
Step (1126): each is instructed, the maximum stack version of stack memory space in corresponding stack version set SVS is taken
Stack memory space as the instruction backup needed for stack memory space.
In the step (2), the behavior of Cahce refers to that Cache access hit and Cache access miss.
The step of step (2), is as follows:
Step (21): can obtain the dis-assembling code P' of insertion slot tag using step (17), to the anti-of insertion slot tag
Assembly code P' carries out Cache persistence analysis, records the Analysis of Persistence persistence range of every instruction；
Step (22): it calculates under cache hit situation, executes instruction consumption energy；
According to instruction set corresponding with processor, and consumed in each execution process instruction under cache hit situation
Energy balane instruction execution consumes ENERGY E ne (Ins_hit), and Ene (Ins_hit) includes that all types are instructed in cache hit
In the case of execute consumed by energy；
Step (23): it can be obtained under cache miss situation using step (13), the ENERGY E ne of the consumption executed instruction
(Ins_miss)；The ENERGY E ne (backup) of backup operation consumption can be obtained using step (14)；
Step (24): ins is instructed to each, it is assumed that energy warning occurs at instruction ins, utilizes instruction
Persistence range analyzes all possible path, determines the position of the long maximum slot tag of forward step in each path,
It is inserted into backup label；The slot tag for being not inserted into backup label is replaced with into NOP instruction.
Common persistence method in academia's Real Time System Analysis is borrowed.It is to the difference circulation in program
(loop) carry out persistence analysis respectively, the instruction of possible same can include in several cycles, such as after having analyzed,
Instructing ins is persistence in circulation a circulation b, is not persistence in circulation c.The instruction
The range of persistence is exactly to recycle a, b.Persistence is meant that: in particular range, from calling in cache,
It will not just replace away always and (i.e. in cache access, a cache miss can only occur).
Using the operating characteristic of persistence, when carrying out path analysis, if instruction ins is not persistence
, just analyzed by the execution energy consumption of Cache miss；If instructing ins is persistence, need further to judge
Be it is rear it is no be first time cache access, if for the first time just press cache miss execution energy consumption analysis；If not just pressing
The execution energy consumption analysis of cache hit.
The last one label is exactly the position of the maximum label of step-length of advancing in each path.
In the step (3):
Target, when energy warning occurs, is backed up in success in the non-volatile memory NVP based on NVM
Under the premise of program advance step-length it is maximum.After being inserted into backup label, to reach maximum advance step-length, to be crossed between possibility
Multiple backup labels.The power failure position (that is, for each instruction) for needing to occur for each determines a backup
Label position label, expression receive energy alarm signal at certain instruction, need the position in which backup label enterprising
Row backup.
The step of step (3) are as follows:
Step 31): ins is instructed for each, passes through NiIt counts on each possible path i started with the instruction
The number of backup label；
Step 32): N is takeniMinimum value min (Ni) as the backup label position mark for instructing ins.
The step of step (4) are as follows:
Step (41): it using the disassembler P ' of step (24) available insertion backup label, utilizes step (32)
The corresponding backup label position mark of every instruction can be obtained；
Step (42): operation disassembler P ', if receiving energy caution signal at instruction ins, program is continued to run,
And the number N um of the backup label since instructing ins is counted, whether the backup label position mark of inquiry Num and instruction ins
It is identical；If they are the same, program determination, and start to carry out backup operation；If not identical, program is continued to run, and continues statistics backup
The number N um of label.
Step (1) insertion slot tag be potential backup location, following step (2) by the behavior to Cache into
Row analysis, determines the position of backup label, so that guaranteeing under the premise of successfully backing up after receiving energy alarm signal every time
(no matter which way to go, can find a backup label), the step-length longest that program executes forward.Behavioural analysis to Cache,
We use the analysis method of the Cache persistence in WECT.Cache persistence block can only occur once
Cache miss, that is, after the access of first time Cache, access later can ensure it is that Cache is hit.Cache
After persistence has been analyzed, then the range of the persistence of available every instruction is instructed according to every
Persistence information determines the position of backup label.
NVP performance based on Cache perception optimizes standby system, characterized in that includes:
Off-line analysis unit and online management unit；
Wherein off-line analysis unit includes:
Slot tag is inserted into module: being configured as slot tag being inserted into the candidate point in dis-assembling code as backup location；
Dis-assembling code analysis module: being configured as analyzing the dis-assembling code with slot tag, slow to high speed
The behavior for rushing memory Cache is analyzed, and under the premise of guaranteeing successfully to back up, selects farthest slot tag to be inserted into standby
Part label；
Backup label position mark module: it is configured as carrying out backup label position mark to every instruction, indicates to receive
The instruction of energy alarm signal starts to be backed up on the backup label position of respective markers, so that instruction is starting to back up
Before, instruction operation reaches farthest advance step-length；
The online management unit includes:
Backup module: when being configured as encountering energy alarm signal in program operation process, to based on the non-volatile of NVM
Property processor NVP in main memory backup, the internal storage data other than stack space is by the way of full backup, and for stack sky
Between within data, program, which continues to run until at farthest backup label, just starts triggering backup, to realize that program receives energy
Maximum operation step-length can be run after alarm signal.
Beneficial effects of the present invention:
1 proposes that one is backed up (CAB) frame by the cache perception that off-line analysis and online management form, and analyzes calling program
More precisely；
2 may be implemented the maximum advance progress of program under the premise of successfully backing up；
3 improve the execution efficiency of program；
4 improve the utilization rate of energy.
Detailed description of the invention
Fig. 1 is volatibility processor and non-volatile memory operation principle schematic diagram；
Is backup (Instant) immediately is respectively adopted in Fig. 2, cache does not perceive (Cache-unaware), cache perception
(Cache-aware) the case where backup method analyzes example procedure；
Fig. 3 is the configuration diagram based on the Cache NVP system perceived；
Fig. 4 is that the NVP performance perceived based on Cache optimizes backup method and system solution flow chart.
Specific embodiment
The invention will be further described with embodiment with reference to the accompanying drawing.
We pass through an example illustratively below.As illustrated in fig. 2, it is assumed that energy caution signal is received at instruction 1,
Remaining utilisable energy is 31 (being only used for instruction execution and backup) in capacitor at this time, wherein instruction 6-10 access must be
Cache hit, the instruction consumption energy for executing Cache-miss is 1, and the energy for executing the instruction consumption of Cache-hit is
The energy of 0.2, NVM backup, one unit consumption is 10.Within the scope of remaining utilisable energy, according to traditional backup side
Formula backs up (Instant) immediately, then has executed instruction 1 with regard to directly being backed up, program is after power failure to preceding at this time
Perform 1 step.The backup mode (Cache-unaware) not perceived according to Cache conservatively assumes all instructions access all
It is Cache miss, program most backs up after having executed instruction 5, and program is after power failure to preceding holding at this time
5 steps are gone.According to the backup mode (Cache-aware) of Cache perception, since instruction 6-10 access must be Cache life
In, program most backs up after having executed instruction 12, and program performs forward 12 steps again after power failure at this time.
Above-mentioned three kinds of methods are compared, and after receiving energy alarm signal, using the third method, forward step is maximum forward for program, i.e.,
The backup point looked for is farthest.This also means that it is most fast that the program of the third backup mode executes rate under same case.Therefore, I
Propose based on Cache perception NVP performance optimize backup scenario, target be guarantee receive energy warning after, utilize
The behavioural information of Cache finds a backup location as far as possible, improves the advance step-length of program, promotes program and executes rate
And system performance.
As shown in figure 3, the structural schematic diagram of the NVP system of Cache based on instruction.
Non-volatile memory NVP based on NVM, including CPU, the CPU include the register based on non-volatile memory
Group, the CPU are connect with main memory, and the CPU is also connect with instruction-level cache register I-Cahce；The main memory
Reservoir is connect with instruction-level cache register I-Cahce；The main memory is also connect with nonvolatile memory NVM.
To all instructions, CPU will first access I-Cache, and only in the case where access miss, CPU is just gone in access
It deposits, and the instruction of miss is stored in I-Cache.In non-volatile memory NVP based on NVM, the register group in CPU
It is the register group based on non-volatile memory, the non-volatile row data in register can be backed up；Non-volatile memories
Device NVM is an individual block storage, for backing up to primary storage data therein.
When energy warning occurs, data carry out full backup with non volatile register in register, in Instruction Cache
Data do not need to back up, the data in main memory are selectively backed up.Dynamic memory size is companion in main memory
Change with program execution, wherein stack space is the important component in dynamic memory.Therefore, to non-volatile memory
Backup in piece on main memory, internal storage data other than stack space we by the way of full backup, and for stack space
Part, the maximum value for the stack space that we go determination to be backed up according to its dynamic size rule.
From the example of front Fig. 2, it is easy to it is huge to find out that the information of Cache provides the advance progress for improving NVP
Potentiality.Backup operation is usually to be realized by being inserted into certain special instruction in program.This brings very big shadow to caching analysis
It rings, because the address of instruction and Cache content all can correspondingly change after insertion extra-instruction.So will be according to Cache
Behavior come determine insertion backup instruction position.The present invention is based on the schematic diagrames of the NVP performance optimization backup scenario of Cache perception
As shown in figure 4, including off-line analysis and the big module of online management two.In off-line analysis, slot tag is first inserted into former dis-assembling
As the candidate point of backup location in code, then the dis-assembling code with slot tag is analyzed, the row according to Cache
With the characteristics of, under the premise of can guarantee successfully to back up, farthest slot tag is selected to be inserted into backup label.At runtime, most
Triggering backup is at remote label to realize program maximum advance step-length.
1, it is inserted into slot tag
The main reason for slot tag is inserted into source dis-assembling code is to be inserted into the memory address instructed after slot tag to be exactly
Fixed, so that it may position of the determine instruction in Cache, so that it may which Cache behavioural analysis is carried out to program.Slot tag is made
For the candidate point of backup label, backup label or NOP operation replacement slot tag can be finally used in a program.
The method and step for being inserted into slot tag is as follows:
1) former disassembler P is analyzed, determines the stack space size of every instruction backup；
2) P ' indicates the disassembler after insertion slot tag, initializes P ', P is copied in P '；
3) first instruction of program is put into queue Q by initialization directive queue Q；
4) head of the queue is taken out from queue Q and instruct ins, to former disassembler P, it is assumed that at instruction ins, it is alert to receive energy
Accuse signal, according to inequality (1), analyze all possible path in remaining available energy range, find it is farthest can be with
The instruction ins ' that success is backed up, the instruction ins ' in P ' are previously inserted into a slot tag and will instruct ins ' addition queue Q, so
The instruction ins in Q is deleted afterwards；
5) step 4) is repeated, until queue Q is sky, end, the disassembler P ' after returning to insertion slot tag.
The implementation procedure for being inserted into slot tag algorithm is as follows:
2, the backup label selection based on Cache behavior perception
The slot tag of insertion is potential backup location, next needs to analyze by the behavior to Cache, determine
The position of backup label, so that guaranteeing (any item no matter walked under the premise of successfully backing up after receiving energy alarm signal every time
Road can find a backup label), the step-length longest that program executes forward.Behavioural analysis to Cache, we use
The analysis method of Cache persistence in WECT.Cache, which can only occur, for Cache persistence block does not order
In, that is, after the access of first time Cache, access later can ensure it is that Cache is hit.Cache persistence points
After having analysed, the range of the persistence of available every instruction, the persistence information then instructed according to every
Determine the position of backup label.
Based on Cache behavior perception backup label selection method the step of it is as follows:
1) Cache persistence analysis is carried out to the dis-assembling code of insertion slot tag, records every instruction
Persistence range；
2) ins is instructed to each, it is assumed that energy warning occurs at instruction ins, believes using the persistence of instruction
Breath, analyzes all possible path, determines the position of the long maximum slot tag of forward step in each path, is inserted into backup label；
3) slot tag for being not inserted into backup label is replaced with into NOP instruction.
The implementation procedure of backup label selection algorithm based on Cache behavior perception is as follows:
3, the selection of backup label position
It, be under the premise of successfully backing up it is an object of the present invention to when power failure occurs, the advance step-length of program is most
Greatly.After being inserted into backup label, to reach maximum advance step-length, multiple backup labels are crossed between possibility.
The power failure position (that is, for each instruction) for needing to occur for each determines a backup label position
Tagging, expression receive energy alarm signal at certain instruction, need to be backed up on the position of which backup label.
To achieve it, for each instruction, one number of label, instruction will be across how much standby before trigger backup operation
Part label, the size of this number.This reference numerals takes farthest backup label on all possible paths started with the instruction
Minimum value.For example, instruction ins there are three possible paths, there are 3,4,5 backup labels in each path respectively, then ins
Backup reference numerals be 3.In this way, if power failure occurs at instruction ins, program will continue to when practical programs are run
It executes forward, after encountering the 3rd backup label, can just trigger backup operation.
4, when operation, backs up
The disassembler of operation insertion slot tag, if receiving energy caution signal at instruction ins, program is after reforwarding
Row, and the number N um of the backup label since instructing ins is counted, inquiry Num and the backup label position mark for instructing ins
It is whether identical；If they are the same, program determination, and start to carry out backup operation；If not identical, program is continued to run, and continues to count
The number N um of backup label.
So, if certain instruction receives energy caution signal, will continue to execute, referring to until encountering this in NVP system
The backup label of the backup label position mark of order can just trigger backup operation.
It, be under the premise of successfully backing up it is an object of the present invention to when power failure occurs, the advance step-length of program is most
Greatly.After being inserted into backup label, to reach maximum advance step-length, multiple backup labels are crossed between possibility.We need
A backup location label is determined for each possible power failure position (that is, for each instruction), if indicating at certain
Energy alarm signal is received at instruction, needs to back up on the position of which backup label.To achieve it, for every
A instruction, one number of label, instruction how many backup label are crossed over before triggering backup operation.This reference numerals,
It need to be calculated by all possible path started with the instruction, be denoted as the public rope of maximum of the backup label in all paths
Draw.For example, instruction ins there are three possible paths, there are 3,4,5 backup labels in each path respectively, then the backup of ins
Reference numerals are 3.In this way, if power failure occurs at instruction ins, program will continue to hold forward when practical programs are run
Row, after encountering the 3rd backup label, can just trigger backup operation.
The reference of Cache persistence analysis method:
C.Cullmann.Cache persistence analysis:Theory and practice.ACM
Trans.Embed.Comput.Syst.,12(1s):40:1–40:25,Mar.2013.
Above-mentioned, although the foregoing specific embodiments of the present invention is described with reference to the accompanying drawings, not protects model to the present invention
The limitation enclosed, those skilled in the art should understand that, based on the technical solutions of the present invention, those skilled in the art are not
Need to make the creative labor the various modifications or changes that can be made still within protection scope of the present invention.
Claims (10)
1. the NVP performance based on Cache perception optimizes backup method, characterized in that include the following steps:
Off-line analysis step and online management step；
Wherein off-line analysis step includes:
Step (1): slot tag is inserted into the candidate point in dis-assembling code as backup location；
Step (2): analyzing the dis-assembling code with slot tag, carries out to the behavior of cache memory Cache
Analysis selects farthest slot tag to be inserted into backup label under the premise of guaranteeing successfully to back up；
Step (3): carrying out backup label position mark to every instruction, the instruction for receiving energy alarm signal is indicated, corresponding
Start to be backed up on the backup label position of label, so as to instruct before starting backup, before instruction operation reaches farthest
Progress length；
The online management step includes:
Step (4): when encountering energy alarm signal in program operation process, in the non-volatile memory NVP based on NVM
The backup of main memory, the internal storage data other than stack space is by the way of full backup, and for the data within stack space,
Program, which continues to run until at farthest backup label, just starts triggering backup, with realize can after program receives energy alarm signal
The maximum operation step-length of operation.
2. the NVP performance as described in claim 1 based on Cache perception optimizes backup method, characterized in that
The reason of slot tag is inserted into dis-assembling code by the step (1) is to be inserted into the memory address instructed after slot tag to be exactly
Fixed, so that it may position of the determine instruction in cache memory Cache, so that it may which Cache behavior is carried out to program
Analysis.
3. the NVP performance as described in claim 1 based on Cache perception optimizes backup method, characterized in that
The step of step (1), is as follows:
Step (11): analysis disassembler P, stack memory space needed for determining every instruction backup；
Step (12): dump energy distribution model is established；
Utilisable energy remaining first should meet subsequent program and execute, and meet the backup of stack again；
Position p is a feasible backup location, then remaining utilisable energy want can support program go to p and back up p
Stack in all the elements:
aveEne≥Ene(Ins)+Ene(backup) (1)
Wherein, aveEne indicates remaining utilisable energy, and Ene (Ins) expression executes instruction consumption energy, Ene (backup) table
Show that backup operation consumes energy；Ene (Ins) indicates the energy consumed in each execution process instruction under cache miss situation
Amount calculates instruction execution consumption ENERGY E ne (Ins_miss) or consumes in each execution process instruction under cache hit situation
Energy balane instruction execution consume ENERGY E ne (Ins_hit)；
Step (13): calculating under cache miss situation, and instruction execution consumes energy；
According to instruction set corresponding with the non-volatile memory based on NVM, and under cache miss situation, each instruction is held
The energy balane instruction execution consumed during row consumes ENERGY E ne (Ins_miss), and Ene (Ins_miss) includes all types
Instruction executes consumed energy under cache miss situation；
Step (14): it calculates backup operation and consumes energy；
According to Energy Expenditure Levels in different NVM backup procedures, and the energy consumed during the content backup to be backed up
It is proportional to memory space occupied by the content to be backed up, calculate backup operation consumption ENERGY E ne (backup)；
Step (15): P' indicates the disassembler after insertion slot tag, by disassembler P assignment into P', initializes P'；
Step (16): first instruction of program is put into queue Q by initialization directive queue Q；
Step (17): head of the queue is taken out from queue Q and instructs ins, to disassembler P, it is assumed that at instruction ins, receive energy
Caution signal analyzes all possible path according to formula (1) within the scope of remaining utilisable energy, find it is farthest can be with
The instruction ins ' that success is backed up, the instruction ins ' in P' are previously inserted into a slot tag and will instruct ins ' addition queue Q, so
The instruction ins in Q is deleted afterwards；
Repeat step (17), until queue Q be sky, terminate and export insertion slot tag after disassembler P'.
4. the NVP performance as claimed in claim 3 based on Cache perception optimizes backup method, characterized in that
The step of step (11), is as follows:
Step (111): by former binary program dis-assembling at disassembler, according to the precedence relationship instructed in disassembler
Establish program control flow chart CFG；CFG is the abbreviation of control flow graph；
Step (112): stack analysis of version.
5. the NVP performance as claimed in claim 4 based on Cache perception optimizes backup method, characterized in that
In the step (111):
Disassembler is divided into four major class: unconditional jump instruction, conditional jump instructions, function call instruction and sequence execute
Instruction；
The realization function of instructing according to every, that establishes every instruction enters line set and out line set, it is described enter line set include
The set of all previous item instructions of present instruction；The previous item instruction of present instruction has one or more；The line set out
The set of all latter item instructions including present instruction；The latter item instruction of present instruction has one or more.
6. the NVP performance as claimed in claim 4 based on Cache perception optimizes backup method, characterized in that
The step of step (112), is as follows:
Step (1121): assuming that SVS indicates the version set of the stack of every instruction, SL indicates to store the stack version of entire program
Table, the cycle-index of lp representation program first carry out initialization of variable；
Step (1122): whether the storage size of stack is had an impact according to instruction, instruction is divided into stack-
Affected instruction and stack-unaffected instruction；It is big that stack-affected refers to that instruction execution will affect stack
Small instruction；Stack-unaffected refers to instruction execution but not influences the instruction of stack size；
Step (1123): the topological order list Seq of entire program is established according to CFG；
Step (1124): the topological order according to topological order list Seq analyzes each instruction；If present instruction is
Stack-unaffected instruction, directly after brought forward after the stack of instruction version set SVS；If present instruction is stack-
Affected instruction further analyzes the stack that influences and whether can generate new version of the execution to stack of present instruction, if generating
Corresponding modification then is made to the SVS of the stack version table SL and present instruction that store entire program；It is entered step if not generating
(1125)；
Step (1125): repeating step (1124), executes lp times, terminates；
Step (1126): each is instructed, the stack of the maximum stack version of stack memory space in corresponding stack version set SVS is taken
Memory space is as stack memory space needed for instruction backup.
7. the NVP performance as claimed in claim 3 based on Cache perception optimizes backup method, characterized in that
In the step (2), the behavior of Cahce refers to that Cache access hit and Cache access miss；
The step of step (2), is as follows:
Step (21): can obtain the dis-assembling code P' of insertion slot tag using step (17), the dis-assembling to insertion slot tag
Code P' carries out Cache persistence analysis, records the Analysis of Persistence persistence range of every instruction；
Step (22): it calculates under cache hit situation, executes instruction consumption energy；
According to instruction set corresponding with processor, and the energy consumed in each execution process instruction under cache hit situation
Computations execute consumption ENERGY E ne (Ins_hit), and Ene (Ins_hit) includes that all types are instructed in cache hit situation
Energy consumed by lower execution；
Step (23): can be obtained under cache miss situation using step (13), and instruction execution consumes ENERGY E ne (Ins_
miss)；The ENERGY E ne (backup) of backup operation consumption can be obtained using step (14)；
Step (24): ins is instructed to each, it is assumed that energy warning occurs at instruction ins, utilizes instruction
Persistence range analyzes all possible path, determines the position of the long maximum slot tag of forward step in each path,
It is inserted into backup label；The slot tag for being not inserted into backup label is replaced with into NOP instruction.
8. the NVP performance as claimed in claim 7 based on Cache perception optimizes backup method, characterized in that
The step of step (3) are as follows:
Step (31): ins is instructed for each, passes through NiCount the backup on each possible path i started with the instruction
The number of label；
Step (32): N is takeniMinimum value min (Ni) as the backup label position mark for instructing ins.
9. the NVP performance as claimed in claim 8 based on Cache perception optimizes backup method, characterized in that
The step of step (4) are as follows:
Step (41): it using the disassembler P ' of step (24) available insertion backup label, can be arrived using step (32)
The corresponding backup label position mark of every instruction；
Step (42): operation disassembler P ', if receiving energy caution signal at instruction ins, program is continued to run, and unites
The number N um of the backup label since instructing ins is counted, whether inquiry Num is identical as the backup label position mark of instruction i；
If they are the same, program determination, and start to carry out backup operation；If not identical, program is continued to run, and continues to count backup label
Number N um.
10. the NVP performance based on Cache perception optimizes standby system, characterized in that include:
Off-line analysis unit and online management unit；
Wherein off-line analysis unit includes:
Slot tag is inserted into module: being configured as slot tag being inserted into the candidate point in dis-assembling code as backup location；
Dis-assembling code analysis module: it is configured as analyzing the dis-assembling code with slot tag, speed buffering is deposited
The behavior of reservoir Cache is analyzed, and under the premise of guaranteeing successfully to back up, farthest slot tag is selected to be inserted into backup mark
Label；
Backup label position mark module: it is configured as carrying out every instruction backup label position mark, expression receives energy
The instruction of alarm signal starts to be backed up on the backup label position of respective markers, so as to instruct before starting backup,
Instruction operation reaches farthest advance step-length；
The online management unit includes:
Backup module: when being configured as encountering energy alarm signal in program operation process, to the non-volatile place based on NVM
The backup for managing main memory in device NVP, the internal storage data other than stack space by the way of full backup, and for stack space with
Interior data, program, which continues to run until, just starts triggering backup at farthest backup label, to realize that program receives energy alarm
Maximum operation step-length can be run after signal.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102156652A (en) * | 2011-04-26 | 2011-08-17 | 中兴通讯股份有限公司 | Mobile terminal and updating method for mobile terminal |
| CN102385637A (en) * | 2011-12-22 | 2012-03-21 | 山东中创软件商用中间件股份有限公司 | Backup method and system for database information |
-
2017
- 2017-01-16 CN CN201710029385.8A patent/CN106844101B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102156652A (en) * | 2011-04-26 | 2011-08-17 | 中兴通讯股份有限公司 | Mobile terminal and updating method for mobile terminal |
| CN102385637A (en) * | 2011-12-22 | 2012-03-21 | 山东中创软件商用中间件股份有限公司 | Backup method and system for database information |
Non-Patent Citations (2)
| Title |
|---|
| Fixing the Broken Time Machine:Consistency-Aware Checkpoint for Energy Harvesting Powered Non-Volatile Processor;Mimi Xie;《2015 ACM》;20150611;全文 * |
| Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications;Kaisheng Ma;《IEEE Computer Society》;20151231;全文 * |
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