CN106842898A - Synchronization adjustment method during a kind of aeronautical satellite time dual clock domain high-precision real - Google Patents
Synchronization adjustment method during a kind of aeronautical satellite time dual clock domain high-precision real Download PDFInfo
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- CN106842898A CN106842898A CN201611246856.2A CN201611246856A CN106842898A CN 106842898 A CN106842898 A CN 106842898A CN 201611246856 A CN201611246856 A CN 201611246856A CN 106842898 A CN106842898 A CN 106842898A
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/02—Details of the space or ground control segments
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/03—Cooperating elements; Interaction or communication between different cooperating elements or between cooperating elements and receivers
- G01S19/05—Cooperating elements; Interaction or communication between different cooperating elements or between cooperating elements and receivers providing aiding data
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- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Electric Clocks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Synchronization adjustment method during a kind of aeronautical satellite time dual clock domain high-precision real, parsed after receiving the data frame that ground sends first, second will be parsed in the week for obtaining, uplink distance measuring value and the time synchronized instruction of star ground are sent to satellite load, then judged, if data frame is instructed including time synchronized, then calculate pps pulse per second signal, and then obtain result POS of the new aeronautical satellite time to 1s complementations, if do not instructed including time synchronized, then each clock adjustment the cycle carry out accumulation operations, obtain new complementation result POS, aeronautical satellite time corresponding periodicity is updated finally according to new complementation result POS, second SOW in all, and then complete aeronautical satellite time synchronized.
Description
Technical field
The present invention relates to Satellite Navigation Technique, particularly a kind of aeronautical satellite time dual clock domain high accuracy real-time synchronization is adjusted
Adjusting method.
Background technology
, it is necessary to carry out time synchronized with ground after aeronautical satellite start, the aeronautical satellite time is adjusted to and ground elapsed time
Unanimously.Existing satellite time method of adjustment mainly includes two classes, one be by adjust satellite frequency come it is slow adjust satellite when
Between, the method has the disadvantage that：Take more long, the terrestrial user stand-by period long, it is impossible to realize multi-clock zone synchronous adjustment；Two
It is that satellite time is adjusted by the method for directly adjustment satellite time register, the method is regulated the speed soon, but the method is still
Multi-clock zone synchronous adjustment cannot so be realized.
The content of the invention
Present invention solves the technical problem that being：Overcome the deficiencies in the prior art, there is provided when a kind of aeronautical satellite time is double
The synchronization adjustment method during high-precision real of clock domain, solves existing satellite time method of adjustment time-consuming more long or can not be simultaneously real
The problem of existing multiple clock zone clock adjustment, shortens adjustment time, and can realize that two clock zones are same compared with prior art
Successive step.
Technical solution of the invention is：Synchronous adjustment side during a kind of aeronautical satellite time dual clock domain high-precision real
Method, comprises the following steps：
(1) control Satellite Payloads receive the uplink data frames that ground sends using uplink receiver；Described is up
Data frame include star ground time synchronized instruction, week in second SOW or uplink distance measuring value PR, wherein, star ground time synchronized instruction for control
System carries out the instruction of aeronautical satellite time dual clock domain real-time synchronization adjustment；Described uplink distance measuring value PR is Present navigation satellite
The time difference of time in time and uplink data frames；
(2) uplink data frames parse with obtaining star time synchronized instruction, second SOW or uplink distance measuring value PR in week,
And deliver to satellite time generation and keep load；
(3) satellite time generation is judged with load is kept, if receiving the time synchronized instruction of star ground, is transferred to
Step (4), is otherwise transferred to step (6)；
(4) second SOW in week is delivered to the time management FPGA of satellite, according to uplink distance measuring value PR, star ground time delay preset value
RR, calculating aeronautical satellite time pps pulse per second signal 1PPS adjusted value Δ POS is
Δ POS=round { Δ t*fFPGA}
Wherein, round { } is rounding operation, and the unit of Δ t=PR-RR, Δ t is s, fFPGANeeded for the adjustment of expression time
Working clock frequency, Δ POS represents aeronautical satellite time lead ground elapsed time for positive, and Δ POS is the negative indication aeronautical satellite time
Fall behind ground elapsed time；
Aeronautical satellite time pps pulse per second signal 1PPS adjusted value Δ POS, the time synchronized instruction of star ground are sent to time pipe
Manage two different clock-domains of FPGA；
(5) following time adjustment operation is carried out respectively in each clock zone：Control time manages FPGA in 1 clock week
By in second SOW register in the week of second SOW write-in aeronautical satellite times in week in phase, POS is calculatedold+ Δ POS+1, if
POSold+ Δ POS+1 is less than 0, then calculate POSold+ΔPOS+1+fFPGAThe phase of aeronautical satellite time is inserted as new POS
Register POS_reg, then carries out subtracting one operation by phase register POS_reg；If POSold+ Δ POS+1 is more than or equal to
fFPGA, then by POSold+ΔPOS+1-fFPGAThe phase register POS_reg of aeronautical satellite time is inserted as new POS, then
Phase register POS_reg is added into 1 operation, if POSold+ Δ POS+1 is more than or equal to 0 and less than fFPGA, then by POSold+Δ
POS+1 inserts the phase register POS_reg of aeronautical satellite time as new POS；Wherein, POS is the aeronautical satellite time pair
The result of 1s complementations；POSoldIt is corresponding POS before the adjustment of aeronautical satellite time；
(6) in the operating clock cycle needed for the adjustment of each time, aeronautical satellite time pps pulse per second signal 1PPS phase is controlled
Bit register POS_reg cumulative 1, by the register of second SOW in week cumulative 1；Wherein, when phase register POS_reg is equal to
fFPGAWhen, phase register POS_reg is reset, when the register of second SOW in week is equal to 604799, by second SOW in week
Register resets；
(7) when updating aeronautical satellite using the POS in the phase register POS_reg of aeronautical satellite time pps pulse per second signal
Between corresponding periodicity WN, number of seconds SOW in the week in week in second SOW register, and then complete aeronautical satellite time synchronized.
Described fFPGAComputational methods comprise the following steps：
(1) working clock frequency needed for obtaining two clock zone time adjustment；
(2) greatest common divisors of the working clock frequency needed for being calculated the adjustment of two clock zone times, and as when
Between adjust required working clock frequency fFPGA。
Described PR ∈ [0,1000ms), RR=82ms.
Present invention advantage compared with prior art is：The inventive method is adjusted compared with existing with the time
High precision, time adjustment take less, are capable of achieving the advantages of two clock zone synchronous adjustments, and 1PPS phases are adjusted in the inventive method in addition
The adjustment of whole and second counting phase independently is carried out, except carry and to borrow operation outer, without interacting, it is to avoid the counting of appearance second is adjusted out
Existing 1 whole second problem of deviation.
Brief description of the drawings
Protocol procedures figure when Fig. 1 is experiment star school；
Fig. 2 is the correction of the inventive method Satellite time, keeps and distribution method flow chart；
Fig. 3 is networking Adjusted Option star time, flow graph time；
Fig. 4 is the adjustment process analysis procedure analysis of a variety of satellites and ground phase difference situation.
Specific embodiment
The present invention in view of the shortcomings of the prior art, when proposing a kind of dual clock domain high-precision real of new satellite navigation time
Synchronization adjustment method, has the advantages that time Adjustment precision is high, time adjustment is time-consuming less, be capable of achieving two clock zone synchronous adjustments,
1PPS (1 Pulse Per Second) phase adjustments and the adjustment of second counting phase are independently carried out in other the inventive method, remove into
Position and to borrow operation outer, without interaction, it is to avoid the second occur counts adjustment and 1 whole second problem of deviation, the inventive method step occur
It is rapid as follows：
(1) uplink receiver of Satellite Payloads receives uplink data frames DUP2 yards that terrestrial user sends, wherein, bag
Containing the time synchronized instruction of star ground；
(2) after uplink receiver receives DUP2 yards of frame head of data of the frame, within 100ms, by second, uplink distance measuring in week
Value (scope for [0~1000ms), notes including 0s, not including 1s) and star time synchronized the other information such as instruct by bus
It is sent to satellite time generation and keeps load；
(3) satellite time generation receives the data that the uplink receiver in bus is sent with the CPU of load is kept, if
Time synchronized instruction is wherein contained, the operation of following steps is performed：
(3.1) extracted from the 0th frame of DUP2 yards of uplink data sending frame in week the second (SOW), and calculate SOW%30,
SOW%18, SOW%6, SOW%3 are sent to time management FPGA, and the time of satellite is divided into periodicity (WN：Week Number)、
Number of seconds (SOW in all:Second of Week) and small time several seconds (POS：Position Of Second), POS is when fashion
The star time is to the result of 1s complementations, POSoldRepresent the POS before satellite time adjustment；
(3.2) according to uplink distance measuring value (PR) and star ground time delay preset value (RR), aeronautical satellite time (1PPS) tune is calculated
After whole value Δ POS, uplink distance measuring value PR receive the upward signal of ground master station transmitting for satellite load, conciliate according to tracking
The result of tune, calculates the time difference of time in satellite time and upward signal as uplink distance measuring value PR；
Δ t=PR-RR, wherein PR ∈ [0,1000ms), RR=82ms, Δ t ∈ [- 82ms, 918ms)；
(3.3) the timeticks quantity that Δ t is converted to FPGA is sent to time management FPGA as adjustment amount, and Δ t turns
The method for being changed to the timeticks quantity of FPGA is：
Δ POS=Δs t × fFPGA, wherein, fFPGARepresent the clock frequency that time management is used；
The Δ POS for now obtaining contains sign, and is that 1PPS is opened on star in view of the measuring method of uplink distance measuring value PR
Door, the 1PPS of the up ground elapsed time for recovering close the door, therefore the implication of the sign of Δ POS is as follows：
Δ POS positive signs represent satellite time advanced ground elapsed time, it is necessary to satellite time is carried out into hysteretic operation；
Δ POS positive signs represent satellite time advanced ground elapsed time, it is necessary to satellite time is carried out into hysteretic operation；
(3.4) adjustment amount is sent to time management FPGA；
(3.5) after CPU is calculated and finished, the instruction for starting star ground time synchronized is sent to time management FPGA at once, CPU's
There is no other command operatings between two instructions, the transmission time should be at the 200ms~500ms during Big Dipper of ground；
(4) if FPGA is not received by time synchronized instruction, each clock cycle, following operation is performed：
(4.1) 1PPS phase registers (POS_reg) cumulative 1；
(4.2) when 1PPS phase registers tired (POS_reg) fill it up with 1 whole second (fFPGA) when, POS_reg resets, SOW_reg
Cumulative 1,30s accumulator registers, 18s accumulator registers, 6s accumulator registers, 3s accumulator registers cumulative 1；
(4.3) after SOW_reg fills it up with 1 complete cycle (604799), SOW_reg resets；The cumulative deposit of 30s accumulator registers, 18s
After device, 6s accumulator registers, 3s accumulator registers fill it up with 18s, 6s, 3s, reset respectively；
(4.4) reset after the full 30s of 30s accumulator registers；
(4.5) reset after the full 18s of 18s accumulator registers；
(4.6) reset after the full 6s of 6s accumulator registers；
(4.7) reset after the full 3s of 3s accumulator registers；
(5) if FPGA receives time synchronized instruction, following operation is performed：
(5.1) FPGA receives the SOW that CPU is inserted；
(5.2) FPGA receives SOW%30, SOW%18, SOW%6, SOW%3 that CPU is inserted；
(5.3) FPGA receives the Δ POS that CPU is inserted；
(5.4) FPGA receives the startup time synchronized instruction that CPU is inserted；
(5.5) FPGA1 is operated below execution in 1 time management clock cycle：
Second register in adjustment week：Using sequence circuit, by CPU write enter the SOW of FPGA1, SOW%30, SOW%18,
The new value of SOW%6, SOW%3 is inserted in the register of SOW, SOW%30, SOW%18, SOW%6, SOW%3；
Adjustment 1PPS phase registers：Using sequence circuit, within a clock cycle, POS is judgedold+ Δ POS+1's
Value (notes：Time synchronized operation needs 1 clock cycle in itself, so needing "+1 ")
If less than 0 (i.e.：The value of POSold+ Δs POS+1 is negative), by POSold+ Δs POS+1+fFPGAAs new
POS is inserted in POS registers (POS_reg)；The cumulative deposit of SOW registers, 30s accumulator registers, 18s accumulator registers, 6s
Device, 3s accumulator registers need to carry out it is extra borrow operation, that is, the operation that subtracts；
If greater than equal to 1 second (POSoldThe value of+Δ POS+1 is more than or equal to fFPGA), by POSold+ΔPOS+1-fFPGAMake
For new POS is inserted in POS registers (POS_reg)；SOW registers, 30s accumulator registers, 18s accumulator registers, 6s tire out
Plus register, 3s accumulator registers need to carry out extra carry operation, i.e., Jia 1 and operate；
If greater than equal to 0, less than or equal to 1 second, by POSold+ Δ POS+1 inserts POS registers as new POS
(POS_reg) in；SOW registers, 30s accumulator registers, 18s accumulator registers, 6s accumulator registers, 3s accumulator registers are not
Extra plus/minus 1 is carried out to operate；
Clock management module work clock fFPGASystem of selection, comprise the following steps：To ensure B2/B3/S
(61.38MHz/122.76MHz/245.52MHz clock zones) and B1 (85.932MHz/171.864MHz clock zones) are with satellite
The adjustment of time, the navigation signal that synchronous adjustment is broadcast need to be to being respectively provided with the deposit of 1PPS phase adjustments under two clock zones
Device POS_Reg, the 1PPS phases difference set time Δ τ under two clock zones, and during school, phase modulation do not influence the value of Δ τ, that is, protect
During card school, before and after phase modulation, under 61.38MHz/122.76MHz/245.52MHz and 85.932MHz/171.864MHz clock zones
The phase difference of 1PPS is constant.
In order to realize the function, the greatest common divisor 12.276MHz for finding 61.38MHz and 85.932MHz is adjusted as phase
Whole frequency, phase adjustment value calculating method and set-up procedure are as follows：
(1) CPU according to uplink distance measuring value be calculated star ground clock correction Δ t, for MEO clock correction scope for [- 82ms,
918ms), the clock correction is 32bits signed numbers；
(2) middle adjustment amount is calculated according to clock correction Δ t, computational methods are：Round { Δ t (unit is s) * fFPGA, wherein
Round { } is rounding operation, and this causes phase adjustment step-length to be 81.45ns；
(3) in the phase adjustment register inserted in FPGA the adjustment amount (32bits signed numbers), for adjusting
The phase of the 1PPS in FPGA1.
The FPGA implementation method of big bit wide and two-forty, comprises the following steps in phase adjustment function：FPGA1 and FPGA2
Interior time management module is operated under 61.38MHz and 85.932MHz clocks respectively, because clock frequency is higher, and FPGA1
With the clock 245.52MHz and 171.864MHz, FPGA1 of higher rate and the Clock management mould of FPGA2 are run in FPGA2
After block completes placement-and-routing, by static timing analysis (STA) instrument, the operating rate of Clock management module is not reached
61.38MHz and 85.932MHz clocks.
To solve the problem, critical path is analysed in depth by STA, discovery realizes POS within a clock cycleold+Δ
POS+1+fFPGA、POSold+ΔPOS+1-fFPGAAnd POSoldThe combinational logic of+Δ POS+1 is the critical path of time management module
Footpath.
Adopt and solve sequence problem with the following method：
(1) CPU no longer inserts Δ POS values to FPGA1, FPGA2, but inserts Δ POS+1+f to FPGA1, FPGA2FPGA、
ΔPOS+1-fFPGAWith Δ POS+1 so that FPGA1, FPGA2 avoid multiple continuous add operations；
(2) according to the universal method for solving critical path, improving circuit sequence, combinational logic is broken up, POSold+ΔPOS
+1+fFPGA、POSold+ΔPOS+1-fFPGAAnd POSold+ Δ POS+1 original computing completes operation within 1 clock cycle, existing
Computing realized within 3 clock cycle；
(3) Δ POS+1+f is inserted in CPUFPGA、ΔPOS+1-fFPGAAfter Δ POS+1, CPU is most inserted after 250ns soon
Enabled instruction (1 cpu instruction cycle of interval, CPU speed of service 60MHz, each instruction cycle inserts 15 latent periods).And
Δ POS+1+f is inserted in CPUFPGA、ΔPOS+1-fFPGAAfter Δ POS+1, FPGA carries out POS at onceold+(ΔPOS+1+
fFPGA)、POSold+(ΔPOS+1-fFPGA) and POSold+ (Δ POS+1) computings, computing is complete within 3 61.38MHz clock cycle
Into operation time is about 48.8ns, less than 250ns, therefore can complete above-mentioned computing before CPU inserts adjustment enabled instruction.
If inserting Δ POS+1+f in CPUFPGA、ΔPOS+1-fFPGAAfter Δ POS+1, FPGA completes POSold+Δ
POS+1+fFPGA、POSold+ΔPOS+1-fFPGAWith POSold+ Δ POS+1 computings, but because CPU work is relatively slow, put in CPU
Enter before adjusting enabled instruction, FPGA have updated POSoldValue (POSoldValue per 1/fFPGA=1/12.276MHz updates once),
Need to recalculate POSold+ΔPOS+1+fFPGA、POSold+ΔPOS+1-fFPGAAnd POSold+ΔPOS+1.FPGA is by design
Ensure to complete fortune using 3 clock (each 12.276MHz clock there are 5 61.38MHz clock cycle) cycles of 61.38MHz
Calculate, i.e., complete computing before the renewals of POSold next time, the inventive method is described in detail below in conjunction with the accompanying drawings.
Protocol procedures figure when as shown in Figure 1 for experiment star school, existing satellite time method of adjustment comprises the following steps：
(1) step 1：The instruction space is transmitted
Space vector transfer phase refers to that signal is in space propagation and by up note after ground sends time synchronized instruction
Enter receiver and deliver to satellite time generation and the time for keeping load.Time-consuming about 1s.
(2) step 2：Wait 90N-1
After CPU software receives time synchronized instruction, instructed when waiting ground elapsed time to during 90N-1 to FPGA transmission schools,
At most wait 90s.Due to being designed as while adjust all signals for FPGA experiment stars, so the cycle of all signals must be waited until
Least common multiple when can just be adjusted.
(3) step 3：Instruction treatment during school
When sending school to FPGA after instruction, CPU software enters standby mode, does not process now and does not also send any information,
During to ensure that FPGA has time enough to complete school, CPU waits the interruption of FPGA to start working after waiting 20s.
(4) step 4：Wait uplink distance measuring value stabilization
After the completion of during school, information is completed when CPU software is to device broadcasts school in 1553B buses, 5s, per second 1 are broadcasted altogether
It is secondary.Now up injection receiver is started working, then thinks uplink distance measuring value stabilization after waiting 13 seconds, now begins to use range finding
Value carries out phase modulation.
(5) step 5：First time phase modulation
After CPU software sends phase modulation instruction to FPGA, into standby mode, think that phase modulation has completed to wait after waiting 8s
FPGA is interrupted after arriving and started working.
(6) step 6：Second phase modulation
If star ground time delay is more than 500ms, a phase modulation cannot be adjusted in place also need and carry out second phase modulation, second phase modulation
Execution is got started after the completion of first time phase modulation, implementation procedure is with first time phase modulation.
The existing time Adjusted Option flow of table 1 and time consuming analysis
It is illustrated in figure 2 the correction of satellite time, keeps and distribution method flow chart, is illustrated in figure 3 the networking star time
Adjusted Option time flow graph, the correction of satellite time, keeps and distribution method, comprises the following steps：
(1) uplink receiver of Satellite Payloads receives uplink data frames DUP2 yards that terrestrial user sends, wherein wrapping
Containing the time synchronized instruction of star ground；
(2) after uplink receiver receives DUP2 yards of frame head of data of the frame, within 100ms, by second, uplink distance measuring in week
Value (scope for [0~1000ms), notes including 0s, not including 1s) and star time synchronized the other information such as instruct by bus
It is sent to satellite time generation and keeps load；
(3) satellite time generation receives the data that the uplink receiver in bus is sent with the CPU of load is kept, if its
In contain time synchronized instruction, perform following steps operation：
(3.1) extracted from the 0th frame of DUP2 yards of uplink data sending frame in week the second (SOW), and calculate SOW%30,
SOW%18, SOW%6, SOW%3 are sent to time management FPGA；
(3.2) according to uplink distance measuring value (PR) and star ground time delay preset value (RR), aeronautical satellite time (1PPS) tune is calculated
Whole value Δ POS：
Δ t=PR-RR, wherein PR ∈ [0,1000ms), RR=82ms, Δ t ∈ [- 82ms, 918ms)；
(3.3) the timeticks quantity that Δ t is converted to FPGA is sent to time management FPGA as adjustment amount, and Δ t turns
The method for being changed to the timeticks quantity of FPGA is：
Δ POS=Δs t × fFPGA, wherein fFPGARepresent the clock frequency that time management is used
The Δ POS for now obtaining contains sign, and is that 1PPS is opened on star in view of the measuring method of uplink distance measuring value PR
Door, the 1PPS of the up ground elapsed time for recovering close the door, therefore the implication of the sign of Δ POS is as follows：
Δ POS positive signs represent satellite time advanced ground elapsed time, it is necessary to satellite time is carried out into hysteretic operation；
Δ POS positive signs represent satellite time advanced ground elapsed time, it is necessary to satellite time is carried out into hysteretic operation；
(3.4) adjustment amount is sent to time management FPGA；
(3.5) after CPU is calculated and finished, the instruction for starting star ground time synchronized is sent to time management FPGA at once, CPU's
There is no other command operatings between two instructions, the transmission time should be at the 200ms~500ms during Big Dipper of ground；
(4) if FPGA is not received by time synchronized instruction, each clock cycle, following operation is performed：
(4.1) 1PPS phase registers (POS_reg) cumulative 1；
(4.2) when 1PPS phase registers tired (POS_reg) fill it up with 1 whole second (fFPGA) when, POS_reg resets, SOW_reg
Cumulative 1,30s accumulator registers, 18s accumulator registers, 6s accumulator registers, 3s accumulator registers cumulative 1；
(4.3) after SOW_reg fills it up with 1 complete cycle (604799), SOW_reg resets；The cumulative deposit of 30s accumulator registers, 18s
After device, 6s accumulator registers, 3s accumulator registers fill it up with 18s, 6s, 3s, reset respectively；
(4.4) reset after the full 30s of 30s accumulator registers；
(4.5) reset after the full 18s of 18s accumulator registers；
(4.6) reset after the full 6s of 6s accumulator registers；
(4.7) reset after the full 3s of 3s accumulator registers；
(5) if FPGA receives time synchronized instruction, following operation is performed：
(5.1) FPGA receives the SOW that CPU is inserted；
(5.2) FPGA receives SOW%30, SOW%18, SOW%6, SOW%3 that CPU is inserted；
(5.3) FPGA receives the Δ POS that CPU is inserted；
(5.4) FPGA receives the startup time synchronized instruction that CPU is inserted；
(5.5) FPGA1 is operated below execution in 1 time management clock cycle：
Second register in adjustment week：Using sequence circuit, by CPU write enter the SOW of FPGA1, SOW%30, SOW%18,
The new value of SOW%6, SOW%3 is inserted in the register of SOW, SOW%30, SOW%18, SOW%6, SOW%3；
Adjustment 1PPS phase registers：Using sequence circuit, within a clock cycle, POS is judgedold+ Δ POS+1's
Value (notes：Time synchronized operation needs 1 clock cycle in itself, so needing "+1 ")
If less than 0 (i.e.：The value of POSold+ Δs POS+1 is negative), by POSold+ Δs POS+1+fFPGAAs new
POS is inserted in POS registers (POS_reg)；The cumulative deposit of SOW registers, 30s accumulator registers, 18s accumulator registers, 6s
Device, 3s accumulator registers need to carry out it is extra borrow operation, that is, the operation that subtracts；
If greater than equal to 1 second (POSoldThe value of+Δ POS+1 is more than or equal to fFPGA), by POSold+ΔPOS+1-fFPGAMake
For new POS is inserted in POS registers (POS_reg)；SOW registers, 30s accumulator registers, 18s accumulator registers, 6s tire out
Plus register, 3s accumulator registers need to carry out extra carry operation, i.e., Jia 1 and operate；
If greater than equal to 0, less than or equal to 1 second, by POSold+ Δ POS+1 inserts POS registers as new POS
(POS_reg) in；SOW registers, 30s accumulator registers, 18s accumulator registers, 6s accumulator registers, 3s accumulator registers are not
Extra plus/minus 1 is carried out to operate.
The adjustment process analysis procedure analysis of a variety of satellites and ground phase difference situation is illustrated in figure 4, is navigated for adjustment
For the 1PPS phases of satellite, different phase relations determines different processing methods before and after adjustment.Following table (table 2) gives
1PPS phase relations are possible to situation before and after star ground time synchronized, and each situation is analyzed, and provide each feelings
The processing method of condition.
The various phase modulation value analyses of table 2
As can be seen that the doubleclocking of the satellite navigation time used suitable for aeronautical satellite payload that the present invention is provided
The synchronization adjustment method during high-precision real of domain, it is adaptable to the situation of a variety of satellites and ground relative time.
The content not being described in detail in description of the invention belongs to the known technology of those skilled in the art.
Claims (3)
1. synchronization adjustment method during a kind of aeronautical satellite time dual clock domain high-precision real, it is characterised in that comprise the following steps：
(1) control Satellite Payloads receive the uplink data frames that ground sends using uplink receiver；Described upstream data
Frame include star ground time synchronized instruction, week in second SOW or uplink distance measuring value PR, wherein, star ground time synchronized instruction for control into
The instruction of row aeronautical satellite time dual clock domain real-time synchronization adjustment；Described uplink distance measuring value PR is Present navigation satellite time
With the time difference of time in uplink data frames；
(2) uplink data frames parse with obtaining star time synchronized instruction, second SOW or uplink distance measuring value PR in week, and is sent
Generated to satellite time and keep load；
(3) satellite time generation is judged with load is kept, if with receiving star time synchronized instruction, is transferred to step
(4), otherwise it is transferred to step (6)；
(4) second SOW in week is delivered to the time management FPGA of satellite, according to uplink distance measuring value PR, star ground time delay preset value RR, meter
Calculating aeronautical satellite time pps pulse per second signal 1PPS adjusted value Δ POS is
Δ POS=round { Δ t*fFPGA}
Wherein, round { } is rounding operation, and the unit of Δ t=PR-RR, Δ t is s, fFPGAWork needed for the adjustment of expression time
Clock frequency, Δ POS represents aeronautical satellite time lead ground elapsed time for positive, and Δ POS is negative indication aeronautical satellite time-lag
Ground elapsed time；
Aeronautical satellite time pps pulse per second signal 1PPS adjusted value Δ POS, the time synchronized instruction of star ground are sent to time management
Two different clock-domains of FPGA；
(5) following time adjustment operation is carried out respectively in each clock zone：Control time manages FPGA within 1 clock cycle
By in second SOW register in the week of second SOW write-in aeronautical satellite times in week, POS is calculatedold+ Δ POS+1, if POSold+Δ
POS+1 is less than 0, then calculate POSold+ΔPOS+1+fFPGAThe phase register of aeronautical satellite time is inserted as new POS
POS_reg, then carries out subtracting one operation by phase register POS_reg；If POSold+ Δ POS+1 is more than or equal to fFPGA, then
By POSold+ΔPOS+1-fFPGAThe phase register POS_reg of aeronautical satellite time is inserted as new POS, then by phase
Register POS_reg adds 1 operation, if POSold+ Δ POS+1 is more than or equal to 0 and less than fFPGA, then by POSold+ Δ POS+1 makees
The phase register POS_reg of aeronautical satellite time is inserted for new POS；Wherein, POS is the aeronautical satellite time to 1s complementations
As a result；POSoldIt is corresponding POS before the adjustment of aeronautical satellite time；
(6) in the operating clock cycle needed for the adjustment of each time, control aeronautical satellite time pps pulse per second signal 1PPS phase is posted
Storage POS_reg cumulative 1, by the register of second SOW in week cumulative 1；Wherein, when phase register POS_reg is equal to fFPGAWhen,
Phase register POS_reg is reset, it is when the register of second SOW in week is equal to 604799, the register of second SOW in week is clear
Zero；
(7) the aeronautical satellite time pair is updated using the POS in the phase register POS_reg of aeronautical satellite time pps pulse per second signal
Periodicity WN, the number of seconds SOW in the week in week in second SOW register for answering, and then complete aeronautical satellite time synchronized.
2. synchronization adjustment method during a kind of aeronautical satellite time dual clock domain high-precision real according to claim 1, it is special
Levy and be：Described fFPGAComputational methods comprise the following steps：
(1) working clock frequency needed for obtaining two clock zone time adjustment；
(2) greatest common divisor of the working clock frequency needed for being calculated two clock zone time adjustment, and adjusted as the time
Working clock frequency f needed for wholeFPGA。
3. synchronization adjustment method during a kind of aeronautical satellite time dual clock domain high-precision real according to claim 1 and 2, its
It is characterised by：Described PR ∈ [0,1000ms), RR=82ms.
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