CN106817139A - Radio frequency sending set - Google Patents
Radio frequency sending set Download PDFInfo
- Publication number
- CN106817139A CN106817139A CN201510845959.XA CN201510845959A CN106817139A CN 106817139 A CN106817139 A CN 106817139A CN 201510845959 A CN201510845959 A CN 201510845959A CN 106817139 A CN106817139 A CN 106817139A
- Authority
- CN
- China
- Prior art keywords
- input end
- signal input
- mos tube
- grid
- mixer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 11
- 230000003321 amplification Effects 0.000 claims abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 4
- 230000010355 oscillation Effects 0.000 claims description 18
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/12—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transmitters (AREA)
Abstract
The present invention provides a kind of radio frequency sending set.The radio frequency sending set includes：Digital analog converter, wave filter, upper frequency mixer, phaselocked loop and power amplification circuit；Wherein, the output end of digital analog converter is connected with the input of wave filter, and the output end of wave filter, the output end of phaselocked loop are connected with the input of upper frequency mixer respectively, and the output end of upper frequency mixer is connected with the input of power amplification circuit；Controlling switch is provided with digital analog converter, wave filter, phaselocked loop and upper frequency mixer；Wherein, when all of controlling switch receives "off" instruction, radio frequency sending set is enhancing data-rate transmission mode emitter, and when all of controlling switch receives " closed " instruction, radio frequency sending set is super low-power consumption mode transmitter.The radio frequency sending set that the present invention is provided, the switching of both of which is carried out by controlling switch, and the same section in circuit structure part can be multiplexed, and enormously simplify circuit structure, reduces circuit footprint, reduces cost.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a radio frequency transmitter.
Background
In the dual-mode bluetooth 4.0, there are two modes (enhanced data rate transmission mode and ultra-low power consumption mode) of radio frequency transmitter, the enhanced data rate transmission mode radio frequency transmitter is formed by digital-to-analog converter, filter, mixer and power amplifier on the I/Q, phase-locked loop, etc., the ultra-low power consumption mode radio frequency transmitter is formed by phase-locked loop, buffer, preamplifier and power amplifier, etc., in the prior art, when the system is set up, the transmitters of the two modes are independently designed on the circuit structure, the mode is switched by the user's choice through the software setting switch, the circuit structure is complex, and the cost is high.
Disclosure of Invention
The invention provides a radio frequency transmitter, which can realize that the radio frequency transmitter in an enhanced data rate transmission mode and an ultra-low power consumption mode is of an integrated structure on a circuit structure, and a hardware control switch is used for switching the two modes, so that related circuits can be multiplexed, the complexity of the circuit structure is reduced, and the cost is saved.
The invention provides a radio frequency transmitter, comprising: the digital-to-analog converter, the filter, the upper mixer, the phase-locked loop and the power amplifying circuit; wherein,
the output end of the digital-to-analog converter is connected with the input end of the filter, the output end of the filter and the output end of the phase-locked loop are respectively connected with the input end of the upper frequency mixer, and the output end of the upper frequency mixer is connected with the input end of the power amplifying circuit;
the digital-to-analog converter, the filter, the phase-locked loop and the upper frequency mixer are all provided with control switches;
when all the control switches receive an 'off' command, the radio frequency transmitter is an enhanced data rate transmission mode transmitter, and when all the control switches receive an 'on' command, the radio frequency transmitter is an ultra-low power consumption mode transmitter.
Furthermore, a control switch is arranged in each of the digital-to-analog converter and the filter, two control switches are arranged in the phase-locked loop, and a plurality of control switches are arranged in the upper frequency mixer;
when all control switches in the upper mixer receive an 'open' instruction, the upper mixer is a quadrature mixer, and when all control switches in the upper mixer receive a 'close' instruction, the upper mixer is a buffer.
Further, the up-mixer includes:
the load circuit comprises a first Gilbert circuit unit, a second Gilbert circuit unit and a load circuit which are connected in parallel;
the first Gilbert circuit unit comprises a first positive baseband signal input end, a first negative baseband signal input end, a first local oscillation signal input end, a second local oscillation signal input end, a first MOS (metal oxide semiconductor) tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube;
the first positive baseband signal input end is connected with a grid of the first MOS tube and a grid of the fourth MOS tube, the grid of the first MOS tube is connected with one end of a first control switch, the grid of the fourth MOS tube is connected with one end of a second control switch, the first negative baseband signal input end is connected with a grid of the second MOS tube and a grid of the third MOS tube, the grids of the second MOS tube and the third MOS tube are both connected with one end of a third control switch, the first local oscillation signal input end is connected with a grid of the fifth MOS tube, and the second local oscillation signal input end is connected with a grid of the sixth MOS tube;
the second gilbert circuit unit comprises a second positive baseband signal input end, a second negative baseband signal input end, a third local oscillation signal input end, a fourth local oscillation signal input end, a seventh MOS (metal oxide semiconductor) transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor and a twelfth MOS transistor;
the second positive baseband signal input end is connected with a grid of the seventh MOS transistor and a grid of the tenth MOS transistor, the grid of the seventh MOS transistor is connected with one end of a fourth control switch, the grid of the tenth MOS transistor is connected with one end of a fifth control switch, the second negative baseband signal input end is connected with a grid of the eighth MOS transistor and a grid of the ninth MOS transistor, the grids of the eighth MOS transistor and the ninth MOS transistor are both connected to one end of a sixth control switch, the third local oscillation signal input end is connected with a grid of the eleventh MOS transistor, and the fourth local oscillation signal input end is connected with a grid of the twelfth MOS transistor;
the other ends of the first control switch and the second control switch are connected to a power supply, and the other ends of the third control switch, the fourth control switch, the fifth control switch and the sixth control switch are all grounded.
Further, the first control switch and the second control switch in the up-mixer are multiplexed, and the third control switch, the fourth control switch, the fifth control switch and the sixth control switch are multiplexed.
Further, the first gilbert circuit unit further includes: a thirteenth MOS tube used as a current source, wherein the drain electrode of the thirteenth MOS tube is connected with the source electrode of the fifth MOS tube and the source electrode of the sixth MOS tube;
the second gilbert circuit cell further comprises: and the drain electrode of the fourteenth MOS tube is connected with the source electrode of the eleventh MOS tube and the source electrode of the twelfth MOS tube.
Further, all control switches provided in the digital-to-analog converter, the filter, the phase-locked loop, and the up-mixer are controlled by the same "open" command or "close" command.
Furthermore, the power amplifier also comprises a matching network and an antenna, and the output end of the power amplifying circuit is connected with the matching network.
The radio frequency transmitter provided by the invention can fuse the circuit structures of the transmitter in the enhanced data rate transmission mode and the low power consumption mode, the two modes are switched by the hardware control switch, the same parts in the circuit structure components can be multiplexed, for example, the mixer, the phase-locked loop, the power amplification circuit and the antenna can be multiplexed, the circuit structure is greatly simplified, the occupied area of the circuit is reduced, and the cost is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a first embodiment of a radio frequency transmitter according to the present invention;
fig. 2 is a schematic diagram of an up-mixer in a first embodiment of an rf transmitter according to the present invention;
FIG. 3 is a schematic diagram of the structure of the upper mixer with all switches open;
FIG. 4 is a schematic diagram of the structure of the up-mixer with all switches closed;
fig. 5 is a schematic structural diagram of a second embodiment of an rf transmitter according to the present invention;
fig. 6 is a schematic structural diagram of the rf transmitter according to the present invention with all the control switches closed.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a first embodiment of the rf transmitter of the present invention, and as shown in fig. 1, the rf transmitter of this embodiment may include: the digital-to-analog converter comprises a digital-to-analog converter 11, a filter 12, an upper mixer 13, a phase-locked loop 15 and a power amplifying circuit 14, wherein the output end of the digital-to-analog converter 11 is connected with the input end of the filter 12, the output end of the filter 12 and the output end of the phase-locked loop 15 are respectively connected with the input end of the upper mixer 13, and the output end of the upper mixer 13 is connected with the input end of the power amplifying circuit 14. The digital-to-analog converter 11, the filter 12, the phase locked loop 15 and the up-mixer 13 are all provided with control switches. When all the control switches receive an 'off' command, the radio frequency transmitter is an enhanced data rate transmission mode transmitter, and when all the control switches receive an 'on' command, the radio frequency transmitter is an ultra-low power consumption mode transmitter.
Specifically, a control switch is disposed in each of the digital-to-analog converter 11 and the filter 12, and is used for controlling whether the digital-to-analog converter 11 and the filter 12 work normally. Two control switches are arranged in the phase-locked loop 15 and used for controlling whether two branches connected with the upper frequency mixer of the phase-locked loop work normally or not, and a plurality of control switches are arranged in the upper frequency mixer 13. When all the control switches in the up-mixer 13 receive the "off" command, the up-mixer 13 is a quadrature mixer, and when all the control switches in the up-mixer 13 receive the "on" command, the up-mixer 13 is a buffer.
All the control switches provided in the digital-to-analog converter 11, the filter 12, the phase-locked loop 15 and the up-mixer 13 may be controlled by the same "open" command or "close" command, and may be configured by software.
Fig. 2 is a schematic structural diagram of an upper mixer in a first embodiment of the rf transmitter of the present invention, and as shown in fig. 2, the upper mixer 13 includes: a first gilbert circuit cell 101a and a second gilbert circuit cell connected in parallel, and a load circuit 101 b. The first gilbert circuit unit 101a includes a first positive baseband signal input terminal (BB _ IP), a first negative baseband signal input terminal (BB _ IN), a first local oscillator signal input terminal (LO _ IP), a second local oscillator signal input terminal (LO _ IN), a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6. The first positive baseband signal input end (BB _ IP) is connected to the gate of the first MOS transistor M1 and the gate of the fourth MOS transistor M4, the gate of the first MOS transistor M1 is connected to one end of the first control switch SW1, the gate of the fourth MOS transistor M4 is connected to one end of the second control switch (SW2), the first negative baseband signal input end (BB _ IN) is connected to the gate of the second MOS transistor M2 and the gate of the third MOS transistor M3, the gates of the second MOS transistor M2 and the third MOS transistor M3 are connected to the third control switch SW3, the first local oscillation signal input end (LO _ IP) is connected to the gate of the fifth MOS transistor M5, the second local oscillation signal input end (LO _ IN) is connected to the gate of the sixth MOS transistor M6, and the other ends of the first control switch 1 and the second control switch SW2 are connected to the power supply SW 4. RF _ P, RF _ N in fig. 2 are all output terminals.
The second gilbert circuit unit 101b includes a second positive baseband signal input terminal (BB _ QP), a second negative baseband signal input terminal (BB _ QN), a third local oscillator signal input terminal (LO _ QP), a fourth local oscillator signal input terminal (LO _ QN), a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, and a twelfth MOS transistor M12.
The second positive baseband signal input end (BB _ QP) is connected to the gate of the seventh MOS transistor M7 and the gate of the tenth MOS transistor M10, the gate of the seventh MOS transistor M7 is connected to one end of the fourth control switch SW4, the gate of the tenth MOS transistor M10 is connected to one end of the fifth control switch SW5, the second negative baseband signal input end (BB _ QN) is connected to the gate of the eighth MOS transistor M8 and the gate of the ninth MOS transistor M9, the gates of the eighth MOS transistor M8 and the ninth MOS transistor M9 are connected to one end of the sixth control switch SW6, the third local oscillator signal input end (LO _ QP) is connected to the gate of the eleventh MOS transistor M11, the fourth local oscillator signal input end (LO _ QN) is connected to the gate of the twelfth MOS transistor M12, and the third control switch SW3, the fourth control switch SW4, the fifth control switch SW5 and the other end of the sixth control switch SW6 are grounded.
Preferably, the first control switch SW1 and the second control switch SW2 in the up-mixer are multiplexed, and the third control switch SW3, the fourth control switch SW4, the fifth control switch SW5 and the sixth control switch SW6 are multiplexed.
Further, the first gilbert circuit unit 101a further includes: and the drain electrode of the thirteenth MOS tube M13 is used as a current source, and the drain electrode of the thirteenth MOS tube M13 is connected with the source electrode of the fifth MOS tube M5 and the source electrode of the sixth MOS tube M6. The second gilbert circuit unit 101b further includes: and the drain electrode of the fourteenth MOS tube M14 is used as a current source, and the drain electrode of the fourteenth MOS tube M14 is connected with the source electrode of the eleventh MOS tube M11 and the source electrode of the twelfth MOS tube M12.
When all the switches SW1-SW6 in the up-mixer 13 are "off", the up-mixer 13 is a quadrature mixer, as shown in fig. 3, and fig. 3 is a schematic diagram of the structure when all the switches in the up-mixer are off.
When all switches SW1-SW6 in the up-mixer 13 are "closed", the up-mixer 13 is a BUFFER (BUFFER), fig. 4 is a schematic diagram of the structure when all switches in the up-mixer are closed, and as shown in fig. 4, the circuits in the dotted line are not operated.
Fig. 5 is a schematic structural diagram of a second embodiment of the radio frequency transmitter of the present invention, and as shown in fig. 5, the radio frequency transmitter of this embodiment is added with a matching network 18 on the basis of fig. 1. When all the control switches receive the "off" command, the up-mixer 13 is a standard I/Q quadrature mixer, which mixes the signal to be transmitted (BB) with the local oscillator signal (LO) to generate a Radio Frequency (RF) signal, which is sent to the power amplifier 17, and the RF transmitter is an enhanced data rate transmission mode transmitter. The working process of the enhanced data rate transmission mode transmitter is as follows: the upper mixer 13 is a common mixer structure, and data to be transmitted is sent to the digital-to-analog converter 11, is sent to the upper mixer 13 after passing through the filter 12, and is transmitted out by an antenna through the power amplifier 17 and the matching network 18.
Fig. 6 is a schematic structural diagram of the radio frequency transmitter according to the present invention when all the control switches are turned off, and at this time, all the control switches receive the "on" command, the upper mixer 13 is a buffer, and the digital-to-analog converter 11 and the filter 12 are turned off and do not operate, and at this time, the radio frequency transmitter is an ultra-low power consumption mode transmitter. The working process of the ultra-low power consumption mode transmitter is as follows: data to be transmitted is fed to the buffer 20 through the phase locked loop 15 and then transmitted through the power amplifier 17 and the matching network 18.
Furthermore, the data to be transmitted is transmitted through the antenna when being transmitted by the radio frequency transmitter.
The radio frequency transmitter provided by the embodiment can fuse the circuit structures of the transmitter in the enhanced data rate transmission mode and the ultra-low power consumption mode, the two modes are switched by the control switch, the same parts in the circuit structure components can be multiplexed, and the mixer, the phase-locked loop, the power amplifier, the matching network and the antenna can be multiplexed, so that the circuit structure is greatly simplified, the occupied area of the circuit is reduced, and the cost is reduced.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Meanwhile, all the above embodiments are a part of the embodiments of the present invention, not all of them. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Claims (7)
1. A radio frequency transmitter, comprising: the digital-to-analog converter, the filter, the upper mixer, the phase-locked loop and the power amplifying circuit; wherein,
the output end of the digital-to-analog converter is connected with the input end of the filter, the output end of the filter and the output end of the phase-locked loop are respectively connected with the input end of the upper frequency mixer, and the output end of the upper frequency mixer is connected with the input end of the power amplifying circuit;
the digital-to-analog converter, the filter, the phase-locked loop and the upper frequency mixer are all provided with control switches;
when all the control switches receive an 'off' command, the radio frequency transmitter is an enhanced data rate transmission mode transmitter, and when all the control switches receive an 'on' command, the radio frequency transmitter is an ultra-low power consumption mode transmitter.
2. The radio frequency transmitter of claim 1, wherein a control switch is provided in each of the digital-to-analog converter and the filter, two control switches are provided in the phase-locked loop, and a plurality of control switches are provided in the up-mixer;
when all control switches in the upper mixer receive an 'open' instruction, the upper mixer is a quadrature mixer, and when all control switches in the upper mixer receive a 'close' instruction, the upper mixer is a buffer.
3. The radio frequency transmitter of claim 2, wherein the up-mixer comprises:
the load circuit comprises a first Gilbert circuit unit, a second Gilbert circuit unit and a load circuit which are connected in parallel;
the first Gilbert circuit unit comprises a first positive baseband signal input end, a first negative baseband signal input end, a first local oscillation signal input end, a second local oscillation signal input end, a first MOS (metal oxide semiconductor) tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube;
the first positive baseband signal input end is connected with a grid of the first MOS tube and a grid of the fourth MOS tube, the grid of the first MOS tube is connected with one end of a first control switch, the grid of the fourth MOS tube is connected with one end of a second control switch, the first negative baseband signal input end is connected with a grid of the second MOS tube and a grid of the third MOS tube, the grids of the second MOS tube and the third MOS tube are both connected with one end of a third control switch, the first local oscillation signal input end is connected with a grid of the fifth MOS tube, and the second local oscillation signal input end is connected with a grid of the sixth MOS tube;
the second gilbert circuit unit comprises a second positive baseband signal input end, a second negative baseband signal input end, a third local oscillation signal input end, a fourth local oscillation signal input end, a seventh MOS (metal oxide semiconductor) transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor and a twelfth MOS transistor;
the second positive baseband signal input end is connected with a grid of the seventh MOS transistor and a grid of the tenth MOS transistor, the grid of the seventh MOS transistor is connected with one end of a fourth control switch, the grid of the tenth MOS transistor is connected with one end of a fifth control switch, the second negative baseband signal input end is connected with a grid of the eighth MOS transistor and a grid of the ninth MOS transistor, the grids of the eighth MOS transistor and the ninth MOS transistor are both connected to one end of a sixth control switch, the third local oscillation signal input end is connected with a grid of the eleventh MOS transistor, and the fourth local oscillation signal input end is connected with a grid of the twelfth MOS transistor;
the other ends of the first control switch and the second control switch are connected to a power supply, and the other ends of the third control switch, the fourth control switch, the fifth control switch and the sixth control switch are all grounded.
4. The radio frequency transmitter of claim 3, wherein the first and second control switches in the up-mixer are multiplexed, and wherein the third, fourth, fifth, and sixth control switches are multiplexed.
5. The radio frequency transmitter of claim 4, wherein the first Gilbert circuit element further comprises: a thirteenth MOS tube used as a current source, wherein the drain electrode of the thirteenth MOS tube is connected with the source electrode of the fifth MOS tube and the source electrode of the sixth MOS tube;
the second gilbert circuit cell further comprises: and the drain electrode of the fourteenth MOS tube is connected with the source electrode of the eleventh MOS tube and the source electrode of the twelfth MOS tube.
6. The radio frequency transmitter of any of claims 1-5, wherein all control switches provided in the digital-to-analog converter, the filter, the phase-locked loop, and the up-mixer are controlled by a same "open" command or "close" command.
7. The radio frequency transmitter of claim 6, further comprising a matching network and an antenna, wherein an output of the power amplification circuit is coupled to the matching network.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510845959.XA CN106817139B (en) | 2015-11-27 | 2015-11-27 | Radio frequency sending set |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510845959.XA CN106817139B (en) | 2015-11-27 | 2015-11-27 | Radio frequency sending set |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106817139A true CN106817139A (en) | 2017-06-09 |
| CN106817139B CN106817139B (en) | 2019-05-03 |
Family
ID=59102762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510845959.XA Active CN106817139B (en) | 2015-11-27 | 2015-11-27 | Radio frequency sending set |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106817139B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110324077A (en) * | 2019-07-05 | 2019-10-11 | 上海航天测控通信研究所 | A kind of spaceborne dual-mode transmitter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522955A (en) * | 2011-12-31 | 2012-06-27 | 东南大学 | Mixer |
| CN104718707A (en) * | 2012-10-08 | 2015-06-17 | 高通股份有限公司 | Transmit diversity architecture with optimized power consumption and area for UMTS and LTE systems |
-
2015
- 2015-11-27 CN CN201510845959.XA patent/CN106817139B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522955A (en) * | 2011-12-31 | 2012-06-27 | 东南大学 | Mixer |
| CN104718707A (en) * | 2012-10-08 | 2015-06-17 | 高通股份有限公司 | Transmit diversity architecture with optimized power consumption and area for UMTS and LTE systems |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110324077A (en) * | 2019-07-05 | 2019-10-11 | 上海航天测控通信研究所 | A kind of spaceborne dual-mode transmitter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106817139B (en) | 2019-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11418149B2 (en) | Re-configurable passive mixer for wireless receivers | |
| CN101399520B (en) | Mixer having high linearity and programmable gain and related transconductor | |
| CN101212441B (en) | Method and system for processing signal in communication system | |
| US8019310B2 (en) | Local oscillator buffer and mixer having adjustable size | |
| EP1798850B1 (en) | Bidirectional frequency converter and radio equipment using same | |
| US8963612B1 (en) | Multiple mode RF circuit | |
| US10257015B2 (en) | Polar transmitter with tunable matching network | |
| EP1696581A1 (en) | Frequency dividing circuit and multimode radio device using same | |
| US8963610B2 (en) | Adaptable mixer and local oscillator devices and methods | |
| US20120142283A1 (en) | Wireless communication apparatus | |
| CN104767491A (en) | Amplifier | |
| US10312861B2 (en) | Apparatus for and method of programmable matching network for multiple signal types | |
| CN203632619U (en) | High linearity mixer capable of switching gains | |
| CN106817139B (en) | Radio frequency sending set | |
| US9059662B1 (en) | Active combiner | |
| CN106464212B (en) | The device and method of common mode and differential loop Bandwidth adjustment for decoupling circuit | |
| US7816954B2 (en) | Circuit configuration of a frequency divider | |
| US9209750B2 (en) | Harmonic rejection mixer | |
| US7285993B2 (en) | Method and system for a divide by N circuit with dummy load for multiband radios | |
| Serhan et al. | Broadband SOI PA with tunable matching network for improved LTE performances under high VSWR | |
| CN111181493B (en) | Millimeter wave dual-band dual-mode mixer | |
| US20230412158A1 (en) | Method and device for outputting frequency multiplication signal having high harmonic suppression, and storage medium | |
| JP5044674B2 (en) | Frequency converter and transmitter using the same | |
| JP5621060B1 (en) | Demodulator and modulator | |
| KR20230041603A (en) | Multi-core oscillator with enhanced mode robustness |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190827 Address after: 200235 Shanghai city Xuhui District Longcao Road No. 299 Tianhua Information Technology Park Building 2 floor A block 5 Co-patentee after: Qingdao Eastsoft Communication Technology Co., Ltd. Patentee after: SHANGHAI EASTSOFT MICROELECTRONICS CO., LTD. Address before: 200235 Shanghai city Xuhui District Longcao Road No. 299 Tianhua Information Technology Park Building 2 floor A block 5 Patentee before: SHANGHAI EASTSOFT MICROELECTRONICS CO., LTD. |