CN106816416A - Embedded hybrid package structure of semiconductor and preparation method thereof - Google Patents
Embedded hybrid package structure of semiconductor and preparation method thereof Download PDFInfo
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- CN106816416A CN106816416A CN201510845904.9A CN201510845904A CN106816416A CN 106816416 A CN106816416 A CN 106816416A CN 201510845904 A CN201510845904 A CN 201510845904A CN 106816416 A CN106816416 A CN 106816416A
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- wiring board
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- ship
- semiconductor chip
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 373
- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 82
- 229910000679 solder Inorganic materials 0.000 claims description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 24
- 239000010949 copper Substances 0.000 claims description 24
- 238000012856 packing Methods 0.000 claims description 20
- 239000002313 adhesive film Substances 0.000 claims description 19
- 239000003989 dielectric material Substances 0.000 claims description 16
- 238000005538 encapsulation Methods 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 238000004806 packaging method and process Methods 0.000 claims description 11
- 239000004642 Polyimide Substances 0.000 claims description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 26
- 238000005516 engineering process Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 21
- 241000208340 Araliaceae Species 0.000 description 18
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 18
- 235000003140 Panax quinquefolius Nutrition 0.000 description 18
- 235000008434 ginseng Nutrition 0.000 description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 6
- 239000004033 plastic Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000002386 leaching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000003032 molecular docking Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses embedded hybrid package structure of a kind of semiconductor and preparation method thereof, the encapsulating structure includes：Wiring board, it has the first surface and second surface being oppositely arranged；Opening or cavity in wiring board, that be at least used to accommodating semiconductor chip (Bare Die) and capsulation body of semiconductor ship (Semiconductor Package)；It is arranged at the semiconductor chip in opening or cavity；It is arranged at the capsulation body of semiconductor ship in opening or cavity；Encapsulating material, is at least used to cover the space not occupied by semiconductor chip and capsulation body of semiconductor ship in the first surface of wiring board and filling opening or cavity；Layer is rerouted, at least for being electrically connected semiconductor chip, capsulation body of semiconductor ship and wiring board.Embedded hybrid package structure of semiconductor in the present invention and preparation method thereof uses wiring board embedded technology scheme, can simplify the integrated process flow of semiconductor chip and capsulation body of semiconductor ship, improves integrated quality and performance, effectively reduces integrated area.
Description
Technical field
The present invention relates to a kind of line carrier plate encapsulating structure, more particularly to a kind of embedded hybrid package structure of semiconductor and preparation method thereof.
Background technology
In the prior art, the encapsulation of semiconductor chip and the assembling of capsulation body of semiconductor ship encapsulates completion respectively by Electronic Packaging factory and Electronic Assemblies factory respectively, and the encapsulation of semiconductor chip is completed first, then carries out the assembling of capsulation body of semiconductor ship in the circuit board again.Capsulation body of semiconductor ship assembling in the circuit board is generally completed using by surface mount process.
Surface mounting technology (Surface Mount Technology, SMT it is) that one kind will be without pin or short leg surface-assembled component (abbreviation SMC/SMD, Chinese claims sheet component) it is arranged on printed wiring board (Printed Circuit Board, PCB on surface) or the surface of other substrates, the circuit load technology of welding assembly is subject to by methods such as Reflow Soldering or immersed solder.The packing density of surface mounting technology is high, electronic product small volume, lightweight, and the volume and weight of surface mount elements only has 1/10 or so of traditional inserting element, general using after SMT, electronic product volume-diminished 40%~60%, weight saving 60%~80%.Generally using being completed by surface mount engineering, in surface mount, generally connected by scolding tin carries out electric interconnection by semiconductor packing device and wiring board for semiconductor packing device assembling in the circuit board.
But the encapsulation between semiconductor chip and capsulation body of semiconductor ship and wiring board has following deficiency in the prior art：
Semiconductor chip/between capsulation body of semiconductor ship and wiring board docks standard and complex process, cumbersome；
Usual semiconductor chip is needed after encapsulation link turns into semiconductor package body device, is just mounted/welded on a printed circuit.In addition in surface mount, generally connected by scolding tin carries out electric interconnection by capsulation body of semiconductor ship and wiring board, surface-pasted scolding tin connection at present needs the pad and pad spacing (pitch) of semiconductor packing device larger, such as pad/pad spacing=280 micron/400 micron, precision has much room for improvement, and scolding tin connection needs to carry out complex solder reflow technology controlling and process；
In addition, capsulation body of semiconductor ship is assembled using surface-pasted mode in the circuit board, because capsulation body of semiconductor ship area is increased, the larger surface area of wiring board will be occupied, hinder the miniaturization of semiconductor packing device assembling.
Therefore a kind of embedded hybrid package structure of new semiconductor of offer and preparation method thereof is needed badly to solve the above problems.
The content of the invention
The technical problems to be solved by the invention are to provide embedded hybrid package structure of a kind of semiconductor and preparation method thereof, can be effectively improved capsulation body of semiconductor ship pad and pad spacing is larger and the problem of encapsulating structure miniaturization.
In order to solve the above technical problems, the embedded hybrid package structure of a kind of semiconductor provided among one aspect of the present invention, it is characterised in that the encapsulating structure includes：
Wiring board, it has the first surface and second surface being oppositely arranged；
Opening or cavity in the wiring board, that be at least used to accommodating semiconductor chip and capsulation body of semiconductor ship；
It is arranged at the semiconductor chip in the opening or cavity；
It is arranged at the capsulation body of semiconductor ship in the opening or cavity；
Encapsulating material, is at least used to cover the first surface of wiring board and fills the space not occupied by semiconductor chip and capsulation body of semiconductor ship in the opening or cavity；
Layer is rerouted, at least for being electrically connected semiconductor chip, capsulation body of semiconductor ship and wiring board.
In a preferred embodiment, the first surface of the wiring board is provided with module contraposition mark, the highest face temperature and minimum surface of the surface of module contraposition mark and the second surface of the wiring board corresponding wiring board respectively.
In a preferred embodiment, passive electronic component is additionally provided with the opening or cavity, the passive electronic component includes the combination of any one or more in electric capacity, resistance, inductance element.
In a preferred embodiment, there is at least one semiconductor bare crystalline piece in capsulation body of semiconductor ship, and be the capsulation body of semiconductor ship with capsulation material encapsulation.
Further, the capsulation body of semiconductor ship comprising with the electrode of semiconductor bare crystalline piece in capsulation body of semiconductor ship/pad electrical connection, and the conductive lead wire that stretches out from the semiconductor bare crystalline piece or wiring.
Further, the capsulation body of semiconductor ship also includes the outer electrode being electrically connected with semiconductor bare crystalline piece, and the outer electrode is exposed aerial or by film covering；The material of the outer electrode is copper metal layer or the copper metal layer for having ni/au layers covering；The material of the film is accumulated layers dielectric material, including capsulation material or increasing layer material or polyimides.
Further, the encapsulating material is additionally operable to fill the space not occupied by passive electronic component in the opening or cavity.
In a preferred embodiment, the encapsulating structure also includes the first accumulated layers of the second surface, described encapsulating material, the semiconductor chip and the capsulation body of semiconductor ship that at least cover the wiring board；First accumulated layers are dielectric materials layer, including ABF increasing layers or photaesthesia dielectric layer.
Further, first accumulated layers are provided with blind hole above the line layer positioned at the electrode/pad, capsulation body of semiconductor ship outer electrode and wiring board of semiconductor chip；First accumulated layers are provided with the first rewiring layer, and the first rewiring layer in first accumulated layers is by the line layer electric interconnection on the electrode/pad of the blind hole and semiconductor chip, capsulation body of semiconductor ship outer electrode and/or wiring board.
Further, be additionally provided with encapsulating material on the wiring board first surface the second rewiring layer, it is described second reroute layer through conductive blind hole at least with wiring board on line layer, semiconductor chip, and/or capsulation body of semiconductor ship outer electrode electric interconnection.
Further, the second accumulated layers are coated with the first rewiring layer and/or the second rewiring layer, the triple wiring layers for rerouting layer and/or the second rewiring layer electric interconnection with first are formed with second accumulated layers, second accumulated layers include ABF increasing layers or photaesthesia dielectric layer.
Further, the encapsulating structure also includes at least solder mask of covering outermost line layer and the opening being arranged in the solder mask；Line layer in the mask open forms the pad of connection outer member.
Further, the encapsulating structure also includes the semiconductor packing device and/or passive electronic component above attachment solder mask, the passive electronic component includes the combination of any one or more in electric capacity, resistance, inductance element, and the semiconductor packing device and/or passive electronic component pass through the pad and triple wiring layer electric interconnections.
A kind of preparation method of the embedded hybrid package structure of semiconductor provided among another technical solution used in the present invention, the preparation method is comprised the following steps：
S1, offer wiring board, it has the first surface and second surface being oppositely arranged, and opening or the cavity for being at least used to accommodating semiconductor chip and capsulation body of semiconductor ship are provided with the wiring board；
S2, adhesive film is attached on the second surface of the wiring board, and the semiconductor chip and capsulation body of semiconductor ship are inserted into the opening or cavity, and the semiconductor chip and capsulation body of semiconductor ship is adhesively fixed with adhesive film；
S3, at least apply encapsulating material on the first surface and the opening or cavity of the wiring board, the packed material of first surface of the wiring board is covered, and is filled up completely with the opening or the packed material of cavity and the semiconductor chip and capsulation body of semiconductor ship；
S4, the removal adhesive film, and the wiring board is overturn；
S5, the wiring board second surface, semiconductor chip, capsulation body of semiconductor ship and with the wiring board second surface more than one layer accumulated layers of coplanar encapsulating material surface overlying lid；
S6, formed in the accumulated layers and to be at least used for the rewiring layer for being electrically connected semiconductor chip, capsulation body of semiconductor ship and wiring board.
The step S6 provided among another technical solution used in the present invention includes：
The first accumulated layers above the line layer positioned at the electrode/pad, capsulation body of semiconductor ship outer electrode and wiring board of semiconductor chip set blind hole, and form the first rewiring layer of the line layer electric interconnection on electrode/pad by the blind hole and semiconductor chip, capsulation body of semiconductor ship outer electrode, and/or wiring board；
Second is set on encapsulating material on assist side first surface and reroutes layer；Described second reroutes outer electrode electric interconnection of the layer through the line layer on conductive blind hole and wiring board, semiconductor chip, and/or capsulation body of semiconductor ship；
The second accumulated layers are formed on the first rewiring layer and/or the second rewiring layer, and conductive blind hole is set in the second accumulated layers, and form triple wiring layers that layer is rerouted through the rewiring layer of conductive blind hole electrical connection first and/or second.
Further, also include after the step S6：
Form solder mask on the outermost line layer of encapsulating structure, and be open on solder mask above line layer and formed respective pad；
Mounting semiconductor packaging and/or passive electronic component above solder mask, the semiconductor packing device and/or passive electronic component pass through the pad and triple wiring layer electric interconnections.
Compared with prior art, the present invention at least has the following advantages that：
By semiconductor chip and semiconductor package body, assist side completes encapsulation process simultaneously, eliminate both complicated and cumbersome standards in the prior art and technique docking, the circulation transfer of electronic manufacture is reduced, is used manpower and material resources sparingly, can further reduce the cost of electronic product；
The electrical connection of semiconductor chip and wiring board and capsulation body of semiconductor ship and wiring board uses succinct copper to reroute (RDL) scheme without scolding tin connection scheme, process stabilizing and reliability is high；
The assembling demand of more accurate semiconductor chip and capsulation body of semiconductor ship can be met, such as pad of semiconductor chip or capsulation body of semiconductor ship/pad spacing can narrow down to 150 microns/less than 200 microns；
The embedded assembling of semiconductor chip and capsulation body of semiconductor ship makes the surface area of wiring board fully be discharged, it is possible to achieve system assembles area significantly reduces, and reduction ratio can be more than 50%.
Brief description of the drawings
Fig. 1 is the structural representation of the embedded hybrid package structure of semiconductor in one embodiment of the present invention；
Fig. 1 a~1m is the process sequence diagram of the preparation method of the embedded hybrid package structure of semiconductor in one embodiment of the present invention, wherein：
Fig. 1 a are the structural representations of wiring board in one embodiment of the present invention；
Fig. 1 b are the scheme of installations of semiconductor chip and capsulation body of semiconductor ship in one embodiment of the present invention；
Fig. 1 c are the encapsulating structure schematic diagrames of capsulation body of semiconductor ship in one embodiment of the present invention；
Fig. 1 d are the encapsulating structure schematic diagrames after semiconductor chip and capsulation body of semiconductor ship are installed in one embodiment of the present invention；
Fig. 1 e are that one embodiment of the present invention includes the encapsulating structure schematic diagram of encapsulating material；
Fig. 1 f are the encapsulating structure schematic diagrames after one embodiment of the present invention includes the wiring board inversion of encapsulating material；
Fig. 1 g are that one embodiment of the present invention includes the encapsulating structure schematic diagram of the first accumulated layers；
Fig. 1 h are the encapsulating structure schematic diagrames of the blind hole in the first accumulated layers and encapsulating material in one embodiment of the present invention；
Fig. 1 i are that one embodiment of the present invention includes that the first rewiring layer and second reroutes the encapsulating structure schematic diagram of layer；
Fig. 1 j are that one embodiment of the present invention includes the encapsulating structure schematic diagram of the second accumulated layers；
Fig. 1 k are the encapsulating structure schematic diagrames that one embodiment of the present invention includes triple wiring layers；
Fig. 1 l are that one embodiment of the present invention includes the encapsulating structure schematic diagram of solder mask；
Fig. 1 m are to complete the surface-pasted structural representation of passive device after semiconductor chip and the embedded encapsulation of capsulation body of semiconductor ship in one embodiment of the present invention；
Fig. 2 is the structural representation of the embedded hybrid package structure of semiconductor in another preferred embodiment of the invention；
Fig. 2 a~2l is the process sequence diagram of the preparation method of the embedded hybrid package structure of semiconductor in another preferred embodiment of the invention, wherein：
Fig. 2 a are the structural representations of wiring board in another preferred embodiment of the invention；
Fig. 2 b are the scheme of installations of semiconductor chip, capsulation body of semiconductor ship and passive electronic component in another preferred embodiment of the invention；
Fig. 2 c are the encapsulating structure schematic diagrames after semiconductor chip in another preferred embodiment of the invention, capsulation body of semiconductor ship and passive electronic component are installed；
Fig. 2 d are that another preferred embodiment of the invention includes the encapsulating structure schematic diagram of encapsulating material；
Fig. 2 e are the encapsulating structure schematic diagrames after another preferred embodiment of the invention includes the wiring board inversion of encapsulating material；
Fig. 2 f are that another preferred embodiment of the invention includes the encapsulating structure schematic diagram of the first accumulated layers；
Fig. 2 g are the encapsulating structure schematic diagrames of the blind hole in the first accumulated layers and encapsulating material in another preferred embodiment of the invention；
Fig. 2 h are that another preferred embodiment of the invention includes that the first rewiring layer and second reroutes the encapsulating structure schematic diagram of layer；
Fig. 2 i are that another preferred embodiment of the invention includes the encapsulating structure schematic diagram of the second accumulated layers；
Fig. 2 j are that another preferred embodiment of the invention includes the encapsulating structure schematic diagram of triple wiring layers；
Fig. 2 k are that another preferred embodiment of the invention includes the encapsulating structure schematic diagram of solder mask；
Fig. 2 l are to complete the surface-pasted structural representation of passive device after semiconductor chip and the embedded encapsulation of capsulation body of semiconductor ship in another preferred embodiment of the invention.
The mark of each part is as follows in accompanying drawing：1- wiring boards, 11- first surfaces, 12- second surfaces, 13- line layers, 2- is open or cavity, the spaces of 21- first, 22- second spaces, 31- semiconductor chips, 32- capsulation body of semiconductor ship, 321- semiconductor bare crystalline pieces, 322- capsulation materials, 323- inner conductives lead or wiring, 324- outer electrodes, 4- encapsulating materials, 5- modules contraposition mark, 6- reroutes layer, 61- first reroutes layer, 62 second reroute layer, the triple wiring layers of 63-, 7- passive electronic components, the accumulated layers of 81- first, the accumulated layers of 82- second, 811, 812, 813- is open, 10- solder masks, 101- semiconductor packing devices and/or passive electronic component, 201- adhesive films.
Specific embodiment
Presently preferred embodiments of the present invention is described in detail below in conjunction with the accompanying drawings, so that advantages and features of the invention can be easier to be readily appreciated by one skilled in the art, apparent is clearly defined so as to be made to protection scope of the present invention.
The embedded hybrid package structure of semiconductor in a specific embodiment of the invention, shown in ginseng Fig. 1, the encapsulating structure is specifically included：
Wiring board 1, i.e., for packaged semiconductor (Bare Die) and the line carrier plate of capsulation body of semiconductor ship (Semiconductor Package), it has the first surface 11 and second surface 12 being oppositely arranged；
It is in the wiring board 1, at least one be used to accommodating semiconductor chip 31 and at least one and be used to opening or the cavity 2 of accommodating capsulation body of semiconductor ship 32；
It is arranged at semiconductor chip 31 and capsulation body of semiconductor ship 32 in the opening or cavity 2；
Encapsulating material 4, is at least used to cover first surface 11, the module contraposition mark 5 of wiring board and fills the space not occupied by semiconductor chip 31 and capsulation body of semiconductor ship 32 in the opening or cavity 2；
Layer 6 is rerouted, at least for being electrically connected semiconductor chip 31, capsulation body of semiconductor ship 32 and wiring board 1.
With reference to shown in Fig. 1 a, 1b, the first surface 11 of wiring board, second surface 12 and the region between first surface 11 and second surface 12 are respectively equipped with line layer 13, module contraposition mark 5 is arranged at the first surface of wiring board 1, and the surface of module contraposition mark 5 and the second surface of wiring board distinguish the highest face temperature and minimum surface of corresponding line plate.Module contraposition mark 5 is used to realize accurate semiconductor chip, capsulation body of semiconductor ship arrangement and conducting wire interconnection that all mark or portion identification can simultaneously turn into connection line and provide conducting function.
The highest face temperature and minimum surface of the opening or the in the vertical direction of cavity 2 are respectively highest face temperature or the module contraposition 5 surfaces of mark and the second surface 12 or its minimum surface of the wiring board 1 of the wiring board 1,And the opening or cavity 2 border in the horizontal direction are the side wall of opening or cavity 2 of the wiring board 1 between first surface 11 and second surface 12,The opening or cavity 2 include the first space 21 and second space 22 simultaneously,Wherein described first space 21 is distributed between the first surface 11 of the wiring board 1 and second surface 12,The second space 22 is distributed between 5 surfaces of the first surface 11 of the wiring board 1 and module contraposition mark,And the side wall in first space 21 is the continuous section of wiring board 1 between the wiring board first surface 11 and second surface 12,And the second space 21 is without side wall.
With reference to shown in Fig. 1 c, there is at least one semiconductor bare crystalline piece 321 in capsulation body of semiconductor ship 32.Wherein, semiconductor bare crystalline piece is that a based semiconductor device that etch, wiring etc. are made, can realizing specific function is carried out on semiconductor sheet material.And can obtain capsulation body of semiconductor ship 32 by the way that above-mentioned semiconductor bare crystalline piece 321 is carried out into plastic packaging encapsulation using capsulation material 322.Capsulation body of semiconductor ship 32 is arranged in the opening or cavity 2, capsulation body of semiconductor ship 32 includes being electrically connected with the electrode/pad of semiconductor bare crystalline piece 321 in capsulation body of semiconductor ship, and the package interior conductive lead wire or wiring 323 and outer electrode 324 stretched out from the semiconductor bare crystalline piece 321, outer electrode 324 is through the electrode/pad electric interconnection on the semiconductor bare crystalline piece 321 in inner conductive lead or wiring and capsulation body of semiconductor ship.The outer electrode 324 of capsulation body of semiconductor ship can be metal copper layer or the metal copper layer for covering ni/au layers.Capsulation body of semiconductor ship 32 can be the capsulation body of semiconductor ship with the encapsulating structures such as InFO, WLCSP, eWLB, FOWLP, FC-BGA, FC-CSP, WB-BGA, QFN or similar structures.
Further, the outer electrode 324 of capsulation body of semiconductor ship 32 is exposed aerial or by film covering in the present invention；The outer electrode 324 is copper metal layer or the copper metal layer for having ni/au layers covering；The material of the film is accumulated layers dielectric material, can be other accumulated layers dielectric materials such as capsulation material, increasing layer material or polyimides (Polyimide).
As in the present embodiment, encapsulating structure also includes the first accumulated layers 81 of the second surface 12, described encapsulating material 4, the semiconductor chip 31 and the capsulation body of semiconductor ship 32 that at least cover the wiring board 1；First accumulated layers 81 are dielectric materials layer, including ABF increasing layers, photaesthesia dielectric layer or other dielectric materials layers.
With reference to shown in Fig. 1 i, the first accumulated layers 81 are provided with blind hole above the line layer positioned at semiconductor chip, capsulation body of semiconductor ship outer electrode and wiring board；First accumulated layers are provided with the first rewiring layer 61 on the first rewiring layer 61, and first accumulated layers 81 by the line layer electric interconnection on the blind hole and semiconductor chip, the outer electrode and wiring board of capsulation body of semiconductor ship.The second rewiring layer 62 is additionally provided with encapsulating material 4 on wiring board first surface 11, described second reroutes layer 62 through the line layer on conductive blind hole and wiring board, semiconductor chip, and/or the electric interconnection of capsulation body of semiconductor ship outer electrode 324.
Further, with reference to shown in Fig. 1 j, 1k, first rewiring layer 61 and second to be rerouted and be coated with the second accumulated layers 82 on layer 62, the triple wiring layers 63 for rerouting layer and the second rewiring layer electric interconnection with first respectively are formed with second accumulated layers 82, wherein, the second accumulated layers are ABF increasing layers, photaesthesia dielectric layer or other dielectric materials layers etc..
In addition, encapsulating structure also includes at least covering the solder mask 10 of outermost line layer, is arranged on the opening of the outermost line layer top solder mask, the pad for being formed in said opening, the top of solder mask 10 is pasted with other semiconductor packing devices and/or passive electronic component 101, passive electronic component includes but is not limited to the elements such as electric capacity, resistance, inductance, and semiconductor packing device and/or passive electronic component 101 pass through the pad and triple wiring layer electric interconnections.In the present embodiment, the first accumulated layers and the second accumulated layers have been illustrated as a example by ABF increasing layers, and the first accumulated layers and the second accumulated layers can also be other dielectric materials layers in other embodiments.
Above-described embodiment is only a preferred embodiment of the present invention, it should be understood that, the first accumulated layers, the second accumulated layers, the first rewiring layer, the second rewiring layer and triple wiring layers can selectively be set in other embodiments, such as only set the first accumulated layers, the first rewiring layer and second and reroute layer；In addition; be may further be provided except above-mentioned accumulated layers and in addition to rerouting layer other for be electrically connected interconnection layer, as long as can reach other semiconductor packing devices and/or passive electronic component 101 belongs to the scope protected of the invention with the encapsulating structure of semiconductor chip, capsulation body of semiconductor ship or wiring board electrical connection.
The preparation method that another aspect of the present invention additionally provides a kind of embedded hybrid package structure of semiconductor, comprises the following steps：
S1, offer wiring board, it has the first surface and second surface being oppositely arranged, at least one is provided with the wiring board for housing opening or the cavity of semiconductor chip and capsulation body of semiconductor ship, and the first surface upper shed of the wiring board or cavity surrounding are provided with module contraposition mark；
S2, adhesive film is attached on the second surface of the wiring board, and the semiconductor chip and capsulation body of semiconductor ship are inserted into the opening or cavity, and the capsulation body of semiconductor ship is adhesively fixed with adhesive film；
Apply encapsulating material on S3, the first surface at least in the wiring board, module contraposition mark and the opening or cavity, the first surface of the wiring board, the packed material of module contraposition mark are covered, and is filled up completely with the opening or the packed material of cavity and the semiconductor chip and capsulation body of semiconductor ship；
S4, the removal adhesive film, and the wiring board is overturn；
S5, the wiring board second surface, semiconductor chip, capsulation body of semiconductor ship and with the wiring board second surface more than one layer accumulated layers of coplanar encapsulating material surface overlying lid；
S6, formed in the accumulated layers and to be at least used for the rewiring layer for being electrically connected semiconductor chip, capsulation body of semiconductor ship and wiring board.
Specifically, elaborated below in conjunction with the preparation method shown in accompanying drawing to the embedded hybrid package structure of semiconductor in one embodiment of the present invention.
Shown in ginseng Fig. 1 a, there is provided wiring board 1, it has a first surface 11 and second surface 12 being oppositely arranged, and the first surface 11 of wiring board, second surface 12 and the region between first surface 11 and second surface 12 are respectively equipped with line layer 13.Include at least one opening or the cavity 2 for being used to accommodating semiconductor chip 31 and capsulation body of semiconductor ship 32 on wiring board 1.Preferably, the present embodiment includes multiple openings or cavity 2, is respectively used to accommodating semiconductor chip 31, capsulation body of semiconductor ship 32.
Module contraposition mark 5 is arranged at the first surface of wiring board 1, and the surface of module contraposition mark 5 and the second surface of wiring board distinguish the highest face temperature and minimum surface of corresponding line plate.
Shown in ginseng Fig. 1 b, 1d, adhesive film 201 is attached on the second surface 12 of assist side 1, and the semiconductor chip 31 and capsulation body of semiconductor ship 32 are inserted into the opening or cavity 2 with reversion form, and the outer electrode of the capsulation body of semiconductor ship 3 and adhesive film 201 is bonded and fixed in opening or cavity 2.
Wherein, the structural representation of capsulation body of semiconductor ship 32 is joined shown in Fig. 1 c in the present embodiment, has at least one semiconductor bare crystalline piece 321 in capsulation body of semiconductor ship 32.Wherein, semiconductor bare crystalline piece is that a based semiconductor device that etch, wiring etc. are made, can realizing specific function is carried out on semiconductor sheet material.And can obtain capsulation body of semiconductor ship 32 by the way that above-mentioned semiconductor bare crystalline piece 321 is carried out into plastic packaging encapsulation using capsulation material 322.Capsulation body of semiconductor ship 32 is arranged in the opening or cavity 2, capsulation body of semiconductor ship 32 includes being electrically connected with the electrode/pad of semiconductor bare crystalline piece 321 in capsulation body of semiconductor ship, and the package interior conductive lead wire or wiring 323 and outer electrode 324 stretched out from the semiconductor bare crystalline piece 321, outer electrode 324 is through the electrode/pad electric interconnection on the semiconductor bare crystalline piece 321 in inner conductive lead or wiring and capsulation body of semiconductor ship.
Shown in ginseng Fig. 1 e, the space plastic packaging not occupied by semiconductor chip 31 and capsulation body of semiconductor ship 32 in the top of first surface 11, module contraposition mark 5 of assist side and the filling opening or cavity 2 forms one layer of encapsulating material 4.
In this step, can also planarizing process be carried out to encapsulating material 4.
Wherein, encapsulating material 4 can be molding compounds (Molding compound), epoxy resin or epoxy resin/filler compound etc., and it is filled into opening or cavity 2 and the first surface 11 of wiring board 1 is covered as a flat accumulation horizon.
Shown in ginseng Fig. 1 f, the adhesive film 201 is removed, and above-mentioned wiring board 1 is overturn.
Shown in ginseng Fig. 1 g, 1h and 1i, the first accumulated layers 81 of at least second surface 12 of covering wiring board 1, encapsulating material 4, semiconductor chip 31 and capsulation body of semiconductor ship 32 are formed on the second surface 12 of the wiring board 1 after upset, and the removal of the first accumulated layers 81 in the top of the outer electrode 32 of the electrode of semiconductor chip 31 and capsulation body of semiconductor ship 3 forms opening 811, the mode of opening 811 of formation has laser boring, photoetching etc..Then form first by opening 811 in the first accumulated layers 81 and reroute layer 61 (RDL)；Similarly, the surface of the encapsulating material 4 on the first surface 11 of assist side 1 equally can form opening 812 using the corresponding encapsulating material of the technique of laser opening removal, and on top of the encapsulation material by the formation of opening 812 second rewiring layer 62.Rerouting the forming method of layer includes that metal film, dry film pressing, exposing patterns, development, copper facing, striping, a sequence technique of copper etching；Or film, copper facing, dry film pressing, exposing patterns, development, copper etching, a sequence technique of striping including metal.
Shown in ginseng Fig. 1 j, 1k, layer 61 and second is rerouted first reroute the second accumulated layers 82 of the top of layer 62 formation, opening 813 is formed with the second accumulated layers 82, the second accumulated layers on assist side first surface set conductive blind hole, and form triple wiring layers 63 that the rewiring electric interconnection of layer 62 of layer 61 and/or second is rerouted through conductive blind hole and first by opening 813 in the second accumulated layers 81.Triple wiring layers are respectively positioned at the both sides up and down of encapsulating structure in the present embodiment.
Shown in ginseng Fig. 1 l, solder mask 10 is formed on the outermost line layer of encapsulating structure, be open on solder mask above outermost line layer, and copper electrode surface carrying out nickel leaching gold at the opening of solder mask technique forming pad after depositing ni/au layers；
Finally shown in ginseng Fig. 1 m, in the top mounting semiconductor packaging and/or passive electronic component 101 of the split shed of solder mask 10, the semiconductor packing device and/or passive electronic component pass through the pad and triple wiring layer electric interconnections.
And in other more preferred embodiment, packed object further relates to one or more passive electronic components 7 except described semiconductor chip 31, capsulation body of semiconductor ship 32.The typical encapsulating structure of one of which see shown in Fig. 2, and its preparation method is joined shown in Fig. 2 a- Fig. 2 l, the preparation method is essentially identical with foregoing preparation method (Fig. 1 a- Fig. 1 m), the opening or cavity 2 for housing passive electronic component 7 are which increased, the first rewiring layer 61 is carried out in the opening where passive electronic component 7 or the correspondence position of cavity 2 correspondence and triple wiring layers 63 is encapsulated.
Specifically, the embedded hybrid package structure of semiconductor in another specific embodiment of the invention, shown in ginseng Fig. 2, the encapsulating structure is specifically included：
Wiring board 1, it is used for the line carrier plate of packaged semiconductor (Bare Die), capsulation body of semiconductor ship (Semiconductor Package) and passive electronic component 7, it has the first surface 11 and second surface 12 being oppositely arranged；
It is in the wiring board 1, at least one be used to accommodating semiconductor chip 31, at least one and be used to accommodating capsulation body of semiconductor ship 32 and at least one to be used to opening or the cavity 2 of accommodating passive electronic component 7；
It is arranged at semiconductor chip 31, capsulation body of semiconductor ship 32 and passive electronic component 7 in the opening or cavity 2；
Encapsulating material 4, is at least used to cover first surface 11, the module contraposition mark 5 of wiring board and fills the space not occupied by semiconductor chip 31, capsulation body of semiconductor ship 32 and passive electronic component 7 in the opening or cavity 2；
Layer 6 is rerouted, at least for being electrically connected semiconductor chip 31, capsulation body of semiconductor ship 32, passive electronic component 7 and wiring board 1.
With reference to shown in Fig. 2 a, 2b, the first surface 11 of wiring board, second surface 12 and the region between first surface 11 and second surface 12 are respectively equipped with line layer 13, module contraposition mark 5 is arranged at the first surface of wiring board 1, and the surface of module contraposition mark 5 and the second surface of wiring board distinguish the highest face temperature and minimum surface of corresponding line plate.Module contraposition mark 5 is used to realize accurate semiconductor chip, capsulation body of semiconductor ship, passive electronic component arrangement and conducting wire interconnection that all mark or portion identification can simultaneously turn into connection line and provide conducting function.
The highest face temperature and minimum surface of the opening or the in the vertical direction of cavity 2 are respectively highest face temperature or the module contraposition 5 surfaces of mark and the second surface 12 or its minimum surface of the wiring board 1 of the wiring board 1,And the opening or cavity 2 border in the horizontal direction are the side wall of opening or cavity 2 of the wiring board 1 between first surface 11 and second surface 12,The opening or cavity 2 include the first space 21 and second space 22 simultaneously,Wherein described first space 21 is distributed between the first surface 11 of the wiring board 1 and second surface 12,The second space 22 is distributed between 5 surfaces of the first surface 11 of the wiring board 1 and module contraposition mark,And the side wall in first space 21 is the continuous section of wiring board 1 between the wiring board first surface 11 and second surface 12,And the second space 21 is without side wall.
Same as the previously described embodimentsly, there is at least one semiconductor bare crystalline piece 321 in capsulation body of semiconductor ship 32.Wherein, semiconductor bare crystalline piece is that a based semiconductor device that etch, wiring etc. are made, can realizing specific function is carried out on semiconductor sheet material.And can obtain capsulation body of semiconductor ship 32 by the way that above-mentioned semiconductor bare crystalline piece 321 is carried out into plastic packaging encapsulation using capsulation material 322.Capsulation body of semiconductor ship 32 is arranged in the opening or cavity 2, capsulation body of semiconductor ship 32 includes being electrically connected with the electrode/pad of semiconductor bare crystalline piece 321 in capsulation body of semiconductor ship, and the package interior conductive lead wire or wiring 323 and outer electrode 324 stretched out from the semiconductor bare crystalline piece 321, outer electrode 324 is through the electrode/pad electric interconnection on the semiconductor bare crystalline piece 321 in inner conductive lead or wiring and capsulation body of semiconductor ship.The outer electrode 324 of capsulation body of semiconductor ship can be metal copper layer or the metal copper layer for covering ni/au layers.Capsulation body of semiconductor ship 32 can be the capsulation body of semiconductor ship with the encapsulating structures such as InFO, WLCSP, eWLB, FOWLP, FC-BGA, FC-CSP, WB-BGA, QFN or similar structures.
From unlike the embodiment shown in Fig. 1, outs open or cavity 2 are interior except for installing semiconductor chip 31 and capsulation body of semiconductor ship 32 in the present embodiment, other opening or cavity 2 can also be used to install other passive electronic components 7, passive electronic component includes but is not limited to the elements such as electric capacity, resistance, inductance, and encapsulating material 4 is additionally operable to fill the space not occupied by passive electronic component 7 in the opening or cavity.
Further, the outer electrode 324 of capsulation body of semiconductor ship 32 is exposed aerial or by film covering in the present invention；The outer electrode 324 is copper metal layer or the copper metal layer for having ni/au layers covering；The material of the film is accumulated layers dielectric material, can be other accumulated layers dielectric materials such as capsulation material, increasing layer material or polyimides (Polyimide).
As in the present embodiment, encapsulating structure also includes the first accumulated layers 81 of the second surface 12, described encapsulating material 4, the semiconductor chip 31, capsulation body of semiconductor ship 32 and the passive electronic component 7 that at least cover the wiring board 1；First accumulated layers 81 are dielectric materials layer, including ABF increasing layers, photaesthesia dielectric layer or other dielectric materials layers.
With reference to shown in Fig. 2 h, the first accumulated layers 81 are provided with blind hole above the line layer positioned at semiconductor chip, capsulation body of semiconductor ship outer electrode, passive electronic component 7 and wiring board；First accumulated layers are provided with the first rewiring layer 61 on the first rewiring layer 61, and first accumulated layers 81 by the line layer electric interconnection on the blind hole and semiconductor chip, the outer electrode of capsulation body of semiconductor ship, passive electronic component and wiring board.The second rewiring layer 62 is additionally provided with encapsulating material 4 on wiring board first surface 11, described second reroutes layer 62 through the line layer on conductive blind hole and wiring board, semiconductor chip, and/or capsulation body of semiconductor ship outer electrode 324 and/or the electric interconnection of passive electronic component 7.
Further, with reference to shown in Fig. 2 i, 2j, first rewiring layer 61 and second to be rerouted and be coated with the second accumulated layers 82 on layer 62, the triple wiring layers 63 for rerouting layer and the second rewiring layer electric interconnection with first respectively are formed with second accumulated layers 82, wherein, the second accumulated layers are ABF increasing layers, photaesthesia dielectric layer or other dielectric materials layers etc..
In addition, encapsulating structure also includes at least covering the solder mask 10 of outermost line layer, is arranged on the opening of the outermost line layer top solder mask, the pad for being formed in said opening, the top of solder mask 10 is pasted with other semiconductor packing devices and/or passive electronic component 101, passive electronic component includes but is not limited to the elements such as electric capacity, resistance, inductance, and semiconductor packing device and/or passive electronic component 101 pass through the pad and triple wiring layer electric interconnections.In the present embodiment, the first accumulated layers and the second accumulated layers have been illustrated as a example by ABF increasing layers, and the first accumulated layers and the second accumulated layers can also be other dielectric materials layers in other embodiments.
Above-described embodiment is only a preferred embodiment of the present invention, it should be understood that, the first accumulated layers, the second accumulated layers, the first rewiring layer, the second rewiring layer and triple wiring layers can selectively be set in other embodiments, such as only set the first accumulated layers, the first rewiring layer and second and reroute layer；In addition; be may further be provided except above-mentioned accumulated layers and in addition to rerouting layer other for be electrically connected interconnection layer, as long as can reach other semiconductor packing devices and/or passive electronic component 101 belongs to the scope protected of the invention with the encapsulating structure of semiconductor chip, capsulation body of semiconductor ship, passive electronic component or wiring board electrical connection.
The preparation method that another aspect of the present invention additionally provides a kind of embedded hybrid package structure of semiconductor, comprises the following steps：
S1, offer wiring board, it has the first surface and second surface being oppositely arranged, at least one is provided with the wiring board for housing opening or the cavity of semiconductor chip, capsulation body of semiconductor ship and passive electronic component, and the first surface upper shed of the wiring board or cavity surrounding are provided with module contraposition mark；
S2, adhesive film is attached on the second surface of the wiring board, and the semiconductor chip, capsulation body of semiconductor ship and passive electronic component are inserted into the opening or cavity, and the capsulation body of semiconductor ship is adhesively fixed with adhesive film；
Apply encapsulating material on S3, the first surface at least in the wiring board, module contraposition mark and the opening or cavity, the first surface of the wiring board, the packed material of module contraposition mark are covered, and is filled up completely with the opening or the packed material of cavity and the semiconductor chip, capsulation body of semiconductor ship and passive electronic component；
S4, the removal adhesive film, and the wiring board is overturn；
S5, the wiring board second surface, semiconductor chip, capsulation body of semiconductor ship, passive electronic component and with the wiring board second surface more than one layer accumulated layers of coplanar encapsulating material surface overlying lid；
S6, formed in the accumulated layers and to be at least used for the rewiring layer for being electrically connected semiconductor chip, capsulation body of semiconductor ship, passive electronic component and wiring board.
Specifically, elaborated below in conjunction with the preparation method shown in accompanying drawing to the embedded hybrid package structure of semiconductor in one embodiment of the present invention.
Shown in ginseng Fig. 2 a, there is provided wiring board 1, it has a first surface 11 and second surface 12 being oppositely arranged, and the first surface 11 of wiring board, second surface 12 and the region between first surface 11 and second surface 12 are respectively equipped with line layer 13.It is used to accommodating semiconductor chip 31, the opening of capsulation body of semiconductor ship 32 and passive electronic component 7 or cavity 2 including at least one on wiring board 1.Preferably, the present embodiment includes multiple openings or cavity 2, is respectively used to accommodating semiconductor chip 31, capsulation body of semiconductor ship 32 and passive electronic component 7.
Module contraposition mark 5 is arranged at the first surface of wiring board 1, and the surface of module contraposition mark 5 and the second surface of wiring board distinguish the highest face temperature and minimum surface of corresponding line plate.
Shown in ginseng Fig. 2 b, 2c, adhesive film 201 is attached on the second surface 12 of assist side 1, and the semiconductor chip 31, capsulation body of semiconductor ship 32 and passive electronic component 7 are inserted into the opening or cavity 2 with reversion form, and the outer electrode of the capsulation body of semiconductor ship 3 and adhesive film 201 is bonded and fixed in opening or cavity 2.
Wherein, it is identical with the structure of capsulation body of semiconductor ship 32 in first embodiment shown in Fig. 1 c, there is at least one semiconductor bare crystalline piece 321 in capsulation body of semiconductor ship 32 in the present embodiment.Wherein, semiconductor bare crystalline piece is that a based semiconductor device that etch, wiring etc. are made, can realizing specific function is carried out on semiconductor sheet material.And can obtain capsulation body of semiconductor ship 32 by the way that above-mentioned semiconductor bare crystalline piece 321 is carried out into plastic packaging encapsulation using capsulation material 322.Capsulation body of semiconductor ship 32 is arranged in the opening or cavity 2, capsulation body of semiconductor ship 32 includes being electrically connected with the electrode/pad of semiconductor bare crystalline piece 321 in capsulation body of semiconductor ship, and the package interior conductive lead wire or wiring 323 and outer electrode 324 stretched out from the semiconductor bare crystalline piece 321, outer electrode 324 is through the electrode/pad electric interconnection on the semiconductor bare crystalline piece 321 in inner conductive lead or wiring and capsulation body of semiconductor ship.
Shown in ginseng Fig. 2 d, the space plastic packaging not occupied by semiconductor chip 31, capsulation body of semiconductor ship 32 and passive electronic component 7 in the top of first surface 11, module contraposition mark 5 of assist side and the filling opening or cavity 2 forms one layer of encapsulating material 4.
In this step, can also planarizing process be carried out to encapsulating material 4.
Wherein, encapsulating material 4 can be molding compounds (Molding compound), epoxy resin or epoxy resin/filler compound etc., and it is filled into opening or cavity 2 and the first surface 11 of wiring board 1 is covered as a flat accumulation horizon.
Shown in ginseng Fig. 2 e, the adhesive film 201 is removed, and above-mentioned wiring board 1 is overturn.
Shown in ginseng Fig. 2 f, 2g and 2h, the first accumulated layers 81 of at least second surface 12 of covering wiring board 1, encapsulating material 4, semiconductor chip 31, capsulation body of semiconductor ship 32 and passive electronic component 7 are formed on the second surface 12 of the wiring board 1 after upset, and the removal of the first accumulated layers 81 in the top of the outer electrode 32 of the electrode of semiconductor chip 31, capsulation body of semiconductor ship 3 and passive electronic component 7 forms opening 811, the mode of opening 811 of formation has laser boring, photoetching etc..Then form first by opening 811 in the first accumulated layers 81 and reroute layer 61 (RDL)；Similarly, the surface of the encapsulating material 4 on the first surface 11 of assist side 1 equally can form opening 812 using the corresponding encapsulating material of the technique of laser opening removal, and on top of the encapsulation material by the formation of opening 812 second rewiring layer 62.Rerouting the forming method of layer includes that metal film, dry film pressing, exposing patterns, development, copper facing, striping, a sequence technique of copper etching；Or film, copper facing, dry film pressing, exposing patterns, development, copper etching, a sequence technique of striping including metal.
Shown in ginseng Fig. 2 i, 2j, layer 61 and second is rerouted first reroute the second accumulated layers 82 of the top of layer 62 formation, opening 813 is formed with the second accumulated layers 82, the second accumulated layers on assist side first surface set conductive blind hole, and form triple wiring layers 63 that the rewiring electric interconnection of layer 62 of layer 61 and/or second is rerouted through conductive blind hole and first by opening 813 in the second accumulated layers 81.Triple wiring layers are respectively positioned at the both sides up and down of encapsulating structure in the present embodiment.
Shown in ginseng Fig. 2 k, solder mask 10 is formed on the outermost line layer of encapsulating structure, be open on solder mask above outermost line layer, and copper electrode surface carrying out nickel leaching gold at the opening of solder mask technique forming pad after depositing ni/au layers；
Finally shown in ginseng Fig. 2 l, in the top mounting semiconductor packaging and/or passive electronic component 101 of the split shed of solder mask 10, the semiconductor packing device and/or passive electronic component pass through the pad and triple wiring layer electric interconnections.
Compared with prior art, embedded hybrid package structure of semiconductor in the present invention and preparation method thereof uses wiring board embedded technology scheme, the integrated process flow of semiconductor chip and capsulation body of semiconductor ship can be simplified, improve integrated quality and performance, integrated area is effectively reduced, is specifically included：
By semiconductor chip and semiconductor package body, assist side completes encapsulation process simultaneously, eliminate both complicated and cumbersome standards in the prior art and technique docking, the circulation transfer of electronic manufacture is reduced, is used manpower and material resources sparingly, can further reduce the cost of electronic product；
The electrical connection of semiconductor chip and wiring board and capsulation body of semiconductor ship and wiring board uses succinct copper to reroute (RDL) scheme without scolding tin connection scheme, process stabilizing and reliability is high；
The assembling demand of more accurate semiconductor chip and capsulation body of semiconductor ship can be met, such as pad of semiconductor chip or capsulation body of semiconductor ship/pad spacing can narrow down to 150 microns/less than 200 microns；
The embedded assembling of semiconductor chip and capsulation body of semiconductor ship makes the surface area of wiring board fully be discharged, it is possible to achieve system assembles area significantly reduces, and reduction ratio can be more than 50%.
It should be understood that; the foregoing is only embodiments of the invention; not thereby the scope of the claims of the invention is limited; equivalent structure or equivalent flow conversion that every utilization description of the invention and accompanying drawing content are made; or other related technical fields are directly or indirectly used in, it is included within the scope of the present invention.
Claims (16)
1. the embedded hybrid package structure of a kind of semiconductor, it is characterised in that the encapsulating structure includes：
Wiring board, it has the first surface and second surface being oppositely arranged；
Opening or cavity in the wiring board, that be at least used to accommodating semiconductor chip and capsulation body of semiconductor ship；
It is arranged at the semiconductor chip in the opening or cavity；
It is arranged at the capsulation body of semiconductor ship in the opening or cavity；
Encapsulating material, be at least used to cover the first surface of wiring board and fill in the opening or cavity not by semiconductor chip and
The space that capsulation body of semiconductor ship is occupied；
Layer is rerouted, at least for being electrically connected semiconductor chip, capsulation body of semiconductor ship and wiring board.
2. the embedded hybrid package structure of semiconductor according to claim 1, it is characterised in that the first of the wiring board
Surface is provided with module contraposition mark, the surface of module contraposition mark and the second surface of the wiring board corresponding circuit respectively
The highest face temperature and minimum surface of plate.
3. the embedded hybrid package structure of semiconductor according to claim 1, it is characterised in that in the opening or cavity
Passive electronic component is additionally provided with, the passive electronic component includes the group of any one or more in electric capacity, resistance, inductance element
Close.
4. the embedded hybrid package structure of semiconductor according to claim 1, it is characterised in that capsulation body of semiconductor ship
Inside there is at least one semiconductor bare crystalline piece, and be the capsulation body of semiconductor ship with capsulation material encapsulation.
5. the embedded hybrid package structure of semiconductor according to claim 4, it is characterised in that the semiconductor chip envelope
Dress body comprising with the electrode of semiconductor bare crystalline piece in capsulation body of semiconductor ship/pad electrical connection, and from the semiconductor bare crystalline piece
The conductive lead wire for stretching out or wiring.
6. the embedded hybrid package structure of semiconductor according to claim 5, it is characterised in that the semiconductor chip envelope
Dress body also includes the outer electrode being electrically connected with semiconductor bare crystalline piece, and the outer electrode is exposed aerial or quilt
Film covering；The material of the outer electrode is copper metal layer or the copper metal layer for having ni/au layers covering；The material of the film
Expect to be accumulated layers dielectric material, including capsulation material or increasing layer material or polyimides.
7. the embedded hybrid package structure of semiconductor according to claim 3, it is characterised in that the encapsulating material is also used
In the space not occupied by passive electronic component in the filling opening or cavity.
8. the embedded hybrid package structure of semiconductor according to claim 1 or 3, it is characterised in that the encapsulating structure
Also include at least covering second surface, described encapsulating material, the semiconductor chip and the semiconductor of the wiring board
First accumulated layers of chip packing-body；First accumulated layers are dielectric materials layer, including ABF increasing layers or photaesthesia dielectric layer.
9. the embedded hybrid package structure of semiconductor according to claim 8, it is characterised in that first accumulated layers exist
Line layer top positioned at the electrode/pad, capsulation body of semiconductor ship outer electrode and wiring board of semiconductor chip is provided with blind hole；
First accumulated layers be provided with the first rewiring layer, and in first accumulated layers first rewiring layer by the blind hole with
Line layer electric interconnection on the electrode/pad of semiconductor chip, capsulation body of semiconductor ship outer electrode and/or wiring board.
10. the embedded hybrid package structure of semiconductor according to claim 9, it is characterised in that the wiring board first
Be additionally provided with encapsulating material on surface the second rewiring layer, it is described second reroute layer through conductive blind hole at least with wiring board on
The outer electrode electric interconnection of line layer, semiconductor chip, and/or capsulation body of semiconductor ship.
The 11. embedded hybrid package structures of semiconductor according to claim 10, it is characterised in that described first reroutes
The second accumulated layers are coated with layer and/or the second rewiring layer, are formed with second accumulated layers and are rerouted layer and/or the with first
Triple wiring layers of double wiring layer electric interconnection, second accumulated layers include ABF increasing layers or photaesthesia dielectric layer.
The 12. embedded hybrid package structures of semiconductor according to claim 11, it is characterised in that the encapsulating structure is also
Including the opening at least covering the solder mask of outermost line layer and be arranged in the solder mask；In the mask open
Line layer formed connection outer member pad.
The 13. embedded hybrid package structures of semiconductor according to claim 12, it is characterised in that the encapsulating structure is also
Including attachment solder mask above semiconductor packing device and/or passive electronic component, the passive electronic component include electric capacity,
The combination of any one or more in resistance, inductance element, the semiconductor packing device and/or passive electronic component are by described
Pad and triple wiring layer electric interconnections.
14. a kind of preparation methods of the embedded hybrid package structure of semiconductor, it is characterised in that the preparation method includes following
Step：
S1, offer wiring board, it has the first surface and second surface being oppositely arranged, is provided with the wiring board and at least used
To house opening or the cavity of semiconductor chip and capsulation body of semiconductor ship；
S2, adhesive film is attached on the second surface of the wiring board, and by the semiconductor chip and capsulation body of semiconductor ship
The opening or cavity are inserted, and the semiconductor chip and capsulation body of semiconductor ship is adhesively fixed with adhesive film；
S3, at least apply encapsulating material on the first surface and the opening or cavity of the wiring board, make the wiring board
The packed material covering of first surface, and make the opening or cavity packed material and the semiconductor chip and semiconductor core
Piece packaging body is filled up completely with；
S4, the removal adhesive film, and the wiring board is overturn；
S5, the wiring board second surface, semiconductor chip, capsulation body of semiconductor ship and with the wiring board second surface
More than one layer accumulated layers of coplanar encapsulating material surface overlying lid；
S6, to be formed in the accumulated layers be at least used for and be electrically connected semiconductor chip, capsulation body of semiconductor ship and wiring board
Rewiring layer.
The preparation method of the 15. embedded hybrid package structures of semiconductor according to claim 14, it is characterised in that described
Step S6 includes：
Above the line layer positioned at the electrode/pad, capsulation body of semiconductor ship outer electrode and wiring board of semiconductor chip
One accumulated layers set blind hole, and form electrode/pad by the blind hole and semiconductor chip, outside capsulation body of semiconductor ship
First rewiring layer of the line layer electric interconnection on electrode, and/or wiring board；
Second is set on encapsulating material on assist side first surface and reroutes layer；Described second reroute layer through conductive blind hole and
The outer electrode electric interconnection of line layer, semiconductor chip, and/or capsulation body of semiconductor ship on wiring board；
The second accumulated layers are formed on the first rewiring layer and/or the second rewiring layer, and sets conductive blind in the second accumulated layers
Hole, and form triple wiring layers that layer and/or the second rewiring layer are rerouted through conductive blind hole electrical connection first.
The preparation method of the 16. embedded hybrid package structures of semiconductor according to claim 15, it is characterised in that described
Also include after step S6：
Form solder mask on the outermost line layer of encapsulating structure, and be open simultaneously on solder mask above line layer
Form respective pad；
Mounting semiconductor packaging and/or passive electronic component above solder mask, the semiconductor packing device and/or passive
Electronic component passes through the pad and triple wiring layer electric interconnections.
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| CN108711570A (en) * | 2018-08-10 | 2018-10-26 | 付伟 | The multichip packaging structure and preparation method thereof of integrated chip package structure |
| CN109509727A (en) * | 2017-09-15 | 2019-03-22 | Pep创新私人有限公司 | A kind of semiconductor chip packaging method and encapsulating structure |
| CN113161249A (en) * | 2021-03-31 | 2021-07-23 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| US11189500B2 (en) | 2018-11-20 | 2021-11-30 | AT&S (Chongqing) Company Limited | Method of manufacturing a component carrier with an embedded cluster and the component carrier |
| TWI829396B (en) * | 2022-10-21 | 2024-01-11 | 欣興電子股份有限公司 | Circuit board structure and manufacturing method thereof |
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| CN101859752A (en) * | 2009-04-06 | 2010-10-13 | 杨文焜 | Stack package structure and manufacture method thereof with chip embedded and silicon through hole crystal grain |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109509727A (en) * | 2017-09-15 | 2019-03-22 | Pep创新私人有限公司 | A kind of semiconductor chip packaging method and encapsulating structure |
| CN109509727B (en) * | 2017-09-15 | 2023-01-31 | Pep创新私人有限公司 | Semiconductor chip packaging method and packaging structure |
| CN108711570A (en) * | 2018-08-10 | 2018-10-26 | 付伟 | The multichip packaging structure and preparation method thereof of integrated chip package structure |
| CN108711570B (en) * | 2018-08-10 | 2024-03-29 | 浙江熔城半导体有限公司 | Multi-chip packaging structure of integrated chip packaging structure and manufacturing method thereof |
| US11189500B2 (en) | 2018-11-20 | 2021-11-30 | AT&S (Chongqing) Company Limited | Method of manufacturing a component carrier with an embedded cluster and the component carrier |
| CN113161249A (en) * | 2021-03-31 | 2021-07-23 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
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| TWI829396B (en) * | 2022-10-21 | 2024-01-11 | 欣興電子股份有限公司 | Circuit board structure and manufacturing method thereof |
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| CN106816416B (en) | 2020-02-14 |
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