CN106815178A - High-speed reconfigurable data processing unit and method based on PLD - Google Patents
High-speed reconfigurable data processing unit and method based on PLD Download PDFInfo
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- CN106815178A CN106815178A CN201710041211.3A CN201710041211A CN106815178A CN 106815178 A CN106815178 A CN 106815178A CN 201710041211 A CN201710041211 A CN 201710041211A CN 106815178 A CN106815178 A CN 106815178A
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- 238000007726 management method Methods 0.000 claims abstract description 43
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- 238000003860 storage Methods 0.000 claims description 16
- 238000003672 processing method Methods 0.000 claims description 7
- 230000003068 static effect Effects 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 6
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present invention discloses a kind of high-speed reconfigurable data processing unit and method based on PLD, and the device includes PCIE bridging chips, management control chip, code memory, some arithmetic processors and some data storages；PCIE bridging chips connect PCIE EBIs；Management control chip is interconnected by 32 bit data bus, 30 bit address buses and arithmetic processor；Code memory passes through 25 bit address buses and 16 bit data bus connection management control chips；Arithmetic processor is connected with PCIE bridging chips；Data storage connects one to one with arithmetic processor.The present invention provides a kind of external data processing accelerator for computer, and using PCIE EBIs, highly versatile, transmission speed is fast；Data operation is processed by arithmetic processor；Arithmetic processor selects programming device, and low cost, low-power consumption, low heating, program is flexibly customized.
Description
Technical field
The present invention relates to a kind of data processing equipment, more particularly to a kind of high-speed reconfigurable based on PLD
Data processing equipment and method.
Background technology
High speed development and popularization with information technology, information technology is to the dependence more and more higher of big data, big data
Have swept the globe such as tide, life, work and the mode of thinking of people are changed deeply.Global metadata is increased with geometric progression
Long, the application of future computer will launch around big data.The arrival of big data, to the processing data ability band of computer
New challenge.At present, the treatment for big data is still based on the central processing unit (CPU) and graphic process unit of computer
(GPU) realize, when the data-handling capacity of single cpu is limited, traditional method is to improve computer by increasing CPU quantity
Data processing performance, but the price of CPU is higher, and it is big to the cost pressure that enterprise brings to increase CPU quantity, and with
The increase of CPU quantity, the power consumption of computer and heating will also increase therewith.
The content of the invention
It is an object of the invention to by a kind of high-speed reconfigurable data processing unit based on PLD and
Method is mentioned solving the problems, such as background section above.
It is that, up to this purpose, the present invention uses following technical scheme：
A kind of high-speed reconfigurable data processing unit based on PLD, it includes PCIE bridging chips, pipe
Reason control chip, code memory, some arithmetic processors and some data corresponding with some arithmetic processors
Holder；The PCIE bridging chips connect PCIE EBIs, for PCIE EBIs to be converted into local 32 s'
Parallel bus interface；The management control chip passes through 32 bit data bus, 30 bit address buses and some calculation process
Device is interconnected, for initializing the arithmetic processor, and to carried out between PCIE bridging chips and arithmetic processor data and when
The management control of sequence, makes data accurately be transferred to specified address process and returning result；The code memory passes through
25 bit address buses and 16 bit data bus connection management control chips, it is each required for storing some arithmetic processors
Data operation program, and management control chip control under be supplied to some arithmetic processors；Some arithmetic processors
It is connected with PCIE bridging chips, for each completing data operation according to the data operation program that receives, and by operation result
Server is transferred to by PCIE bridging chips；Some data storages are corresponded with some arithmetic processors and connected
Connect, for initial data, the storage of intermediate operations data and reading.
Especially, the high-speed reconfigurable data processing unit based on PLD include six arithmetic processors with
And six data storages connected one to one with six arithmetic processors.
Especially, PEX8311 type bridging chip of the PCIE bridging chips from Avago company.
Especially, the management control chip selects CPLD chips；The code memory selects FLASH storage chips.
Especially, the arithmetic processor selects fpga chip；The data storage is from synchronous static random-access
Memory (SSRAM).
Based on said apparatus, the invention also discloses a kind of high-speed reconfigurable data treatment based on PLD
Method, the method includes：
PCIE EBIs are converted into PCIE bridging chips the parallel bus interface of local 32；
Management control chip initialization arithmetic processor, and to carrying out data between PCIE bridging chips and arithmetic processor
Management with sequential is controlled, and data is accurately transferred to specified address process and returning result；
Code memory stores each required data operation program of some arithmetic processors, and in management control chip control
Some arithmetic processors are supplied under system；
Some arithmetic processors each complete data operation according to the data operation program that receives, and by operation result
Server is transferred to by PCIE bridging chips；
Some data storages connect one to one with some arithmetic processors, store with read initial data and in
Between operational data.
Especially, the high-speed reconfigurable data processing method based on PLD uses six calculation process
Device and six data storages connected one to one with six arithmetic processors.
Especially, PEX8311 type bridging chip of the PCIE bridging chips from Avago company.
Especially, the management control chip selects CPLD chips；The code memory selects FLASH storage chips.
Especially, the arithmetic processor selects fpga chip；The data storage is from synchronous static random-access
Memory.
The present invention provides a kind of external data processing accelerator for computer, and communication interface is using ripe, stabilization
PCIE EBIs, be installed in computer by PCIE EBIs, installed on computer corresponding driver and should
With software, corresponding application software is opened, you can access the accelerator, the computing of specific data is then by the computing of accelerator
Processor treatment.The present invention is provided with six arithmetic processors, and from programming device, program can be with flexible customization, at a high speed
Restructural, multi-field can use, while six arithmetic processors efficiently and executed in parallel computing multiple task management can realize many places
Reason device system is run simultaneously, and each arithmetic processor can carry out multi-thread data treatment, so as to more effectively improve data processing
Speed, 10-2000 times faster than common computer, and low-power consumption, low heating.The present invention uses extensive PCIE EBIs, leads to
Strong with property, transmission speed is fast, can meet the application of current high-speed computation.Programmability of the present invention is strong, and hardware interface is using calculating
The general control register of machine peripheral hardware, the mode of status register are defined, and interface clearly, can be according to different operating system designs
Driver, with good transplantability.Scalability of the invention is strong, can design corresponding application according to different applications
Program storage is in code memory.Superior performance of the present invention, data storage uses SSRAM, code memory from FLASH and
Arithmetic processor selects fpga chip.Fpga chip memory capacity is big in the present invention, can store more data amount.The present invention is being answered
Can bulk-download data, improving performance in.
Brief description of the drawings
Fig. 1 is the high-speed reconfigurable data processing unit structure based on PLD provided in an embodiment of the present invention
Figure.
Specific embodiment
For the ease of understanding the present invention, the present invention is described more fully below with reference to relevant drawings.In accompanying drawing
Give presently preferred embodiments of the present invention.But, the present invention can be realized in many different forms, however it is not limited to this paper institutes
The embodiment of description.On the contrary, the purpose for providing these embodiments is made to the more thorough of the disclosure understanding
Comprehensively.It should be noted that when an element is considered as " connection " another element, it can be directly to another
Element may be simultaneously present centering elements.Unless otherwise defined, all of technologies and scientific terms used here by the article with
Belong to the implication that those skilled in the art of the invention are generally understood that identical.Made in the description of the invention herein
Term is intended merely to describe the purpose of specific embodiment, it is not intended that in the limitation present invention.Term as used herein
" and/or " include the arbitrary and all of combination of one or more related Listed Items.
Refer to shown in Fig. 1, Fig. 1 is the high-speed reconfigurable number based on PLD provided in an embodiment of the present invention
According to processing unit structure chart.
The high-speed reconfigurable data processing unit 100 based on PLD specifically includes PCIE bridges in the present embodiment
Connect chip 101, management control chip 102, code memory 103, some arithmetic processors 104 and with some computings at
The corresponding some data storages 105 of reason device 104.The connection PCIE of PCIE bridging chips 101 EBIs 106, are used for
PCIE EBIs 106 (GEN1.0) are converted into the parallel bus interface of local 32；The management control chip 102 leads to
Cross 32 bit data bus, 30 bit address buses to be interconnected with some arithmetic processors 104, for initializing the calculation process
Device 104, and to carrying out the management control of data and sequential between PCIE bridging chips 101 and arithmetic processor 104, make data accurate
It is really errorless to be transferred to specified address process and returning result；The code memory 103 passes through 25 bit address buses and 16
Data/address bus connection management control chip 102, the data operation journey needed for for storing some arithmetic processors 104 each
Sequence, and it is supplied to some arithmetic processors 104 in the case where management control chip 102 is controlled；Some arithmetic processors 104 with
PCIE bridging chips 101 are connected, and for each completing data operation according to the data operation program for receiving, and operation result are led to
Cross PCIE bridging chips 101 and be transferred to server；Some data storages 105 and some arithmetic processors 104 1
One correspondence connection, for initial data, the storage of intermediate operations data and reading.
Specifically, the PCIE bridging chips 101 bridge core from the PEX8311 types of Avago company in the present embodiment
Piece.PEX8311 types bridging chip can carry out data transmission between PCIE buses and LOCAL buses (local bus), and it can
Main control device as 2 buses goes controlling bus, it is also possible to remove response bus as the target device of 2 buses.
PEX8311 types bridging chip is by internal logic control module, and internal bus state machine and local bus state machine module are common
The transmission of control data.
The management control chip 102 is from ALTERA EPM2210 serial CPLD chips, and its internal processes is customizable.
During work, management control chip 102 acts on as follows：First, some initial works of management configuration arithmetic processor 104：1st, carry
For Clock management, external clock was by after CPLD chips, entering BUFFER1 points for 6 tunnels provide each arithmetic processor 104；
2nd, the initial configuration of code, CPLD chips extract data from code memory 103 and are written to each by parallel bus
In arithmetic processor 104；For different application fields, there is provided the distinct program that the initial work of arithmetic processor 104 needs；
2nd, the management that data and sequential are carried out between PCIE bridging chips 101 and arithmetic processor 104 is controlled, it is ensured that data
The address specified accurately is transferred to get on process and returning result.The code memory 103 is public from NTEL
The FLASH storage chips of department, 64MB PC28F640P30B85.
The arithmetic processor 104 selects ALTERA CYCLONE V Series FPGA chips.Arithmetic processor 104 according to from
The data operation program obtained in code memory 103, carries out different treatment, so as to the knot for being needed to initial data
Really, it is delivered in PCIE buses eventually through local bus, is finally stored and shown in terminal device.Data storage
105 from synchronous static RAM (SSRAM), and storage initial data, intermediate operations data carry out middle fortune in real time
The storage of the evidence that counts and reading.
The high-speed reconfigurable data processing unit 100 based on PLD is included at six computings in the present embodiment
Reason device 104 and six data storages 105 connected one to one with six arithmetic processors 104.During work, server is issued
Data, PCIE bridging chips 101 are delivered to by PCIE EBIs 106 (250MB/S), in the association of management control chip 102
Under tune, data are split and then are transmitted according to specified address by local bus (32 bit data bus/30 bit address bus)
Calculation process is carried out in arithmetic processor 104.Data transfer is all two-way simultaneously is carried out, whenever data operation goes out result
When, will transmit to server and show and store.
Based on said apparatus, the present embodiment is also disclosed at a kind of high-speed reconfigurable data based on PLD
Reason method, the method includes：
PCIE EBIs are converted into PCIE bridging chips the parallel bus interface of local 32.
Management control chip initialization arithmetic processor, and to carrying out data between PCIE bridging chips and arithmetic processor
Management with sequential is controlled, and data is accurately transferred to specified address process and returning result.
Code memory stores each required data operation program of some arithmetic processors, and in management control chip control
Some arithmetic processors are supplied under system.
Some arithmetic processors each complete data operation according to the data operation program that receives, and by operation result
Server is transferred to by PCIE bridging chips.
Some data storages connect one to one with some arithmetic processors, real-time storage with read intermediate operations
Data, it is also possible to deposit some initial data in batches, can lift integral operation performance.
Likewise, the PCIE bridging chips select the PEX8311 type bridges of Avago company (AVAGO) in the present embodiment
Connect chip.PEX8311 types bridging chip can carry out data transmission between PCIE buses and LOCAL buses (local bus),
It can go controlling bus as the main control device of 2 buses, it is also possible to remove response bus as the target device of 2 buses.
PEX8311 types bridging chip is by internal logic control module, and internal bus state machine and local bus state machine module are common
The transmission of control data., from the CPLD chips of ALTERA EPM2210 series, its internal processes can for the management control chip
Customization.During work, management control chip effect is as follows：First, some initial works of management configuration arithmetic processor：1st, provide
Clock management, external clock was by after CPLD chips, entering 1 point of BUFFER for 6 tunnels provide each arithmetic processor；2nd, generation
The initial configuration of code, CPLD chips extract data from code memory and are written to each calculation process by parallel bus
In device；For different application fields, there is provided the distinct program that arithmetic processor initial work needs；2nd, PCIE is bridged
The management control of data and sequential is carried out between chip and arithmetic processor, it is ensured that data are accurately transferred to specified
Address get on process and returning result.The code memory selects the FLASH storage chips of NTEL companies, 64MB
PC28F640P30B85.Fpga chip of the arithmetic processor from ALTERA CYCLONE V series.Arithmetic processor root
According to the data operation program obtained from code memory, different treatment is carried out to initial data, so as to what is needed
As a result, it is delivered in PCIE buses eventually through local bus, is finally stored and shown in terminal device.The data storage
From synchronous static RAM (SSRAM), storage initial data, intermediate operations data carry out centre to storage in real time
The storage of operational data and reading.
During concrete application, the high-speed reconfigurable data processing method based on PLD uses six computings
Processor and six data storages connected one to one with six arithmetic processors.
The technical scheme is that computer provides a kind of external data processing accelerator, communication interface is used
Ripe, stabilization PCIE EBIs, are installed in computer by PCIE EBIs, and corresponding driving is installed on computer
Program and application software, open corresponding application software, you can access the accelerator, the computing of specific data is then by accelerating to fill
The arithmetic processor treatment put.The present invention is provided with six arithmetic processors, and from programming device, program can flexibly determine
System, high-speed reconfigurable multi-field can use, while six arithmetic processors can efficiently and executed in parallel computing multiple task management,
Realize that multicomputer system runs simultaneously, each arithmetic processor can carry out multi-thread data treatment, so as to more effectively improve
Data processing speed, 10-2000 times faster than common computer, and low-power consumption, low heating.The present invention uses extensive PCIE buses
Interface, highly versatile, transmission speed is fast, can meet the application of current high-speed computation.Programmability of the present invention is strong, and hardware interface is adopted
Defined with the general control register of computer peripheral equipment, the mode of status register, interface clearly, can be according to different operation systems
System design driven program, with good transplantability.Scalability of the invention is strong, can design corresponding according to different applications
Application program store in code memory.Superior performance of the present invention, data storage uses SSRAM, code memory to select
FLASH and arithmetic processor select fpga chip.Fpga chip memory capacity is big in the present invention, can store more data amount.This
Invention in the application can bulk-download data, improving performance.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention is carried out by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
More other Equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
1. a kind of high-speed reconfigurable data processing unit based on PLD, it is characterised in that including PCIE bridge joints
If chip, management control chip, code memory, some arithmetic processors and corresponding with some arithmetic processors
Dry data storage；The PCIE bridging chips connect PCIE EBIs, local for PCIE EBIs to be converted into
The parallel bus interface of 32；The management control chip passes through 32 bit data bus, 30 bit address buses and some fortune
Processor interconnection is calculated, for initializing the arithmetic processor, and to entering line number between PCIE bridging chips and arithmetic processor
Controlled according to the management with sequential, data is accurately transferred to specified address process and returning result；The code storage
Device is each for storing some arithmetic processors by 25 bit address buses and 16 bit data bus connection management control chips
From required data operation program, and some arithmetic processors are supplied under management control chip control；Some computings
Processor is connected with PCIE bridging chips, for each completing data operation according to the data operation program for receiving, and will fortune
Calculate result and server is transferred to by PCIE bridging chips；Some data storages are with some arithmetic processors one by one
Correspondence connection, for initial data, the storage of intermediate operations data and reading.
2. the high-speed reconfigurable data processing unit based on PLD according to claim 1, its feature exists
In, including six arithmetic processors and six data storages being connected one to one with six arithmetic processors.
3. the high-speed reconfigurable data processing unit based on PLD according to claim 1, its feature exists
In PEX8311 type bridging chip of the PCIE bridging chips from Avago company.
4. the high-speed reconfigurable data processing unit based on PLD according to claim 1, its feature exists
In the management control chip selects CPLD chips；The code memory selects FLASH storage chips.
5. according to the high-speed reconfigurable data processing unit based on PLD that one of Claims 1-4 is described, its
It is characterised by, the arithmetic processor selects fpga chip；The data storage is from synchronous static RAM.
6. a kind of high-speed reconfigurable data processing method based on PLD, it is characterised in that the method includes：
PCIE EBIs are converted into PCIE bridging chips the parallel bus interface of local 32；
Management control chip initialization arithmetic processor, and to carried out between PCIE bridging chips and arithmetic processor data and when
The management control of sequence, makes data accurately be transferred to specified address process and returning result；
Code memory stores each required data operation program of some arithmetic processors, and under management control chip control
It is supplied to some arithmetic processors；
Some arithmetic processors each complete data operation according to the data operation program for receiving, and operation result is passed through
PCIE bridging chips are transferred to server；
Some data storages connect one to one with some arithmetic processors, store and read initial data and middle fortune
Count evidence.
7. the high-speed reconfigurable data processing method based on PLD according to claim 6, its feature exists
In the method is using six arithmetic processors and six data storages connected one to one with six arithmetic processors.
8. the high-speed reconfigurable data processing method based on PLD according to claim 6, its feature exists
In PEX8311 type bridging chip of the PCIE bridging chips from Avago company.
9. the high-speed reconfigurable data processing method based on PLD according to claim 6, its feature exists
In the management control chip selects CPLD chips；The code memory selects FLASH storage chips.
10. according to the high-speed reconfigurable data processing method based on PLD that one of claim 6 to 9 is described,
Characterized in that, the arithmetic processor selects fpga chip；The data storage is from synchronous static random access memory
Device.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111433758A (en) * | 2018-11-21 | 2020-07-17 | 吴国盛 | Programmable operation and control chip, design method and device thereof |
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| CN101833534A (en) * | 2010-03-17 | 2010-09-15 | 无锡市同威科技有限公司 | FPGA (Field Programmable Gate Array) high-performance operating PCI (Peripheral Component Interconnect) card |
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