CN106796884A - Three port bit locations of the width with increase - Google Patents

Three port bit locations of the width with increase Download PDF

Info

Publication number
CN106796884A
CN106796884A CN201580044997.3A CN201580044997A CN106796884A CN 106796884 A CN106796884 A CN 106796884A CN 201580044997 A CN201580044997 A CN 201580044997A CN 106796884 A CN106796884 A CN 106796884A
Authority
CN
China
Prior art keywords
bit location
bitcell
institute
bit
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201580044997.3A
Other languages
Chinese (zh)
Other versions
CN106796884B (en
Inventor
N·N·莫江德
S·S·宋
Z·王
C·F·耶普
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN106796884A publication Critical patent/CN106796884A/en
Application granted granted Critical
Publication of CN106796884B publication Critical patent/CN106796884B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Abstract

A kind of device includes the first read port, the second read port, write port and at least one memory latch.The width of the bit location including the first read port, the second read port and write port is more than the twice of contact polycrystalline spacing (CPP) being associated with the bit location.For example, bit location can be three port static random access memory (SRAM) bit locations manufactured with self-aligned double patterning case (SADP) process compatible and the usable semiconductor fabrication process less than 14 nanometers (nm).

Description

Three port bit locations of the width with increase
Cross-Reference to Related Applications
This application claims jointly owned in the U.S. Non-provisional Patent application No.14/468 of submission on the 26th of August in 2014, 976 priority, the content of the patent application is all clearly included in this by quoting.
Field
The disclosure relates generally to bit location.
Description of Related Art
Technological progress has produced less and less and stronger and stronger computing device.For example, there is currently various Portable, personal computing device, including smaller, light weight and be easy to by user carry wireless computer device, such as portable mobile wireless Phone, personal digital assistant (PDA) and paging equipment.(the such as cell phone and internet more specifically, portable radiotelephone Agreement (IP) phone) voice-and-data can be passed on to be grouped by wireless network.Additionally, many such radio telephones include being included into In other kinds of equipment therein.For example, radio telephone may also include digital camera, DV, digital recorder with And audio file player.Equally, such radio telephone can process executable instruction, including can be used for accessing the soft of internet Part application, such as web browser application.In this way, these radio telephones may include significant computing capability.
Electronic equipment (such as radio telephone) may include comprising the memory array being made up of one or more memory cells The memory of row.The a type of memory cell that can be used for memory (for example, L1/L2 caches) is that three ports position is single Unit.Three port bit locations may include two read ports and a write port, and can be used for static RAM (SRAM) device.In 14 nanometers of (nm) complementary metal oxide semiconductors (CMOS) (CMOS) technologies, three port SRAM bit locations can lead to Cross the dual masks light using fin formula field effect transistor (FinFET) and two coverings of metal level (being referred to as M1 and M2 layers) Quarter-etching-photoetching-etching (LELE) technique is manufactured.Metal layer at top M2 can be patterned and may include by nonlinear way " concavo-convex (jog) " (for example, coil).For the manufacturing process (for example, 10nm or 7nm) less than 14nm, due to self-aligned double patterning The cost of the reduction that case (SADP) is provided compared with LELE and the process control of improvement are (for example, more accurate line width and line Separation control), SADP may be than LELE more preferably for forming M1 and M2.However, SADP may not support to include it is concavo-convex Non-linear pattern.Thus, the three port bit locations for 14nm manufactures may incompatible SADP.
It is also possible to propose other challenges from the reduction of 14nm technologies.For example, for 14nm and bigger technology node, three ports The width of bit location can be constrained to less than or equal to contact polycrystalline spacing (between CPP, i.e. contact polycrystalline (grid) line Distance) twice.For 14nm, CPP can be about 80-90nm.As used herein, unit " width " can be perpendicular to Polycrystalline direction and along fin direction.For the technology node less than 14nm, CPP is reduced, and this causes the bit location width for reducing.When When bit location width is reduced (that is, constriction), write word line and readout word line in bit location can also be narrowed down, so as to cause because of increase Word line resistance device-capacitor (RC) resistance and increased read/write stand-by period for causing.In addition, less bit location size The interval between the metal-metal through hole in bit location may be caused to reduce.Reduce as through hole to through hole is spaced, may become LELE (that is, dual masks) is more difficult with to pattern these through holes.As a result, it is possible to use the 3rd mask (that is, LELELE), This may increase the manufacturing cost of bit location.
General introduction
Present disclose provides including linearity pattern and bit location design therefore compatible with SADP, the SADP is such as used for small In the technology node (for example, 10nm or 7nm) of 14nm.According to the first technology, three port bit locations can have the twice more than CPP Width.The increase of bit location width can realize broader wordline in the bit location, this can by reduce wordline RC resistance come Reduce the read/write stand-by period.Can also be increased sufficiently to for the interval between metal-metal through hole to be covered with double by increase bit location width The distance of mould LELE process compatibles.Thus, the twice that bit location width is increased above CPP also may be such that metal-metal leads to The mask process that hole can be patterned and be added without introducing.
According to the second technology, three port bit locations may include two memory latch coupled to each other, wherein these latches The side of device is shorted.Two latch are coupled can increase to 4*CPP by the overall width of bit location from 2*CPP, this Be capable of achieving as described by the first technology benefit (for example, the linearity pattern compatible with SADP, broader wordline, increase Metal-metal through hole interval, etc.).Further, since two latch are included in each bit location, therefore each list Unit can have onboard data redundancy.
According to the 3rd technology, three port bit locations can be formed as described by the second technology.In addition, three ports position is single Two read ports of unit can be in the same side of bit location, rather than in the opposite side of bit location.Make two read ports in bit location The same side can reduce the length of bit location, so as to cause the total face than being occupied by the bit location of the first technology or the second technology The smaller gross area of product.
In a specific embodiment, a kind of device includes the first read port, the second read port, write port and at least one Memory latch.The width of the bit location including the first read port, the second read port and write port is more than related to the bit location The twice of contact polycrystalline spacing (CPP) of connection.
In another specific embodiment, a kind of bit location includes that the first read port, the second read port, write port, first are deposited Storage latch and the second memory latch.First side of the first memory latch is connected to the second storage by short circuit connection First side of latch.
In another specific embodiment, a kind of bit location includes that the first read port, the second read port, write port, first are deposited Storage latch and the second memory latch.First read port and the second read port are in the first memory latch and the second storage lock The same side of storage.
In another specific embodiment, a kind of bit location is included for reading the first device of data, for reading data Second device and the device for writing data.The bit location is also included for the first device of data storage and for depositing Store up the second device of data.The first side for the first device of data storage is connected to for storing number by short circuit connection According to second device the first side.
In another specific embodiment, a kind of method includes patterning position by self-aligned double patterning case (SADP) technique The first metal layer of unit.The bit location includes the first read port, the second read port and write port.The method also includes passing through SADP techniques pattern the second layer of the bit location.The width of the bit location is more than the two of the CPP being associated with the bit location Times.
In another specific embodiment, a kind of non-transient computer-readable media includes instruction, and the instruction is by computer The computer is set to perform operation during execution, the operation includes being patterned by SADP techniques the first metal layer of bit location.Should Bit location includes the first read port, the second read port and write port.The operation also includes patterning the position by SADP techniques The second layer of unit.The width of the bit location is more than the twice of the CPP being associated with the bit location.
The specific advantages provided by least one the disclosed embodiments are that three port bit locations have increase Width (for example, the twice more than CPP), does not have a non-linear pattern, and with less than 14nm (for example, 10nm or 7nm) place SADP semiconductor fabrication process is compatible.Another particular advantage is that including a pair of memory latch (wherein these memory latch In each memory latch side by short circuit connection come it is short-circuit) three port bit locations in onboard data redundancy.
Other aspects of the disclosure, advantages and features will be apparent from after whole application has been read, and whole application includes Sections below：Brief description, detailed description and claims.
Brief description
Figure 1A and Figure 1B are the circuit diagrams of the first illustrative embodiment of three port bit locations；
Fig. 2 is the first layout of the three port bit locations of Fig. 1；
Fig. 3 is the second layout of the three port bit locations of Fig. 1；
Fig. 4 A and Fig. 4 B are the circuit diagrams of the second illustrative embodiment of three port bit locations；
Fig. 5 depicts the layout of the three port bit locations of Fig. 4；
Fig. 6 A and Fig. 6 B are the circuit diagrams of the 3rd illustrative embodiment of three port bit locations；
Fig. 7 depicts the layout of the three port bit locations of Fig. 6；
Fig. 8 is the flow chart of the certain illustrative embodiments of the method to form three port bit locations；
Fig. 9 is the block diagram of the electronic equipment for including the three port bit locations of Fig. 1, Fig. 4 and/or Fig. 6；And
Figure 10 is that manufacture includes the specific of the manufacturing process of the electronic equipment of the three port bit locations of Fig. 1, Fig. 4 and/or Fig. 6 The DFD of illustrative embodiment.
Describe in detail
The specific embodiment of the disclosure described referring to the drawings.In this description and accompanying drawing, for describing and retouch The embodiment stated it is clear for the sake of, same characteristic features are specified by identical reference.
Reference picture 1A and 1B, show the circuit diagram of the first illustrative embodiment of bit location 100.Bit location 100 includes Memory latch 110.Memory latch 110 may include the phase inverter 112,114 of a pair of cross coupling.In phase inverter 112,114 Each may include p-type metal oxide semiconductor (MOS) field-effect transistor (PFET) and N-shaped MOS FET (NFET), such as Shown in Figure 1B.
Memory latch 110 can be connected (for example, coupling) to the first write transistor 121 and the second write transistor 122.Write crystalline substance Body pipe 121,122 can be NFET, as shown in the figure.First write transistor 121 may be connected to the first write bit line (WBL1) 135 and write Wordline (WWL) 137, and the second write transistor 122 may be connected to the second write bit line (WBL2) 136 and write word line (WWL) 137.The One write transistor 121 and the second write transistor 122 can be the complementary write transistors of the write port in bit location 100.When writing When a write bit line in line 137 and write bit line 135 or 136 is asserted, can be used the write port by logical zero (for example, It is low) value write-in memory latch 110.When another write bit line in write word line 137 and write bit line 135 or 136 is asserted, The write port can be used by logic 1 (for example, high) value write-in memory latch 110.
Memory latch 110 is also connected to the first reading driving transistor 123 and second and reads driving transistor 124.First Reading driving transistor 123 may be connected to the first reading transistor 125 and the second reading driving transistor 124 may be connected to the second reading crystal Pipe 126.It can be NFET to read driving transistor 123,124 and reading transistor 125,126, as shown in the figure.First reading transistor 125 May be connected to the first sense bit line (RBL1) 131 and the first readout word line (RWL1) 133.Second reading transistor 126 may be connected to second Sense bit line (RBL2) 132 and the second readout word line (RWL2) 134.Transistor 123 and 125 may correspond to the first reading of bit location 100 Port, and transistor 124 and 126 may correspond to the second read port of bit location 100.Readout word line 133 and/or 134 can read to grasp It is asserted during work and these read ports can be complementary read port.For example, the data value at the first read port is logical zero When, the data value at the second read port is logic 1, and vice versa.In the example of Figure 1B, the first read port (left side) is illustrated as Read logical zero value (" 0 ") and the second read port (right side) is illustrated as reading logic 1 (" 1 ") value.
Thus bit location 100 may include two read ports and a write port, and may be alternatively referred to as " three ports " Bit location.Because bit location 100 includes ten transistors, therefore bit location 100 is also referred to as " 10T " bit location.It is special one Determine in embodiment, bit location 100 is included in static RAM (SRAM) device and provides high-speed parallel and deposits Reservoir is accessed.SRAM device as the non-limiting example of illustrative, including bit location 100 can be used for the L1 of processor And/or L2 caches.The SRAM device may include one or more bit cell arrays arranged in the way of to be similar to grid, bag Include a line or many bitcells and one or more columns per page bit location.
As further described herein, bit location 100 can have height (H) and width (W).According to described skill Art, width (W) can be more than the twice of contact polycrystalline spacing (CPP) be associated with bit location 100, and wherein CPP is corresponding to connecing The distance between touch polycrystalline (grid) line.CPP may be alternatively referred to as grid spacing.For example, in 10nm semiconductor manufacturing works In skill (for example, the technique with 10nm minimum available line distance/feature sizes), CPP can be substantially equal to 60-66nm.For than Compared with purpose, the CPP for 14nm techniques (for example, the technique with 14nm minimum available line distance/feature sizes) can be about 80-90nm.In the prior art, bit location width can be constrained to less than or equal to 2*CPP.Conversely, the technology of the disclosure will The width of bit location 100 is increased above 2*CPP, is achieved in broader reading and write word line.As reference picture 2 is further described , wordline wider can be that bit location 100 provides the read/write stand-by period for reducing.The width of bit location 100 is increased above 2*CPP also may be such that the interval between metal-metal through hole can increase to and dual masks photoetching-etching-photoetching-etching (LELE) amount of process compatible, as reference picture 3 is further described.Dual masks LELE can be more less expensive than three mask LELELE, The technique that LELELE can be directed to less than 14nm is required when the width of bit location 100 is less than or equal to 2*CPP.It is less than The example of the technique of 14nm may include but be not limited to 10nm techniques and 7nm techniques.
Reference picture 2, shows the first layout of bit location 100 and is generally expressed as 200.Fig. 3 depicts position Second layout of unit 100 is simultaneously generally expressed as 300.Fig. 2 and 3 depicts two row of bit location, wherein each Bit location has the circuit layout shown in Figure 1A and 1B.During fabrication, bit location 100 may include various assemblies/layer, such as fin (including FinFET of source/drain regions), transistor gate (being alternatively referred to as polycrystalline line), for transistor source/drain electrode The middle part processing procedure contact in area --- MD (for example, local interlinkage), for middle part processing procedure contact --- the MP (examples of grid/polycrystalline line Such as, local interlinkage), the first metal layer (M1), the through hole (through hole 0) that MD and MP are connected to M1, second metal layer (M2) and M1 is connected to the through hole (through hole 1) of M2.Fig. 2 illustrates fin, polycrystalline line and M2.Thus, in fig. 2, CPP is from polycrystalline The edge of line to the corresponding edges for adjoining polycrystalline line distance (for example, top sides along to top sides along or bottom sides along to bottom Edge).Therefore CPP is also contemplated as being equal to a polycrystalline width and a polycrystalline interval sum.
As described with reference to fig. 1, when from 14nm technogenic migrations to 10nm techniques, for patterning bit location 100 SADP is probably preferred for all metal levels.Because SADP may be not suitable for concavo-convex/coil, the metal level of bit location 100 May correspond to only linearity pattern.When at 10nm using only linearity pattern, radical CPP reductions are maintained simultaneously can independent access Three wordline (2 readout word lines and 1 write word line) wordline width can be reduced.As the non-limiting example of illustrative, such as The width of fruit bit location is fixed as 2*CPP, then the write word line 137 of Fig. 1 can be for about 60-70nm wide and can be in 14nm situations It is for about 27nm wide in 10nm situations.The wordline width of reduction can increase resistor-capacitor circuit (RC) resistance of wordline, so as to cause The increased stand-by period.In fig. 2, it is longitudinal perpendicular to polycrystalline direction and along the bit location width in fin direction.Parallel to many Chip is horizontal to and perpendicular to the bit location height in fin direction.
When the technique less than 14nm is moved to, the width of bit location 100 is increased above 2* by described technology CPP.Thus, it is possible to increase the width of write word line 137 and/or readout word line 133,134.For example, in fig. 2, bit location width quilt The width for increasing to the substantially three times of CPP and write word line is substantially doubled to 55nm.The increase of line width of writing is reduced and write The RC resistance of wordline, thus reduces write latency and provides the performance of improvement.It should be noted that write line width and readout word line width Incrementss can be based on read the stand-by period relative to write latency expectation balance and change.For example, in crucial application is read, The readout word line width comparable line width that writes increases more.For writing crucial application, write word line width comparable readout word line width increases Plus it is more.For reading crucial and writing crucial application, the relative increase of line width of reading and write can be determined based on design requirement.
It shall yet further be noted that increasing to 3*CPP by by bit location width, the 10nm bit locations shown in Fig. 2 have and non-SADP The roughly the same width (3*CPP=3*60=180nm) of 14nm bit locations (2*CPP=2*90=180nm).However, due to from The change of 14nm to 10nm can also reduce fin spacing (for example, from 40-50nm to 30-35nm), by bit location 100 occupy it is total Area can be reduced.The reduction of bit cell area can provide the ability of the smaller storage component part of manufacture, and this is being included in In processor or to be tightly coupled into the situation of the on-chip memory of processor be probably what is be particularly desired in.In order to explain, In a specific embodiment, with 0.186 μm of the port bit locations of non-SADP 14nm tri-2Area compare, by position list at 10nm The areas that occupy of unit 100 can be about 0.130 square micron (μm2)。
It should be noted that the example that bit location width is increased to about 3*CPP is not to be regarded as limited.Implement replacing In example, bit location width can be increased to another amount (for example, 2.5*CPP, 2.75*CPP, 4*CPP etc.) more than 2*CPP.
Although SADP is probably preferred for all metal levels of bit location 100 are patterned in the technology less than 14nm , but for the through hole of these metal levels is connected for being formed LELE be probably it is preferred (for example, for cost it is related and/ Or the reason for technique correlation).However, the technique moved to less than 14nm may reduce the metal-metal through hole in bit location 100 Interval between (being such as connected to M2 layers of through hole (through hole 1) by M1 layers).Specifically, when bit location width is fixed as 2* During CPP, the interval between such through hole can be reduced to less than 40nm.Reduce and can prevent the double of these through holes in this through hole interval Color is decomposed.That is, dual masks LELE techniques may form these through holes without enough technology controlling and process or precision.As a result, may be used Three mask LELELE techniques can be needed to pattern these metal-metal through holes.Adding another mask may increase to bit location Significant manufacturing cost.2*CPP is increased above by by the width of bit location 100, the interval between metal-metal through hole can It is increased to the amount with dual masks LELE process compatibles.For example, when the width of bit location 100 is increased to 3*CPP, metal- Interval between metal throuth hole can be more than 60nm, (it illustrates M1, M2 and 1 layer of through hole) as shown in Figure 3.Thus, by position list The width of unit 100 is increased above 2*CPP can also reduce the manufacturing cost being associated with bit location 100.
Bit location 100 described by reference picture 1-3 thus can with for less than 14nm manufacturing process (for example, 10nm or SADP metal patterns 7nm) are compatible.In addition, bit location 100 can have the reading of increase and/or the line width that writes, this can be reduced Read and/or write latency.Additionally, bit location 100 can provide the interval that increases between metal-metal through hole and can be used for The dual masks LELE process compatibles that through hole is formed, cover for through hole the dual masks LELE techniques for being formed and three formed for through hole Mould LELELE techniques are compared and can reduce manufacturing cost.
Reference picture 4A and Fig. 4 B, shows the circuit diagram of the second illustrative embodiment of three port bit locations 400.Bit location 400 include the first memory latch 110, and also including the second memory latch 410 and the additional He of write transistor 421 422.The side of the first memory latch 110 is connected to the same side of the second memory latch 410 by short circuit connection 450.The One memory latch 110 is connected to the first read port and the second memory latch 410 is connected to the second read port, wherein these readings Port in the opposite side of bit location 400, as shown in the figure.
In a specific embodiment, as shown in the bottom of Fig. 4 A, bit location 400 can have the width of 4*CPP, and it is more than 2* CPP.Thus, similar to bit location 100, bit location 400 can be with the SADP patternings for metal level and for metal-metal The dual masks LELE patternings of through hole are compatible.The height of bit location 400 can 21.5 times of substantially fin spacing.For 10nm works Skill, fin spacing can be 30-35nm.In a specific embodiment, the area for being occupied by bit location 400 can be about 0.181 μ m2。
Note, bit location 400 provides the digital independent of complementation.For example, as shown in Figure 4 B, when the first read port (left side) is read When taking logical zero value, the second read port (right side) reads logic 1 and is worth.In addition, by including two memory latch 110,410 with And by the side short circuit of these memory latch, bit location 400 has onboard data redundancy.If for example, the strong value of logic 1 can not The left side (for example, due to process variations) of the first memory latch 110 is written into, be then worth still can be due to the short circuit/friendship for strong logic 1 Fork coupled motions and be present in the left side of the second memory latch 410.
Reference picture 5, shows including four layouts of the 2x2 arrays of bit location, wherein every in this four bit locations One has the circuit layout of bit location 400.As described by reference picture 2-3, bit location may include various assemblies/layer, such as Fin, polycrystalline grid, MD, MP, M1, through hole 0, M2 and through hole 1.For the sake of clarity and be easy to explain, shown for phase in Fig. 5 With three kinds of layouts 510,520 and 530 of 2x2 arrays.Each of layout 510,520 and 530 depicts fin (in Fig. 5 It is middle longitudinally to be patterned) and polycrystalline grid (lateral patterning in Figure 5).It is (horizontal that first layout 510 depicts MD in addition To patterning) and MP (by longitudinally patterning) layer, each of which layer is below M1 layers.Second layout 520 depicts M1 in addition (by longitudinally patterning) and through hole 0 (dark square) layer.3rd layout 530 depicts M1 (by longitudinally patterning), M2 (quilts in addition It is lateral patterning) and through hole 1 (shallow square) layer.In a specific embodiment, MD and/or MP layers is can be used to pattern short circuit even Connect 450.
Reference picture 4-5 description bit location 400 thus can with for less than 14nm manufacturing process (for example, 10nm or SADP metal patterns 7nm) are compatible, it is possible to provide the reading of reduction and/or write latency, and can with formed for through hole Dual masks LELE is compatible.Bit location 400 may also provide onboard data redundancy, and this can improve bit location 400 to process variations Tolerance limit.
Reference picture 6A and Fig. 6 B, shows the circuit diagram of the 3rd illustrative embodiment of three port bit locations 600.Similar to Bit location 400, bit location 600 includes the first memory latch 110 and the second memory latch 410, wherein the first storage is latched First (for example, right) side of device 110 is connected to first (for example, right) of the second memory latch 410 by short circuit connection 450 Side.It is contrasted with bit location 400, in bit location 600, the first read port and the second read port are relative with the first side Two (for example, left) sides, as indicated by 620.
In a specific embodiment, as shown in the bottom of Fig. 6 A, bit location 600 can have the width of 4*CPP, and it is more than 2* CPP.Thus, similar to bit location 100 and bit location 400, bit location 600 can be with the SADP patternings and use for metal level Patterned in the dual masks LELE of metal-metal through hole compatible.The height of bit location 600 can 15.5 times of substantially fin spacing. For 10nm techniques, fin spacing can be 30-35nm.In a specific embodiment, the area for being occupied by bit location 600 can be About 0.139 μm2, it is less than the area of bit location 100 and less than the area of bit location 400 at 10nm.
Note, different from bit location 100 and bit location 400, bit location 600 does not provide complementary data reading.For example, as schemed Shown in 6B, when the first read port (left side) reads logical zero value, the second read port (right side) also reads logical zero value.Thus, wrap The memory architecture (for example, sensing amplifier, driver, Memory Controller etc.) for including the device of bit location 600 may differ from The memory architecture of the device including bit location 100 or bit location 400.In addition, similar to bit location 400, bit location 600 has Onboard data redundancy.
Reference picture 7, shows including four layouts of the 2x2 arrays of bit location, wherein each in these bit locations Person has the circuit of bit location 600.For the sake of clarity and be easy to explain, three kinds for identical 2x2 arrays are shown in Fig. 7 Layout 710,720 and 730.Each of layout 710,720 and 730 depicts fin (longitudinally being patterned in the figure 7) With polycrystalline grid (lateral patterning in the figure 7).First layout 710 depicts MD (lateral patterning) and MP in addition (by longitudinally patterning) layer, each of which layer is below M1 layers.Second layout 720 depicts M1 in addition (by vertically patterning) With through hole 0 (dark square) layer.3rd layout 730 depict in addition M1 (by longitudinally patterning), M2 (lateral patterning) and Through hole 1 (shallow square) layer.In a specific embodiment, MD and/or MP layers is can be used to pattern short circuit connection 450.
Bit location 600 thus can be with the SADP metal patterns for the manufacturing process (for example, 10nm or 7nm) less than 14nm Change compatible, it is possible to provide the reading of reduction and/or write latency, and can be compatible with the dual masks LELE formed for through hole.Position Unit 600 may also provide onboard data redundancy, and this can improve tolerance limit of the bit location 600 to process variations.Additionally, bit location 600 are smaller than bit location 100 and bit location 400, and this can provide when the semiconductor fabrication process less than 14nm is moved to and change The scaling for entering.
Reference picture 8, shows the flow chart of the certain illustrative embodiments of the method 800 to form bit location and its is general Be denoted as 800.In an illustrative embodiment, method 800 all or part of can bit location 100, bit location 400 or Performed during the manufacture of bit location 600.
Method 800 may include the fin (source/drain regions) and polycrystalline line (grid) in 802 patterning bit locations.This list Unit may include the first read port, the second read port, write port and at least one memory latch.The width of the bit location can be big In the twice of the CPP being associated with the bit location.Method 800 may additionally include the source/drain of the 804 patterning bit locations Middle part processing procedure contact (for example, local interlinkage) (for example, MD layers) and the middle part processing procedure contact (for example, local interlinkage) of polycrystalline line (for example, MP layers).In a specific embodiment, patterning middle part processing procedure contact may include to form short circuit connection 806.The short circuit The side of the first memory latch of the bit location can be connected to the same side of the second memory latch of the bit location for connection. For example, when the bit location is bit location 400 or bit location 600, short circuit connection 450 may be formed in MD and/or MP layers.So And, when the bit location is bit location 100, short circuit connection (i.e., it is possible to not performing method and step 806) can not be formed.
Method 800 can be further included in 808 the first metal layers (M1) that the bit location is patterned by SADP techniques, The metal-metal through hole (through hole 1) of the bit location is patterned using dual masks LELE techniques 810, and is passed through 812 SADP techniques pattern the second metal layer (M2) of the bit location.For example, the M1 and M2 layers each can be without non-linear figure Case simultaneously thus can be compatible with SADP, as described with reference to Figure 2.Additionally, the interval between metal-metal through hole (through hole 1) can With dual masks LELE process compatibles, as described with respect to figure 3.Increased bit location width also may be such that through hole 0 be spaced with it is double Mask LELE process compatibles.
It should be noted that the step of being explained in Fig. 8 order is only used for illustrative purpose and is not qualified as limited.Replacing In alternative embodiment, some steps can in different order be performed and/or can held by concurrent (or at least partially concurrent) OK.
Method 800 can (such as CPU (CPU), controller, another hardware device, firmware set by processing unit Standby or its any combinations) realize.As an example, method 800 can be performed by the processor of execute instruction, such as reference picture 10 Described.
Reference picture 9, depicts the block diagram of the certain illustrative embodiments of a kind of electronic equipment and is generally expressed as 900.Electronic equipment 900 includes being coupled to the processor 910 of memory 932, such as digital signal processor (DSP) or centre Reason unit (CPU).Processor 910 include SRAM device 964, wherein the SRAM device include bit location 100, bit location 400 and/ Or bit location 600.For example, SRAM device 964 may correspond to L1 and/or L2 cache memories.In an illustrative embodiment In, the bit location of SRAM device 964 can be manufactured according to all or part of of the method 800 of Fig. 8.In an alternative embodiment In, SRAM device 964 can be in the outside of processor 910 and/or coupled to processor 910.Although it should be noted that Fig. 9 is illustrated in spy Determine to use bit location 100, bit location 400 and/or bit location 600 in the SRAM of electronic equipment, but this is not qualified as limiting Property.Bit location (such as bit location 100, bit location 400 and/or bit location 600) according to the disclosure can be included in any In any kind of memory of the electronic equipment of type.
Fig. 9 shows the display controller 926 coupled to processor 910 and display 928.Encoder/decoder (CODEC) 934 it is also coupled to processor 910.Loudspeaker 936 and microphone 938 can be coupled to CODEC 934.Fig. 9 also indicates nothing Lane controller 940 can be coupled to processor 910 and antenna 942.In a specific embodiment, processor 910, display controller 926th, memory 932, CODEC 934 and wireless controller 940 are included in system in package or system-on-chip apparatus (example Such as, mobile station modems (MSM)) in 922.In a specific embodiment, input equipment 930 and power supply 944 are coupled to piece Upper system equipment 922.Additionally, in a specific embodiment, as shown in Figure 9 in the commentary, display 928, input equipment 930, raise Sound device 936, microphone 938, antenna 942 and power supply 944 are outside system-on-chip apparatus 922.However, display 928, input equipment 930th, each of loudspeaker 936, microphone 938, antenna 942 and power supply 944 can be coupled to the group of system-on-chip apparatus 922 Part, such as interface or controller.
With reference to described embodiment, a kind of bit location is included for reading the first device of data, for reading data Second device, the device for writing data and at least one device for data storage.For example, for reading data First device may include the first read port (for example, it include transistor 123, transistor 125, the first sense bit line 131 and/or First readout word line 133), be configured to support bit location in read operation one or more other devices or its any combinations.With May include the second read port (for example, it includes transistor 124, transistor 126, the second read bit in the second device for reading data The readout word line 134 of line 132 and/or second), be configured to support bit location on read operation one or more other devices or its Any combinations.Device for writing data may include write port (for example, it includes transistor 121, transistor 122, transistor 421st, transistor 422, write word line 137), be configured to support bit location in write operation one or more other devices or its Any combinations.At least one device for data storage may include memory latch 110, memory latch 410, be configured to deposit Store up one or more other devices or its any combinations of data.In a specific embodiment, the width of the bit location be more than with The twice of associated contact polycrystalline spacing (CPP) of the bit location.In a specific embodiment, for the first of data storage First side of device is connected to first (that is, same) side of the second device for data storage by short circuit connection.For example, Short circuit connection can be the short circuit connection 450 of Fig. 4 or Fig. 6.In a specific embodiment, for reading the first device of data With the second device for reading data in the same side of at least one device for data storage.For example, such as Fig. 6 institutes Show, the two read ports can be in the same side of bit location 600.In an alternative embodiment, the first dress for reading data Put and for reading the second device of data in the opposite side of at least one device for data storage.For example, such as Fig. 1 and Shown in Fig. 4, the two read ports can be in bit location 100 and the opposite side of bit location 400.
Above-disclosed device and feature can be designed and configured in the computer being stored on computer-readable medium In file (for example, RTL, GDSII, GERBER etc.).Some or all this class files are provided to be made based on this class file Make the manufacture treatment people of device.The product that result is obtained includes semiconductor wafer, and it is then cut into semiconductor element simultaneously It is packaged into semiconductor chip.These chips can be deployed in electronic equipment.Figure 10 depicts electronic equipment manufacturing process 1000 certain illustrative embodiments.For example, manufacturing process 1000 can be used to manufacture including bit location 100, bit location 400 And/or the electronic equipment of bit location 600.
At manufacturing process 1000 physical device information 1002 is received (such as at research computer 1006).Physical device Information 1002 may include the design letter of at least one physical property for representing bit location 100, bit location 400 and/or bit location 600 Breath.For example, physical device information 1002 may include the thing being input into via the user interface 1004 for being coupled to research computer 1006 Reason parameter, material property and structural information.Research computer 1006 is included coupled to computer-readable medium (for example, non-wink State computer-readable medium) (such as memory 1010) processor 1008, such as one or more process cores.Memory 1010 Computer-readable instruction can be stored, it can be performed so that physical device information 1002 is converted into following file by processor 1008 Form simultaneously generates library file 1012.
In a specific embodiment, library file 1012 includes that at least one includes the data text of converted design information Part.For example, library file 1012 may include to be provided to and bit location storehouse associated with electric design automation (EDA) instrument 1020 (including bit location 100, bit location 400 and/or bit location 600).
Library file 1012 can be used to design a calculating machine cooperateed with eda tool 1020 at 1014, and design a calculating machine 1014 bags Include the processor 1016 for being coupled to memory 1018, such as one or more process cores.Eda tool 1020 can be stored as storage Processor-executable instruction at device 1018, with enable to design a calculating machine 1014 user design library file 1012 including position The circuit of unit 100, bit location 400 and/or bit location 600.For example, 1014 user of designing a calculating machine can set via being coupled to The user interface 1024 for counting computer 1014 carrys out input circuit design information 1022.Circuit-design information 1022 may include to represent position The design information of at least one physical property of unit 100, bit location 400 and/or bit location 600.In order to explain, circuit design Property may include particular electrical circuit mark and with the relation of other elements in circuit design, location information, characteristic size information, The other information of the physical property of interconnection information or expression bit location 100, bit location 400 and/or bit location 600.
Designing a calculating machine 1014, to can be configured to conversion designs information (including circuit-design information 1022) a certain to follow File format.In order to explain, this document form may include with hierarchy type form represent the plane geometric shape on circuit layout, The database binary file format of text mark and other information, such as graphic data system (GDSII) file format.If Meter computer 1014 can be configured to generation includes the data file of converted design information, such as including description bit location 100th, the GDSII file 1026 of the information and other circuits or information of bit location 400 and/or bit location 600.In order to explain, Data file may include to correspond to be included the on-chip system (SOC) of bit location 100, bit location 400 and/or bit location 600 and goes back Including additional electronic circuit and the information of component in SOC.
GDSII file 1026 can be received with the converted letter in GDSII file 1026 at manufacturing process 1028 Cease to manufacture bit location 100, bit location 400 and/or bit location 600.For example, device manufacturing processes may include GDSII file 1026 are supplied to mask manufacturer 1030 to create one or more masks, such as mask associated with photoetching treatment, its It is explained as representative mask 1032.Mask 1032 can be used to generate one or more chips 1033 during manufacturing process, Chip 1033 can be tested and be divided into tube core, such as representative tube core 1036.Tube core 1036 includes the circuit comprising device, should Device includes bit location 100, bit location 400 and/or bit location 600.
For example, manufacturing process 1028 may include processor 1034 and memory 1035 to initiate and/or control manufacturing process 1028.Memory 1035 may include executable instruction, such as computer-readable instruction or processor readable instruction.These can perform Instruction may include one or more instructions that can be performed by computer (such as processor 1034).In a specific embodiment, this A little executable instructions can make computer perform Fig. 8 method 800 or its at least partially.
Manufacturing process 1028 can be realized by the manufacture system of full-automatic or partial automation.For example, manufacturing process 1028 can automate according to scheduling.Manufacture system may include for performing one or more operations to form semiconductor devices Manufacturing equipment (for example, handling implement).For example, manufacturing equipment is configured to chemical vapor deposition (CVD) and/or thing Physical vapor deposition (PVD) deposits one or more material, using single mask or many mask lithography-etch process (for example, double cover Mould LELE) carry out patterning materials, carry out patterning materials using photoetching-freeze-photoetching-etching (LFLE) technique, use autoregistration Double patterning (SADP) technique carrys out patterning materials, and one or more material of epitaxial growth conformally deposits one or more material Material, applies hard mask, applies etching mask, performs etching, performs planarization, forms dummy gate electrode stacking, forms gate stack, The type of execution standard 1 cleaning, etc..In a specific embodiment, manufacturing process 1028 corresponds to and the technology node less than 14nm (for example, 10nm, 7nm etc.) associated semiconductor fabrication.For manufacturing device (for example, it includes bit location 100, position Unit 400 and/or bit location 600) concrete technology or process combination can be based on design constraint and available material/equipment.Thus, In a particular embodiment, the technique described different from reference picture 1-10 can be used during the manufacture of device.
As illustrative example, used during the through hole 1 of bit location 100, bit location 400 and/or bit location 600 is formed Dual masks LELE techniques may include using the first photoresist mask on the ground floor (for example, nitride layer) of device Form the first pattern of the first pattern and etching.The second mask is may then use that to form the second pattern and can on the device Second lower level (for example, oxide skin(coating)) of combination pattern to the device is etched downwards.In combination pattern, the first pattern and The feature (for example, line) of two patterns can interweave.Thus the combination pattern can have compared with first pattern and the second pattern Small feature (for example, line) spacing.
As another illustrative example, for pattern bit location 100, the M1 of bit location 400 and/or bit location 600 or M2 layers of SADP techniques may include to form " illusory " pattern on device.Conformal dielectric layer can be formed (for example, deposition) at this In dummy pattern and can be etched.During etching, the whole of the dielectric layer can be removed, except adjoining the dummy pattern The dielectric material " wall " of side wall.The dummy pattern (for example, without etching) can be then removed, so as to leave wall, this The pattern with feature (for example, line) density higher than the dummy pattern can be formed.Higher density interval layer pattern can It is used to M1 or M2 layers of patterning.
Manufacture system (for example, performing the automated system of manufacturing process 1028) can have distributed structure/architecture (for example, layering Structure).For example, the manufacture system may include one or more processors (the such as processor being distributed according to the distributed structure/architecture 1034), one or more memories (such as memory 1035), and/or controller.The distributed structure/architecture may include to control or send out Play the advanced processor of the operation of one or more low-level systems.For example, the superordinate part of manufacturing process 1028 may include one Or multiple processors (such as processor 1034), and low-level system can each include one or more corresponding controllers or can receive Its control.The specific controller of specific low-level system can receive one or more instructions (for example, order) from specific AS, To Subordinate module or handling implement issue subcommand, and can pass on status data to the specific AS in turn.One Each low-level system in individual or multiple low-level systems can be related to one or more corresponding manufacturing equipments (for example, handling implement) Connection.In a specific embodiment, the manufacture system may include the multiple processors being distributed in the manufacture system.For example, rudimentary The controller of system component may include processor, such as processor 1034.
Alternatively, processor 1034 can be a part for AS, subsystem or the component of the manufacture system. In another embodiment, processor 1034 includes the distributed treatment at the various grades and component of manufacture system.
The executable instruction being included in memory 1035 may be such that processor 1034 can form (or initiating to be formed) position Unit 100, bit location 400 and/or bit location 600.In a specific embodiment, memory 1035 is that storage computer can perform The non-transient computer-readable media of instruction, the computer executable instructions can be performed by processor 1034 so that processor 1034 Initiate to form device according at least a portion of the method for Fig. 8.For example, these computer executable instructions can be performed so that Processor 1034 initiates to form bit location 100, bit location 400 and/or bit location 600.As illustrative example, processor 1034 Can initiate or control figure 8 method 800 one or more steps.
Tube core 1036 is provided to encapsulation process 1038, and wherein tube core 1036 is included into representative encapsulation 1040. For example, encapsulation 1040 may include singulated dies 1036 or multiple tube cores, such as system in package (SiP) is arranged.Encapsulation 1040 can It is configured to follow one or more standard or specifications, such as joint electron device engineering council (JEDEC) standard.
Information on encapsulation 1040 can be distributed to each product designer (such as via storage at computer 1046 Component Gallery).Computer 1046 may include to be coupled to the processor 1048 of memory 1050, such as one or more process cores.Print Printed circuit board (PCB) instrument can be stored at memory 1050 as processor-executable instruction, connect via user with processing The PCB design informations 1042 that mouth 1044 is received from the user of computer 1046.PCB design information 1042 may include to encapsulate semiconductor Device physical positioning information on circuit boards, bit location 100, position is included with 1040 corresponding encapsulation semiconductor devices of encapsulation Unit 400 and/or bit location 600.
Computer 1046 can be configured to conversion PCB design information 1042 to generate data file, such as with including envelope The data of dress semiconductor devices physical positioning information on circuit boards and the layout of electrical connection (trace and through hole) etc. GERBER file 1052, wherein encapsulation semiconductor devices correspond to include bit location 100, bit location 400 and/or bit location 600 encapsulation 1040.In other embodiments, the data file for being generated by converted PCB design information can have to be removed Form beyond GERBER forms.
GERBER file 1052 can be received and used to create according to GERBER file at plate assembling process 1054 The design information of 1052 memory storages is come the PCB, such as representativeness PCB 1056 that manufacture.For example, GERBER file 1052 can be gone up One or more machines are passed to perform each step of PCB production processes.PCB 1056 can filled with electronic building brick (including envelope Fill 1040) to form representative printed circuit assembly (PCA) 1058.
PCA 1058 can be received at manufacture course of products 1060 and PCA 1058 is integrated into one or more electronics and set In standby (such as the first representative electronic device 1062 and the second representative electronic device 1064).For example, the first representative electronics Equipment 1062, the second representative electronic device 1064 or both may include or corresponding to the electronic equipment 900 or its group of Fig. 9 Part, such as SRAM device 964.The non-limiting example as illustrative, the first representative electronic device 1062, second is representative Electronic equipment 1064 or both may include communication equipment, fixed position data cell, mobile position data unit, mobile electricity Words, cell phone, satellite phone, computer, tablet device, portable computer or desktop computer.As replacement or benefit Fill, the first representative electronic device 1062, the second representative electronic device 1064 or both may include wherein to be integrated with position list The Set Top Box of unit 100, bit location 400 and/or bit location 600, amusement unit, navigation equipment, personal digital assistant (PDA), prison Visual organ, computer monitor, television set, tuner, radio, satelline radio, music player, digital music player, Portable music player, video player, video frequency player, digital video disc (DVD) player, portable digital are regarded Any other equipment or its combination of frequency player, storage or retrieval data or computer instruction.As another illustrative rather than One or more of limited example, electronic equipment 1062 and 1064 may include remote unit (such as mobile phone), hand-held Formula PCS Personal Communications System (PCS) unit, portable data units (such as personal digital assistant), enable global positioning system (GPS) equipment, navigation equipment, fixed position data cell (such as meter reading equipment) or storage or retrieval data or Any other equipment or its any combinations of computer instruction.Although Figure 10 illustrates the long-range list of the teaching according to the disclosure Unit, but the disclosure is not limited to the unit that these are explained.Embodiment of the disclosure can suitably be used in includes thering is memory In any equipment of the active integrated circuit system of on-chip circuit system.
Device including bit location 100, bit location 400 and/or bit location 600 can be such as the institute in illustrative process 1000 In being manufactured as description, processed and bringing electronic equipment into.One or more on Fig. 1-10 the disclosed embodiments Aspect can be included in each processing stage, such as be included in library file 1012, GDSII file 1026 (for example, having The file of GDS II format) and GERBER file 1052 (for example, the file with GERBER forms) in, and be stored in Study computer 1006 memory 1010, design a calculating machine 1014 memory 1018, the memory 1050 of computer 1046, In one or more other computers or processor (not shown) that each stage (such as at plate assembling process 1054) uses Memory at, and also be included into one or more other physical embodiments, such as mask 1032, tube core 1036, envelope Fill 1040, PCA 1058, other products (such as prototype circuit or equipment (not shown)) or its any combinations.Although depicting Each representative production phase of final products is designed into from physical device, but less rank can be used in other embodiments Section may include additional phase.Similarly, the one of each stage that process 1000 can be by single entity or by implementation procedure 1000 Individual or multiple entities are performed.
Although one or more of Fig. 1-10 may illustrate system, device, and/or the side of the teaching according to the disclosure Method, but the disclosure is not limited to system, device, and/or the method that these are explained.The presently disclosed embodiments can be used suitably In any equipment including IC system (including memory, processor and on-chip circuit system).
Although one or more of Fig. 1-10 may illustrate system, device, and/or the side of the teaching according to the disclosure Method, but the disclosure is not limited to system, device, and/or the method that these are explained.In Fig. 1-10 any one as herein explain Or the one or more functions or component of description can be combined with one or more other parts of another one in Fig. 1-10.Accordingly Ground, any single embodiment described herein is all not interpreted as limited, and the presently disclosed embodiments The teaching that can be appropriately combined without deviating from the disclosure.
Technical staff will further appreciate that, the various illustrative boxes that are described with reference to presently disclosed embodiment, Configuration, module, circuit and algorithm steps can be implemented as electronic hardware, by the computer software of computing device or both Combination.Various illustrative components, frame, configuration, module, circuit and step are made above in its functional form Vague generalization is described.Such feature is implemented as hardware or processor-executable instruction depends on concrete application and is added to The design constraint of total system.Technical staff can by different way realize described feature for every kind of application-specific, But it is such to realize that decision-making is not to be read as causing a departure from the scope of the present disclosure.
The method or each step of algorithm described with reference to presently disclosed embodiment can directly with hardware, by processor be held Capable software module or combination of the two are realized.Software module can reside in random access memory (RAM), flash memory, only Read memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable formula can Program read-only memory (EEPROM), register, hard disk, removable disk, compact disk read-only storage (CD-ROM) or this area In known any other form non-transitory storage media in.Exemplary storage medium is coupled to processor so that the treatment Device can be from/to the storage medium reading writing information.In alternative, storage medium can be integrated into processor.Processor and Storage medium can reside in application specific integrated circuit (ASIC).ASIC can reside in computing device or user terminal.Replacing In scheme, during processor and storage medium can reside in computing device or user terminal as discrete assembly.
Description before offer to the disclosed embodiments is in order that those skilled in the art can all make or use institute Disclosed embodiment.Various modifications to these embodiments will be apparent to those skilled in the art, and The principle being defined herein can be applied to other embodiment without departing from the scope of the present disclosure.Therefore, the disclosure not purport Being defined to embodiments shown herein, but should be awarded and principle and novelty as defined by the accompanying claims The consistent most wide possible range of feature.

Claims (20)

1. a kind of device, including：
First read port；
Second read port；
Write port；And
At least one memory latch,
Including first read port, second read port and the write port bit location width be more than with it is described The twice of associated contact polycrystalline spacing (CPP) of bit location.
2. device as claimed in claim 1, it is characterised in that institute's bitcell is to use the semiconductor less than 14 nanometers (nm) Manufacturing process is manufactured.
3. device as claimed in claim 2, it is characterised in that the semiconductor fabrication process includes 10nm techniques.
4. device as claimed in claim 2, it is characterised in that the semiconductor fabrication process includes 7nm techniques.
5. device as claimed in claim 1, it is characterised in that institute's bitcell includes the first metal layer.
6. device as claimed in claim 5, it is characterised in that the first metal layer does not include non-linear pattern.
7. device as claimed in claim 5, it is characterised in that institute's bitcell includes being formed in the first metal layer top Second metal layer, wherein the second layer not include non-linear pattern.
8. device as claimed in claim 7, it is characterised in that the first metal layer and the second metal layer be using from Double patterning (SADP) technique is directed to pattern.
9. device as claimed in claim 7, it is characterised in that further include：
The first metal layer is connected to the first through hole of the second metal layer；And
The first metal layer is connected to the second through hole of the second metal layer,
Interval and dual masks photoetching-etching-photoetching-etching (LELE) between wherein described first through hole and second through hole Process compatible.
10. device as claimed in claim 9, it is characterised in that the interval is more than 60 nanometers (nm).
11. devices as claimed in claim 1, it is characterised in that the width of institute's bitcell is more than or equal to and institute's rheme list Three times of the associated CPP of unit.
12. devices as claimed in claim 1, it is characterised in that the CPP being associated with institute bitcell is about 60- 66nm。
13. devices as claimed in claim 1, it is characterised in that institute's bitcell is deposited including the first memory latch and second Storage latch, wherein the first side of first memory latch is connected to second memory latch by short circuit connection The first side.
14. devices as claimed in claim 13, it is characterised in that first read port and second read port are described Second side of the first memory latch and second memory latch, wherein second side is relative with first side.
A kind of 15. bit locations, including：
First device for reading data；
Second device for reading data；
Device for writing data；
For the first device of data storage；And
For the second device of data storage,
First side of the wherein described first device for data storage is connected to described for storing number by short circuit connection According to second device the first side.
16. bit locations as claimed in claim 15, it is characterised in that the first device for reading data and the use In read data second device in the first device for data storage and the second device for data storage The second side, wherein second side is relative with first side.
17. bit locations as claimed in claim 15, it is characterised in that the width of institute's bitcell is more than and institute's bitcell phase The twice of contact polycrystalline spacing (CPP) of association.
A kind of 18. methods, including：
The first metal layer of bit location is patterned by self-aligned double patterning case (SADP) technique, wherein the bit location includes First read port, the second read port and write port；And
By the second layer of SADP techniques bitcell to pattern,
Twice of the width of wherein described bit location more than contact polycrystalline spacing (CPP) being associated with institute bitcell.
19. methods as claimed in claim 18, it is characterised in that further include to be latched in the first storage of institute's bitcell Short circuit connection is formed between second memory latch of device and institute's bitcell.
20. methods as claimed in claim 18, it is characterised in that institute's bitcell is included in static RAM (SRAM) in device.
CN201580044997.3A 2014-08-26 2015-07-23 The three port bit locations with increased width Expired - Fee Related CN106796884B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/468,976 US9536596B2 (en) 2014-08-26 2014-08-26 Three-port bit cell having increased width
US14/468,976 2014-08-26
PCT/US2015/041818 WO2016032645A1 (en) 2014-08-26 2015-07-23 Three-port bit cell having increased width

Publications (2)

Publication Number Publication Date
CN106796884A true CN106796884A (en) 2017-05-31
CN106796884B CN106796884B (en) 2018-06-12

Family

ID=53777022

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580044997.3A Expired - Fee Related CN106796884B (en) 2014-08-26 2015-07-23 The three port bit locations with increased width

Country Status (3)

Country Link
US (1) US9536596B2 (en)
CN (1) CN106796884B (en)
WO (1) WO2016032645A1 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9449667B2 (en) * 2014-03-31 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit having shared word line
US9558811B1 (en) * 2014-09-02 2017-01-31 Marvell International Ltd. Disturb-proof static RAM cells
US9524972B2 (en) 2015-02-12 2016-12-20 Qualcomm Incorporated Metal layers for a three-port bit cell
US9691775B1 (en) * 2016-04-28 2017-06-27 Globalfoundries Inc. Combined SADP fins for semiconductor devices and methods of making the same
US10340288B2 (en) * 2016-08-02 2019-07-02 Globalfoundries Inc. Method, apparatus, and system for improved memory cell design having unidirectional layout using self-aligned double patterning
KR102633138B1 (en) 2016-10-17 2024-02-02 삼성전자주식회사 Integrated Circuit and Semiconductor Device
CN112216323A (en) * 2017-09-04 2021-01-12 华为技术有限公司 Memory cell and static random access memory
US10573528B2 (en) 2017-12-14 2020-02-25 Tessera, Inc. Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic
US11088151B2 (en) * 2019-10-01 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. 4Cpp SRAM cell and array
US11398274B2 (en) 2020-08-25 2022-07-26 Qualcomm Incorporated Pseudo-triple-port SRAM
US11302388B2 (en) 2020-08-25 2022-04-12 Qualcomm Incorporated Decoding for pseudo-triple-port SRAM
US11251123B1 (en) 2020-08-25 2022-02-15 Qualcomm Incorporated Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines, and related methods
US11361817B2 (en) 2020-08-25 2022-06-14 Qualcomm Incorporated Pseudo-triple-port SRAM bitcell architecture
US11955169B2 (en) * 2021-03-23 2024-04-09 Qualcomm Incorporated High-speed multi-port memory supporting collision
US20220415378A1 (en) * 2021-06-25 2022-12-29 Advanced Micro Devices, Inc. Split read port latch array bit cell

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100136784A1 (en) * 2008-12-01 2010-06-03 Applied Materials, Inc. Self aligned double patterning flow with non-sacrificial features
CN103106917A (en) * 2011-11-10 2013-05-15 台湾积体电路制造股份有限公司 Semiconductor manufacturing method
US20140024220A1 (en) * 2012-07-20 2014-01-23 Chih-Yang Chang Method of fabricating an ultra low-k dielectric self-aligned via
CN103928048A (en) * 2013-01-14 2014-07-16 飞思卡尔半导体公司 Multiport Memory With Matching Address And Data Line Control

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4873665A (en) * 1988-06-07 1989-10-10 Dallas Semiconductor Corporation Dual storage cell memory including data transfer circuits
US5424996A (en) * 1992-09-29 1995-06-13 Hewlett-Packard Company Dual transparent latch
US6091627A (en) 1998-09-16 2000-07-18 Lucent Technologies, Inc. Message box memory cell for two-side asynchronous access
US6133098A (en) 1999-05-17 2000-10-17 Halo Lsi Design & Device Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic flash memory
JP4885365B2 (en) * 2000-05-16 2012-02-29 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4171201B2 (en) 2001-10-23 2008-10-22 松下電器産業株式会社 Semiconductor memory device
US6778419B2 (en) * 2002-03-29 2004-08-17 International Business Machines Corporation Complementary two transistor ROM cell
US7324377B2 (en) 2004-10-29 2008-01-29 Macronix International Co., Ltd. Apparatus and method for programming and erasing virtual ground EEPROM without disturbing adjacent cells
US7826282B2 (en) 2006-02-21 2010-11-02 Mentor Graphics Corporation Random access memory for use in an emulation environment
JP5078338B2 (en) 2006-12-12 2012-11-21 ルネサスエレクトロニクス株式会社 Semiconductor memory device
JP5362198B2 (en) 2007-08-31 2013-12-11 ルネサスエレクトロニクス株式会社 Semiconductor device
US7856613B1 (en) 2008-01-30 2010-12-21 Cadence Design Systems, Inc. Method for self-aligned doubled patterning lithography
US8680671B2 (en) 2009-01-28 2014-03-25 Spansion Llc Self-aligned double patterning for memory and other microelectronic devices
US8654568B2 (en) 2009-08-24 2014-02-18 Texas Instruments Incorporated 10T SRAM cell with near dual port functionality
US8339893B2 (en) * 2009-09-25 2012-12-25 International Business Machines Corporation Dual beta ratio SRAM
US8174868B2 (en) * 2009-09-30 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded SRAM structure and chip
US8675397B2 (en) * 2010-06-25 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Cell structure for dual-port SRAM
JP5226094B2 (en) 2011-02-23 2013-07-03 株式会社半導体理工学研究センター Semiconductor memory device
US8755218B2 (en) * 2011-05-31 2014-06-17 Altera Corporation Multiport memory element circuitry
US8625334B2 (en) 2011-12-16 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell
US8728940B2 (en) 2012-01-26 2014-05-20 Micron Technology, Inc. Memory arrays and methods of forming same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100136784A1 (en) * 2008-12-01 2010-06-03 Applied Materials, Inc. Self aligned double patterning flow with non-sacrificial features
CN103106917A (en) * 2011-11-10 2013-05-15 台湾积体电路制造股份有限公司 Semiconductor manufacturing method
US20140024220A1 (en) * 2012-07-20 2014-01-23 Chih-Yang Chang Method of fabricating an ultra low-k dielectric self-aligned via
CN103928048A (en) * 2013-01-14 2014-07-16 飞思卡尔半导体公司 Multiport Memory With Matching Address And Data Line Control

Also Published As

Publication number Publication date
US9536596B2 (en) 2017-01-03
WO2016032645A1 (en) 2016-03-03
CN106796884B (en) 2018-06-12
US20160064067A1 (en) 2016-03-03

Similar Documents

Publication Publication Date Title
CN106796884B (en) The three port bit locations with increased width
US10141317B2 (en) Metal layers for a three-port bit cell
CN107004438B (en) The 3 port bit cell arrays with the shared first and second global readout word lines and global write word line in same metal layer
CN105637589B (en) The SRAM read buffers of sensing delay and improved sensing surplus with reduction
CN107771348B (en) Bit cell with shared bit line
CN105518788B (en) System and method for providing reference unit
US10621300B2 (en) Computing system for performing colorless routing for quadruple patterning lithography
CN107004680A (en) FinFET SRAM with bundling type contact
CN106463165A (en) Dual write wordline sram cell
CN105185406A (en) Multi-port Non-volatile Memory That Includes A Resistive Memory Element
CN107690700A (en) Mediator for package-on-package structure
US20160233159A1 (en) Integrated circuit device including multiple via connectors and a metal structure having a ladder shape
US20170338215A1 (en) Heterogeneous cell array
US9379014B1 (en) Static random-access memory (SRAM) array

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180612

Termination date: 20210723

CF01 Termination of patent right due to non-payment of annual fee