CN1067834C - Adaptive equalizer having tap coefficient self adaption separated with data correcting hardware - Google Patents

Abstract

The present invention relates to an adaptive equalizer with tapping coefficient adaptation separated from data correction hardware. The adaptive equalizer is composed of a digital signal processor (DSP), a first transverse filter and a second transverse filter, wherein the DSP is used for adaptive filtering; the transverse filters are used for high-speed transverse filtering; the DSP and the transverse filters combine to an equalizer in HDTV.

Description

The adaptive equalizer that tap coefficient self adaption separates with data correcting hardware

The present invention relates to a kind of adaptive equalizer, relate more specifically to the adaptive equalizer that a kind of tap coefficient self adaption separates with data correcting hardware.

Equalizer hardware in high definition TV (HDTV) receiver requires very high.Because signal code stream speed fast (sign indicating number speed is 13.31MHz) prolongs when paying the footpath, so equalizer needs a lot of tap node.As pair footpath that tackles 10 μ S just needs 133 grades equalizer.The equalizer that in the past was used for microwave communication mostly is the 5-6 level, and the equalizer progression that is used for telephone channel Modem is 20 multistage, so the equalizer hardware scale is unprecedented among the HDTV.The amplitude of paying the footpath in the HDTV wireless transmission channel changed with the 0.9Hz cycle, and it is adaptive requiring equalizer, and convergence rate is very fast.

Equalizer adopts the structure of transversal filter usually, as shown in Figure 1.X (t) is an input signal, and Y (t) is an output signal.Transversal filter postpones input signal, multiply by coefficient Ci, adds up and just obtain output signal again.Ci constant or only when starting, insert be called fixed filters, Ci is with the sef-adapting filter that is called of each input signal X (t) self adaptation adjustment.

Equalizer must be a sef-adapting filter among the HDTV, but allows Ci with each input signal X (t) self adaptation adjustment, and hardware can't be realized.The method of dealing with problems is: use an adaptive equalizer at a slow speed to regulate transversal filter tap coefficient Ci specially; Use fixed lateral filter at a high speed to calculate Y (t).The coefficient Ci of high-speed fixed transversal filter can insert again, just inserts once again after a while, thereby makes " fixed lateral filter " become adaptive transversal filter.

Recently, people have realized that: to a baroque hardware system, using the middle and small scale general-purpose device is to be difficult to realize.Usually, realize that equalizer has only three kinds of schemes among the HDTV:

1. dedicated digital signal processor (DSP) is realized.

2. ultra-large field programmable gate array (FPGA) is realized.

3. ultra-large application-specific integrated circuit (ASIC) (ASIC) is realized.

With our existing condition, it is very difficult that the equalizer of 100 more pieces implements.The speed of equalizer input signal is 13.3M/S among the HDTV, and promptly the equalizer per second must be handled the signal of 13.3M sampled point.To adaptive equalizer, when DSP realized, the every node of every sampled point will be carried out three instruction cycles.Therefore, if each node uses a digital signal processor (DSP) to realize that the command speed of digital signal processor (DSP) also will reach 13.3M * 3=39.9M/S.This almost is the maximum speed that current digital signal processor (DSP) can reach.Even but using the fastest digital signal processor (DSP), the equalizer of 100 multinodes also wants more than 100 digital signal processor (DSP) just can finish.This obviously is actual infeasible.

It is the hard-wired preferred plan of complication system all the time that ASIC realizes, but the huge downpayment development stage that is dropped in the function model machine can not bear.Have only the scheme of FPGA possible feasible.

A preliminary design shows: 100,000 gate devices of altera corp's maximum-norm can be realized the sef-adapting filter of 16 joint left and right sides 8bit precision.The FPGA of altera corp has a kind of new design, can realize a lot of joint transversal filters with less gate circuit.But this transversal filter is not adaptive.Realize adaptive transversal filter, the efficient of the gate circuit of FPGA is not very high.The scheme of FPGA realization equalizer will be used 6-8 sheet 100,000 gate devices.100,000 gate devices are very huge, cost an arm and a leg, and only use a slice in the common system, and therefore, the scheme of FPGA is also infeasible when specific implementation.

The adaptive equalizer that will provide a kind of cost low is provided.

The adaptive equalizer that separates with data correcting hardware according to tap coefficient self adaption of the present invention, it comprises a digital signal processor (DSP) of carrying out adaptive-filtering, and first transversal filter and second transversal filter composition of carrying out at a high speed horizontal filtering; It is characterized in that: digital signal processor (DSP) has a data input, it takes out synchronizing signal from the data of input, calculate the tap coefficient of 128 nodes of equalizer, deliver to the coefficient input of first and second transversal filters by its coefficient output respectively; Digital signal processor (DSP) also provide control word by the control output end to horizontal filter, so that control the operating state of first and second transversal filters; First transversal filter is subjected to input data from the outside by its DI0 termination, and outside input data are delayed through 64 grades in first transversal filter, by its SR end output, delivers to the DI0 input of second transversal filter of cascade; Add up after the input data of the node delay of each transversal filter and node tap coefficient multiply each other, the result is by the output of DO end; The output of first and second transversal filters is by an adder addition, so that obtain balanced output result.

Adaptive equalizer according to above-mentioned tap coefficient self adaption of the present invention separates with data correcting hardware is further characterized in that; Said digital signal processor (DSP) is a TMS320C31 chip; Said first and second transversal filters are the L64240 chip.

Fig. 1 is the schematic diagram of equalizer that adopts the structure of transversal filter.

Fig. 2 is the schematic diagram that constitutes equalizer with dedicated digital signal processor (DSP) or ultra-large field programmable gate array (FPGA).

Fig. 3 shows the structure of transversal filter (L64240).

Fig. 4 shows the signal code stream among the HDTV.

Fig. 5 is the schematic diagram of the adaptive equalizer that separates with data correcting hardware of tap coefficient self adaption of the present invention.

Fig. 6 is the circuit diagram of the equalizer of the FIR type (linear feedforward) as the first embodiment of the present invention.

Fig. 7 is the circuit diagram as the equalizer of the DFE type (decision-feedback) of the second embodiment of the present invention.

Fig. 8 is the principle assumption diagram as the equalizer of the DFE type (decision-feedback) of the second embodiment of the present invention.

Below in conjunction with accompanying drawing most preferred embodiment of the present invention is described in detail.

All restrictions when considering the realization of equalizer in high definition TV (HDTV) the function model machine, we have to rethink the use general-purpose device, but must be ultra-large general-purpose devices.The L64240 chip that U.S. LSI Logic company produces is a kind of transversal filter of special use, operating frequency 16～20MHz, and when precision was 8Bit, a slice can realize the transversal filter of 64 nodes, and is largest in all optional devices.Use two L64240 cascades can realize the transversal filter of 128 joints.L64240 is not a sef-adapting filter, but filter coefficient can be in operation and insert again, after a while can update coefficients.The structure that Fig. 3 has drawn transversal filter (L64240).DI0～DI7 is an input signal, and during as the one-dimensional filtering device, only with the DI0 input, DI1～DI7 is no empty pin, and equalizer promptly is this situation among the HDTV.DO is output.

The TMS320C31 chip that U.S. Texas Instrument company produces is one of the fastest digital signal processor of arithmetic speed (DSP).The structure of the similar CPU of digital signal processor (DSP) can plug-in EPROM coding.Its feature is a flexible function, and function is determined by software behind the construction system.Digital signal processor (DSP) TMS320C31 can constitute sef-adapting filter, but filter speed is nothing like transversal filter (L64240) soon.

Use a slice digital signal processor (DSP) TMS320C31 to make adaptive-filtering, the coefficient that obtains just offers transversal filter (L64240) after a while.The filter of this spline structure has the performance of sef-adapting filter, and it can regulate the filter section dot factor adaptively according to the variation of channel.Therefore its shortcoming is that coefficient will just be regulated once after a while, is difficult to adaptive channel change fast, but the channel variation that pace of change is no more than coefficient update speed is had good adaptability.

Digital signal processor (DSP) can not be finished adaptive-filtering in real time, and therefore the sub-fraction that can only choose in the channel code stream is done adaptive-filtering.Digital signal processor (DSP) is handled the sub-fraction signal of this similar sampling, obtains filter coefficient, is applied to signals all in the channel.Obviously, the channel code stream of this " sampling " must suitably be chosen.

In digital HDTV signal, some signal is the synchronizing signal of the information of not carrying.Because this part signal is known reference signal at receiving terminal, therefore be particularly suitable as " sampling " of channel code stream, offer digital signal processor (DSP) and make adaptive-filtering computing node coefficient.Signal code stream as shown in Figure 4 among the HDTV.

Synchronous and the field synchronization of the synchronizing signal section of having.Segment sync signal has only 4 symbols at every turn, relatively disperses, and is difficult for utilizing.Field sync signal has continuous more than 800, so the selected scenes synchronizing signal makes adaptive-filtering for digital signal processor (DSP).

Field sync signal occurs once every about 20ms, so the every 20ms of coefficient upgrades once.This structure not can do with the channel variation faster than 20ms, and this is generally no problem in HDTV.If the quick variation of adaptive channel can be used segment sync signal.Use suitable step-length, use the LMS algorithm, tens sampled points just can have little adjusting by envoy's dot factor.And the synchronously per 60 μ S of section occur once, and within 100-200 μ S, coefficient just can be finished little adjustment.

The structure of the adaptive equalizer that tap coefficient self adaption of the present invention separates with data correcting hardware as shown in Figure 5.It is by a digital signal processor (DSP) TMS320C31, and first transversal filter (L64240) and second transversal filter (L64240) are formed.Transversal filter (L64240) and digital signal processor (DSP) TMS320C31 respectively have advantage, and the former can realize horizontal filtering at a high speed, and the latter can realize adaptive-filtering.Both respectively finish a kind of function of adaptive equalizer among the HDTV, combine the equalizer that could realize among the HDTV.Digital signal processor (DSP) TMS320C31 takes out synchronizing signal from the data of input, calculates the tap coefficient of 128 nodes of equalizer, delivers to the coefficient input of first and second transversal filters (L64240) respectively.Digital signal processor (DSP) TMS320C31 is also controlling the operating state of first and second transversal filters (L64240), and transversal filter (L64240) control word promptly is provided.First transversal filter (L64240) is accepted the input data from the outside, by its DI0 end input.Outside input data through 64 grades of time-delays, by its SR end output, are delivered to the DI0 input of second transversal filter (L64240) of cascade in first transversal filter (L64240).Add up after the input data of the node delay of each each transversal filter (L64240) and node tap coefficient multiply each other (referring to Fig. 3), the result has promptly finished horizontal filtering by the output of DO end.The output of first and second transversal filters (L64240) promptly obtains the output result of equalizer of the present invention after by an adder addition, and said adder can be a ready-made adder in second transversal filter (L64240).

The realization of the equalizer of embodiment 1 FIR type (linear feedforward)

Transversal filter (L64240) a slice can be finished the 8bit precision, the horizontal filtering of 64 nodes.Because transversal filter (L64240) itself has been considered the multi-disc cascade and has been constituted the problem of bigger filter, finished longer FIR filter so transversal filter (L64240) can cascade up very naturally.The side circuit debugging shows: two transversal filters (L64240) cascade is formed the FIR filter of one 128 joint except overall delay increases a clock cycle, without any other difficulties.The FIR circuit of 128 joints as shown in Figure 6.Left-hand digit signal processor (DSP) TMS320C31 provides coefficient and control word all nodes to two transversal filters (L64240) among the figure.Digital signal processor (DSP) TMS320C31 itself is actually a sef-adapting filter at a slow speed.Two transversal filters in the right (L64240) constitute 128 grades high speed transversal filter.The method of two transversal filters (L64240) cascade is: first SR meets second DI, and first DO meets second PR, and first DI is total input, and second DO is total output.Connection is fairly simple.

The equalizer that 128 joint finite impulse response filters (FIR) constitute generally can satisfy the requirement of HDTV function model machine.If more performance, the equalizer that use IIR (infinite impulse response) filter to constitute.

The realization of the equalizer of embodiment 2 DFE types (decision-feedback)

Infinite impulse response filter (IIR) does not resemble stable convergence always the finite impulse response filter (FIR), so iir filter generally can not make equalizer separately and use, and must use together with the FIR filter.Usually in the feedback loop of IIR, add decision circuit, constitute DFF (DFE).Computer Simulation is told us, have again in the filter of feedback fraction in existing feedforward part, if the length of feedback fraction less than the feedforward part, then performance is bad.In the U.S. Major Leagues schemes (GA), the equalizer feedforward section is divided into 64 joints, and feedback fraction is 192 joints.The condition that is limited to us realizes with digital signal processor (DSP) and transversal filter (L64240).With two transversal filters (L64240), 31 grades long of feedforward filtering parts, 96 grades of feedback filtering parts are long.

For such DFE equalizer, digital signal processor (DSP) part is as broad as long with the FIR equalizer.Choose synchronizing signal and make adaptive-filtering for digital signal processor (DSP), the coefficient that obtains offers transversal filter (L64240).And transversal filter (L64240) cascade constitutes long filter, then designs some problem when constituting IIR originally for FIR.

Iir filter has the operation of decision-feedback, i.e. the output of filter will feed back to the input of filter.Transversal filter (L64240) uses the operation of parallel pipelining process, output signal has time delay, a slice transversal filter (L64240) signal is exported the time delay that 3 clock cycle are arranged from being input to, and two transversal filters (L64240) cascade then has the time delay of 4 clock cycle.So, the problem of iir filter is exactly: when two transversal filters (L64240) constituted IIR, the feedback end of filter can not get feedback signal in 4 clock cycle, and the feedback signal that obtains is before 4 clock cycle.

The circuit of the equalizer of the DFE type (decision-feedback) that two transversal filters (L64240) cascade is constituted as shown in Figure 7, its equivalent filter theory structure is as shown in Figure 8.Through debugging, the test of analysis and side circuit for a long time, we find that finally this problem is not very serious problem.The problem of this IIR is: preceding 4 node coefficients of its feedback fraction are zero, i.e. b ₁=b ₂=b ₃=b ₄=0, (this place is blank among Fig. 8, does not take advantage of, adds circuit).This can reduce the performance of filter, but owing to there is FIR, performance reduces and be little.

According to U.S. GA scheme HDTV function prototyping testing result, HDTV channel worst case is:

1. a pair footpath amplitude peak of prolonging (0.18 μ S) in short-term can reach to be led directly-2dB (0.8 times).

2. pair footpath amplitude peak of long delay (3.2 μ S) can reach main footpath-6dB (0.5 times).

3. most strong footpath time delays of paying are no more than 10 μ S.

4. significantly pay the footpath, reach main footpath-10dB (0.3 times), in short and the long time interval, exist.

5. the footpath of paying that becomes the time often has.Can measure fast-changing pair of footpath, its amplitude and phase place changed with the cycle of about 0.9Hz.But the variation of its phase place is not 360 degree, but 180 degree.

In theory, the thresholding signal to noise ratio of vsb receiver is 14.9dB, and in fact, signal to noise ratio could receive more than will reaching 16dB.Channel distortion can equally with Gaussian noise be analyzed the influence of receiver sometimes with Fu Jing etc.Here we think, as long as reach certain value through the ratio S/NI of signal after balanced and interference, balanced just success.The thresholding signal to noise ratio of considering vsb receiver is 16dB, and S/NI＞20dB is enough.Computer Simulation shows that FIR equalizer S/NI when time delay 3.2 μ S, amplitude 0.5 and time delay 10 μ S, amplitude 0.3 of 128 joints is also a little bit poorer, and all the other situations can both meet the demands.32 grades FIR adds 96 grades IIR then except not can do with the paying the footpath (maximum delay that 96 grades of IIR can do with is 7.2 μ S) of time delay 10 μ S, and the equal better performances of other situation can meet the demands.And the situation of time delay 3.2 μ S, amplitude 0.5 and time delay 10 μ S, amplitude 0.3 is the worst case of channel, and the actual probability that reaches this situation is very little.

Pay the footpath signal and change a week in 0.9 second, and the every 20mS of the structural coefficient of our digital signal processor (DSP)+transversal filter (L64240) upgrades once.Circuit actual measurement shows: pay the footpath from zero and pay the footpath to First Officer footpath or from First Officer footpath to zero, as long as through two sync sections, coefficient has just been finished adaptive variation.Promptly the maximum to channel changes, as long as the 40mS time system just can be adjusted and finish.Pay 1/10th of footpath transformation period because system's adjustment time is about, can think roughly that system self-adaption speed gets caught up in channel variation speed.

In a word, use isolating construction, greatly the hardware circuit of simplified equalization device is realized from not becoming possibility the hardware of equalizer.Theory analysis, Computer Simulation and side circuit test shows, the equalizer performance of isolating construction is the same substantially with the adaptive equalizer of the complete data of traditional structure good.

Claims (3)

1, the adaptive equalizer that a kind of tap coefficient self adaption separates with data correcting hardware, it comprises a digital signal processor (DSP) of carrying out adaptive-filtering, and first transversal filter and second transversal filter composition of carrying out at a high speed horizontal filtering; It is characterized in that: digital signal processor (DSP) has a data input, it takes out synchronizing signal from the data of input, calculate the tap coefficient of 128 nodes of equalizer, deliver to the coefficient input of first and second transversal filters by its coefficient output respectively; Digital signal processor (DSP) also provide control word by the control output end to horizontal filter, so that control the operating state of first and second transversal filters; First transversal filter is subjected to input data from the outside by its DI0 termination, and outside input data are delayed through 64 grades in first transversal filter, by its SR end output, delivers to the DI0 input of second transversal filter of cascade; Add up after the input data of the node delay of each transversal filter and node tap coefficient multiply each other, the result is by the output of DO end; The output of first and second transversal filters is by an adder addition, so that obtain balanced output result.

2, the adaptive equalizer according to the tap coefficient self adaption of claim 1 separates with data correcting hardware is characterized in that; Said adder can be an adder ready-made in second transversal filter.

3, the adaptive equalizer according to the tap coefficient self adaption of claim 1 separates with data correcting hardware is characterized in that; Said digital signal processor (DSP) is a TMS320C31 chip; Said first and second transversal filters are the L64240 chip.

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