CN106776466A - A kind of FPGA isomeries speed-up computation apparatus and system - Google Patents
A kind of FPGA isomeries speed-up computation apparatus and system Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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Abstract
The invention discloses a kind of FPGA isomeries speed-up computation apparatus and system, including fpga chip, interface and the GMM counting circuits that are arranged on fpga chip, wherein, GMM counting circuits, for realizing GMM algorithms；Fpga chip, for the pending data sent by interface host side after startup, and is processed pending data by GMM counting circuits, result is obtained, so that host side obtains result by interface.With the GMM counting circuits for realizing GMM algorithms be combined fpga chip by the present invention, fpga chip realizes the treatment to pending data after the pending data that Receiving Host end sends by GMM counting circuits, the processing speed to data can be accelerated, treatment can obtain performance higher when especially processing big data, and process cycle is shorter.
Description
Technical field
The present invention relates to big data processing technology field, more particularly to a kind of FPGA isomeries speed-up computation device.This hair
It is bright to further relate to a kind of FPGA isomeries speed-up computation system.
Background technology
Spark is the universal parallel framework of the class Hadoop MapReduce that UC Berkeley AMP lab are increased income, energy
Preferably it is applied to the algorithm that data mining and machine learning etc. need the MapReduce of iteration, can be used to build large-scale, low
The data analysis application program of delay.Spark as Computational frame, for the various applications in upper strata provide service.MLlib is Spark
Machine learning storehouse, be one of core component of Spark, performance, power consumption of MLlib machine learning etc. index are directed not only to
The value of big data processing system, and directly affect the task scheduling and management and data throughput of big data processing platform
Rate.GMM (Gaussian Mixture Model, Gaussian Mixture cluster) algorithm is weight in the machine learning storehouse in big data treatment
Want clustering algorithm, thus carry GMM algorithms realize speed be conducive to improve MLlib machine learning performance.
Carrying out being mainly by server (such as CPU) to realize GMM algorithms when big data is processed in the prior art.One
As in the case of, CPU needs to receive a plurality of instruction in processing data, and perform successively after the instruction of each bar could complete paired data
Treatment, when mass data is processed, CPU is accomplished by receiving and performing more instructions completing the treatment to mass data, causes
Realize there is relatively low performance boundary when GMM algorithms are realized by CPU.
Therefore, how to provide a kind of FPGA isomery speed-up computations apparatus and system for solving above-mentioned technical problem turns into ability
The technical staff in domain needs the problem for solving at present.
The content of the invention
It is an object of the invention to provide a kind of FPGA isomeries speed-up computation device, can be obtained when processing big data
Performance higher, process cycle is shorter；It is a further object of the present invention to provide a kind of including above-mentioned FPGA isomeries speed-up computation dress
The system put, it processes when processing big data and can obtain performance higher, and process cycle is shorter.
In order to solve the above technical problems, the invention provides a kind of FPGA isomeries speed-up computation device, described device includes
Fpga chip, interface and the GMM counting circuits being arranged on the fpga chip, wherein：
The GMM counting circuits, for realizing GMM algorithms；
The fpga chip, for the pending data sent by the interface host side after startup, and is passed through
The GMM counting circuits are processed the pending data, obtain result, so that the host side is connect by described
Mouth obtains the result.
Preferably, described device also includes onboard storage device, for receiving and cache the host side send described in treat
Processing data；And for storing the result；
Then the process of the pending data that the corresponding fpga chip Receiving Host end sends is specially：Obtain the plate
Carry the pending data in memory.
Preferably, the GMM counting circuits include：
The computing sub-circuit of symmetrical matrix order 1, for receiving the pending data, the pending data is n element
The vector of composition, logical operation is carried out according to computing formula to the pending data, obtains the weights of current iteration computing, institute
Computing formula is stated for A:=alpha*x*x**T+A, wherein, alpha is given real number scalar；X is pending data, and x**T is x
Transposition, A be n*n symmetrical matrixes；It is additionally operable to terminate computing according to the first control instruction；
GMM right value update sub-circuits, for by the power of the new right value update of grey iterative generation each time last time grey iterative generation
Value；It is additionally operable to terminate to update according to the second control instruction；
Iteration control sub-circuit, for generating and sending first control instruction and institute when computing meets pre-conditioned
State the second control instruction.
Preferably, it is pre-conditioned for operation times reach the first preset value.
Preferably, it is pre-conditioned for the weights that computing is obtained are less than the second preset value.
Preferably, the onboard storage device is DDR3 memories or DDR4 memories.
Preferably, the interface is PCIE interfaces.
Preferably, the FPGA isomery speed-up computation devices as described in above-mentioned any one, the FPGA isomeries speed-up computation
Device is the device for extending cassette design.
In order to solve the above technical problems, the invention provides a kind of FPGA isomeries speed-up computation system, the system includes
Host side and the FPGA isomery speed-up computation devices as described in above-mentioned any one, the FPGA isomeries speed-up computation device pass through
Interface in the device is connected with the host side.
Preferably, the host side includes data transmission management module, for obtaining pending data, and is treated described in judgement
Whether processing data has been buffered in the onboard storage device of the FPGA isomeries speed-up computation device, if it is, not sending described
Pending data, otherwise, sends the pending data.
Preferably, it is described to judge the plate whether pending data has been buffered in the FPGA isomeries speed-up computation device
The process carried in memory is specially：
The numbering of the pending data is obtained, and to judge whether the numbering has preserved in the database, such as
Fruit is that then the pending data has been buffered in the onboard storage device of the FPGA isomeries speed-up computation device, otherwise, described
Pending data is uncached in the onboard storage device of the FPGA isomeries speed-up computation device.
The invention provides a kind of FPGA isomeries speed-up computation apparatus and system, including fpga chip, interface and it is arranged at
GMM counting circuits on fpga chip；GMM counting circuits, for realizing GMM algorithms；Fpga chip, for passing through to connect after startup
The pending data that mouth Receiving Host end sends, and pending data is processed by GMM counting circuits, obtain treatment knot
Really；Interface, is additionally operable to host side and obtains result by the interface.The present invention is by fpga chip and the GMM for realizing GMM algorithms
Counting circuit is combined, and it is right that fpga chip is realized after the pending data that Receiving Host end sends by GMM counting circuits
The treatment of pending data, can accelerate the processing speed to data, when especially processing big data treatment can obtain compared with
Performance high, process cycle is shorter.
Brief description of the drawings
Technical scheme in order to illustrate more clearly the embodiments of the present invention, below will be to institute in prior art and embodiment
The accompanying drawing for needing to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also obtain according to these accompanying drawings
Obtain other accompanying drawings.
A kind of structural representation of FPGA isomeries speed-up computation device that Fig. 1 is provided for the present invention.
Specific embodiment
Core of the invention is to provide a kind of FPGA isomeries speed-up computation device, and when processing big data, treatment can
Performance higher is obtained, process cycle is shorter；Another core of the invention is to provide a kind of including above-mentioned FPGA isomeries accelerometer
The system for calculating device, it processes when processing big data and can obtain performance higher, and process cycle is shorter.
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
Refer to Fig. 1, a kind of structural representation of FPGA isomeries speed-up computation device that Fig. 1 is provided for the present invention.
The device includes fpga chip 1, interface 2 and the GMM counting circuits 11 being arranged on fpga chip 1, wherein：
GMM counting circuits 11, for realizing GMM algorithms；
Fpga chip 1, for the pending data sent by the Receiving Host end of interface 2 after startup, and is calculated by GMM
Circuit 11 is processed pending data, obtains result, so that host side obtains result by interface 2.
In simple terms, FPGA isomery speed-up computations device provided herein passes through interface 2 (hardware interface) and main frame
End connection, and Receiving Host end sends pending data, pending data process obtains result, host side passes through
Interface 2 in the device obtains result.Specifically, the fpga chip 1 in FPGA isomery speed-up computation devices is the device
Core calculations part, GMM counting circuits 11 are provided with fpga chip 1, GMM algorithms can be realized by GMM counting circuits 11.
It should be noted that the circuit connecting form of the circuit can be preset when setting.
Used as preferred, interface 2 is PCIE interfaces.
It should be noted that the interface 2 can also select other kinds of interface, the present invention does not do special limit herein
It is fixed, the purpose of the present invention can be realized.
Used as preferred, the device also includes onboard storage device 3, for receiving and caches the pending number of host side transmission
According to；And for storing result；
Then the process of the pending data that the Receiving Host end of corresponding fpga chip 1 sends is specially：Obtain onboard storage
Pending data in device 3.
It should be noted that also including onboard storage device 3 in FPGA isomery speed-up computation devices, the memory will be received
The pending data that sends of host side cached, so as to fpga chip 1 when data processing is carried out directly from onboard storage
Pending data is obtained in device 3, with time-consuming.Certainly, data processing finishes rear fpga chip 1 and sends to plate result
Carry memory 3 in preserved, when host side need obtain result when by obtained from onboard storage device 3.
Specifically, host side regularly can obtain result by interface 2 from onboard storage device 3, can also connect
The END instruction aft engine end for receiving the transmission of fpga chip 1 obtains result by interface 2 from onboard storage device 3, certainly
Result can also be under other conditions obtained, the present invention does not do special restriction, can realize the purpose of the present invention i.e. herein
Can.
Used as preferred, onboard storage device 3 is DDR3 memories or DDR4 memories.
Certainly, onboard storage device 3 is not limited only to above two memory, can also select other kinds of memory, this
Special restriction is not done in invention herein, can realize the purpose of the present invention.
Used as preferred, GMM counting circuits 11 include：
The computing sub-circuit 111 of symmetrical matrix order 1, for receiving pending data, pending data is what n element was constituted
Vector, logical operation is carried out according to computing formula to pending data, obtains the weights of current iteration computing, and computing formula is A:
=alpha*x*x**T+A, wherein, alpha is given real number scalar；X is pending data, and x**T is the transposition of x, and A is n*n
Symmetrical matrix；It is additionally operable to terminate computing according to the first control instruction；
GMM right value updates sub-circuit 112, for by the new right value update of grey iterative generation each time last time grey iterative generation
Weights；It is additionally operable to terminate to update according to the second control instruction；
Iteration control sub-circuit 113, for generating and sending the first control instruction and when computing meets pre-conditioned
Two control instructions.
It is pre-conditioned for operation times reach the first preset value as preferred.
It should be noted that iteration control sub-circuit 113 mainly carries out judging whether to terminate computing according to pre-conditioned,
When operation times reach the first preset value, it is symmetrical to control that iteration control sub-circuit 113 generates corresponding first control instruction
1 computing sub-circuit of rank of matrix 111 terminates computing, generates corresponding second control instruction to control GMM right value updates sub-circuit 112
Terminate the action of right value update；Here the first preset value can artificially be set, its concrete numerical value according to actual conditions and
Demand is determined.
It is pre-conditioned for the weights that computing is obtained are less than the second preset value as preferred.
Specifically, iteration control sub-circuit 113 according to whether operation times reach the first preset value except that can judge
Whether terminate can also be by being obtained according to computing outside computing weights whether judge whether to terminate less than the second preset value
Computing, i.e., when the weights that computing is obtained are less than the second preset value, iteration control sub-circuit 113 generates corresponding first control and refers to
Make controlling 1 computing sub-circuit of symmetrical matrix order 111 to terminate computing, generate corresponding second control instruction to control GMM weights
Update the action that sub-circuit 112 terminates right value update；Here the second preset value is likelihood score, is set one of GMM algorithms
Parameter.
Used as preferred, as described above FPGA isomery speed-up computation devices, FPGA isomery speed-up computations device is expansion
The device of exhibition cassette design.
It should be noted that the design form of FPGA isomery speed-up computation devices is gone back mainly using the design of extension cassette
Can be designed using integrated type, such as together with other integrated chips.It can certainly be the dress of other design forms
Put, the present invention does not do particular determination herein, can realize the purpose of the present invention.
The invention provides a kind of FPGA isomeries speed-up computation device, including fpga chip, interface and it is arranged at FPGA cores
GMM counting circuits on piece, wherein：GMM counting circuits, for realizing GMM algorithms；Fpga chip, for passing through to connect after startup
The pending data that mouth Receiving Host end sends, and pending data is processed by GMM counting circuits, obtain treatment knot
Really, so that host side obtains result by interface.The present invention is by fpga chip and the GMM counting circuits for realizing GMM algorithms
It is combined, fpga chip is realized to pending number after the pending data that Receiving Host end sends by GMM counting circuits
According to treatment, the processing speed to data can be accelerated, when especially processing big data treatment can obtain performance higher,
Process cycle is shorter.
It is corresponding with said apparatus embodiment, the invention provides a kind of FPGA isomeries speed-up computation system, system bag
Host side and the FPGA isomery speed-up computation devices as described in above-mentioned embodiment are included, FPGA isomery speed-up computation devices are by the dress
Interface 2 in putting is connected with host side.
The method that FPGA isomeries speed-up computation system provided by the present invention is used when GMM algorithms are realized with it is above-mentioned
The method that FPGA isomery speed-up computation devices are used is identical, is specifically referred to above-mentioned to FPGA isomery speed-up computation devices
Describe in detail, the present invention will not be repeated here.
Used as preferred, host side includes data transmission management module, for obtaining pending data, and judges pending
Whether data have been buffered in the onboard storage device 3 of FPGA isomery speed-up computation devices, if it is, pending data is not sent,
Otherwise, pending data is sent.
It should be noted that the data transmission management module of host side is obtained after the instruction for receiving upper layer application transmission
Pending data, and by pending data by the interface 2 in FPGA isomery speed-up computation devices for being connected with host side
Send into the onboard storage device 3 of FPGA isomery speed-up computation devices, so that the row of fpga chip 1 obtains pending data and treats
Processing data is processed.Data transmission management module is additionally operable to obtain result after data processing terminates, and by this
Reason result is back to corresponding upper layer application.
Additionally, because the memory size of onboard storage device 3 is limited, and pass through GMM algorithms carries out data to pending data
Successive ignition is needed to calculate during treatment, in order to avoid the repetition of identical data is transmitted, data transmission management module can also be right
Whether pending data has carried out caching in onboard storage device 3 is judged, waits to locate when this has been cached in onboard storage device 3
Reason data, then need not send, when onboard storage device 3 is that the pending number is retransmited when being cached to pending data again
According to save memory space.
As preferred, judge whether pending data has been buffered in the onboard storage device of FPGA isomery speed-up computation devices
Process in 3 is specially：
The numbering of pending data is obtained, and to judge whether numbering has been stored in database, if it is, pending
Data have been buffered in the onboard storage device 3 of FPGA isomery speed-up computation devices, and otherwise, pending data is uncached different in FPGA
In the onboard storage device 3 of structure speed-up computation device.
It should be noted that the numbering of pending data and pending data are one-to-one relations, and data are passed
Defeated management module often sends a pending data and will preserve to the data of itself numbering of transmitted pending data
Whether the pending number is learnt in storehouse, therefore by need to only judging the numbering for having the pending data currently to be sent in database
Whether according to being cached in onboard storage device 3, no longer occurring if the numbering of pending data is saved in the database should
Pending data, sends the pending data if the numbering of the pending data is not stored in database and should
The numbering of pending data is stored in the database.
Certainly, can also judge onboard storage device 3 using other determination methods in addition to above-mentioned determination methods is
No to have cached pending data, the present invention does not do special restriction, can realize the purpose of the present invention herein.
It should be noted that host side is used to realize that data transmission management module is realized and upper strata by a software interface
Information exchange between.
Also, it should be noted that in this manual, such as first and second or the like relational terms be used merely to by
One entity or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or operation
Between there is any this actual relation or order.And, term " including ", "comprising" or its any other variant meaning
Covering including for nonexcludability, so that process, method, article or equipment including a series of key elements not only include that
A little key elements, but also other key elements including being not expressly set out, or also include for this process, method, article or
The intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence "including a ...", does not arrange
Except also there is other identical element in the process including the key element, method, article or equipment.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or uses the present invention.
Various modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, the present invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The scope most wide for causing.
Claims (11)
1. a kind of FPGA isomeries speed-up computation device, it is characterised in that described device includes fpga chip, interface and is arranged at institute
The GMM counting circuits on fpga chip are stated, wherein：
The GMM counting circuits, for realizing GMM algorithms；
The fpga chip, for the pending data sent by the interface host side after startup, and by described
GMM counting circuits are processed the pending data, obtain result, so that the host side is obtained by the interface
Take the result.
2. FPGA isomeries speed-up computation device according to claim 1, it is characterised in that described device also includes onboard depositing
Reservoir, for receiving and caches the pending data that the host side sends；And for storing the result；
Then the process of the pending data that the corresponding fpga chip Receiving Host end sends is specially：Obtain described onboard deposit
The pending data in reservoir.
3. FPGA isomeries speed-up computation device according to claim 2, it is characterised in that the GMM counting circuits include：
The computing sub-circuit of symmetrical matrix order 1, for receiving the pending data, the pending data is that n element is constituted
Vector, logical operation is carried out to the pending data according to computing formula, obtain the weights of current iteration computing, the meter
Calculation formula is A:=alpha*x*x**T+A, wherein, alpha is given real number scalar；X is pending data, and x**T turns for x's
Put, A is n*n symmetrical matrixes；It is additionally operable to terminate computing according to the first control instruction；
GMM right value update sub-circuits, for by the weights of the new right value update of grey iterative generation each time last time grey iterative generation；Also
For terminating to update according to the second control instruction；
Iteration control sub-circuit, for generating and sending first control instruction and described when computing meets pre-conditioned
Two control instructions.
4. FPGA isomeries speed-up computation device according to claim 3, it is characterised in that pre-conditioned for operation times reach
To the first preset value.
5. FPGA isomeries speed-up computation device according to claim 3, it is characterised in that pre-conditioned for computing is obtained
Weights are less than the second preset value.
6. FPGA isomeries speed-up computation device according to claim 2, it is characterised in that the onboard storage device is DDR3
Memory or DDR4 memories.
7. FPGA isomeries speed-up computation device according to claim 1, it is characterised in that the interface is PCIE interfaces.
8. FPGA isomery speed-up computation devices according to claim 1-7 any one, it is characterised in that the FPGA is different
Structure speed-up computation device is the device for extending cassette design.
9. a kind of FPGA isomeries speed-up computation system, it is characterised in that the system includes host side and as claim 1-8 appoints
FPGA isomery speed-up computation devices described in meaning one, the FPGA isomeries speed-up computation device by the interface in the device with
The host side connection.
10. FPGA isomeries speed-up computation system according to claim 9, it is characterised in that the host side includes data
Transport management module, for obtaining pending data, and judges whether the pending data has been buffered in the FPGA isomeries
In the onboard storage device of speed-up computation device, if it is, not sending the pending data, otherwise, the pending number is sent
According to.
11. FPGA isomeries speed-up computation systems according to claim 10, it is characterised in that the judgement is described pending
The process whether data have been buffered in the onboard storage device of the FPGA isomeries speed-up computation device is specially：
The numbering of the pending data is obtained, and to judge whether the numbering has preserved in the database, if it is,
Then the pending data has been buffered in the onboard storage device of the FPGA isomeries speed-up computation device, otherwise, described to wait to locate
Reason data are uncached in the onboard storage device of the FPGA isomeries speed-up computation device.
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| CN108416433B (en) * | 2018-01-22 | 2020-11-24 | 上海熠知电子科技有限公司 | Neural network heterogeneous acceleration method and system based on asynchronous event |
| CN108509568A (en) * | 2018-03-26 | 2018-09-07 | 深圳大普微电子科技有限公司 | A kind of data storage and management method and device |
| CN108921289A (en) * | 2018-06-20 | 2018-11-30 | 郑州云海信息技术有限公司 | A kind of FPGA isomery accelerated method, apparatus and system |
| CN108921289B (en) * | 2018-06-20 | 2021-10-29 | 郑州云海信息技术有限公司 | FPGA heterogeneous acceleration method, device and system |
| CN110955390B (en) * | 2019-11-22 | 2023-08-08 | 北京达佳互联信息技术有限公司 | Data processing method, device, electronic equipment and storage medium |
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