CN106776445A - PXIe bus embedded type Zero greeve controllers - Google Patents
PXIe bus embedded type Zero greeve controllers Download PDFInfo
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- CN106776445A CN106776445A CN201611255336.8A CN201611255336A CN106776445A CN 106776445 A CN106776445 A CN 106776445A CN 201611255336 A CN201611255336 A CN 201611255336A CN 106776445 A CN106776445 A CN 106776445A
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- 230000006870 function Effects 0.000 claims abstract description 14
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 230000004075 alteration Effects 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- 230000003139 buffering effect Effects 0.000 claims description 4
- 238000013461 design Methods 0.000 claims description 4
- 230000009466 transformation Effects 0.000 claims description 3
- 238000012360 testing method Methods 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 10
- 230000004224 protection Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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Abstract
The invention belongs to test field of measuring technique, and in particular to a kind of PXIe bus embedded types Zero greeve controller.PXIe bus embedded type Zero greeve controllers, including core board and mainboard, are connected between described core board and mainboard by connector AB and connector CD；Described core board includes CPU, internal memory and Intel QM77 chipsets；Intel QM77 chipsets draw VGA signals, LVDS signals, 8 × USB2.0 signals, 6 road PCIe bus signals, GPIs/GPOs signals, 4 × SATA signals, Ethernet signals, LPC bus signals, SMBUS signals, power management and control signal and I2C signal is to AB connectors；Intel QM77 chipsets draw 3 × HDMI/DVI/DisplayPort signals, PCI bus signals, IDE signals and fan governor signal to CD connectors.PXIe bus embedded types Zero greeve controller integrated computer of the present invention and PXIe chain circuit functions, it is flexible and convenient to use, the integrated level of system is improved, have more advantage in portable system.
Description
Technical field
The invention belongs to test field of measuring technique, and in particular to a kind of PXIe bus embedded types Zero greeve controller.
Background technology
With the high speed development of informationization technology, measured signal frequency more and more higher, test data handling capacity is increasing,
The features such as PXIe buses Auto-Test System is with high-performance, high bandwidth, high reliability, progressively as test field of measuring technique hair
The trend of exhibition.
In PXIe bus Auto-Test Systems, PXIe cabinets provide connecting platform for PXI/PXIe functional modules, can be each
Module provides the functions such as working power, triggering, and PXIe buses Zero greeve controller is realized leading to each functional module in PXIe cabinets
News and control.
PXIe bus Zero greeve controllers are the infrastructure devices in PXIe bus Auto-Test Systems, for each function in system
The control of module with communicate, according to the difference of implementation, be generally divided into embedded and external hanging type two types.PXIe buses
Be integrated in one for computer and PXIe communication link expanded functions by PXIe bus embedded types Zero greeve controller, can effectively be lifted
The integrated level of PXIe bus Auto-Test Systems.
PXIe bus embedded type Zero greeve controllers belong to test field of measuring technique, meet PCIe bus specifications R2.0 and
PXIe hardware specification R1.0, meet demand of the Auto-Test System to high speed data transfer.
The content of the invention
It is an object of the present invention to provide a kind of PXIe bus embedded types Zero greeve controller, mainly by core board and mainboard two parts
Composition, is the grooves of PXIe 3 position 3U standard modules, is inserted in the system groove of PXIe cabinets, can be constituted with PXIe cabinets and functional module
It is the Auto-Test System of core.
Technical program of the present invention lies in：
PXIe bus embedded type Zero greeve controllers, including core board and mainboard, by connecting between described core board and mainboard
Connect device AB and connector CD connections；Described core board includes CPU, internal memory and Intel QM77 chipsets；Intel QM77
Chipset draw VGA signals, LVDS signals, 8 × USB2.0 signals, 6 road PCIe bus signals, GPIs/GPOs signals,
4 × SATA signals, Ethernet signals, LPC bus signals, SMBUS signals, power management and control signal and I2C believes
Number to AB connectors；Intel QM77 chipsets draw 3 × HDMI/DVI/DisplayPort signals, PCI buses letter
Number, IDE signals and fan governor signal to CD connectors.
Described mainboard draws core partitioned signal by connector AB and connector CD, realizes DVI-Integrated circuit, RS-
232 serial port circuits, gigabit Ethernet mouth, USB interface, gpib interface circuit, TRIG interface circuits, PXI e interface circuit portions
Function and reset function；And ATX power supply timings circuit provides power supply needed for core board and voltage transformation is provided by simulating
Power supply needed for mainboard.
Described PXI e interface circuit includes PXIe system grooves connector, clock circuit and PCIe alteration switches, wherein,
PXI e interface circuit by PCIe alteration switches connector AB is drawn × 4 PCIe signal extensions be 4 tunnel × 4 PCIe signals
Deliver to PXIe system grooves；Wherein, clock circuit expands 5 road reference clocks by PCIe clock buffer, and 1 tunnel supply PCIe is handed over
Switch is changed, 4 roads supply 4 tunnel × 4 PCIe links in addition；4 tunnels of PXI e interface and PCIe clock circuit realiration and case back plate ×
4PCIe is linked, and provides PCIe link work required clock.
Described gpib interface circuit include be sequentially connected pci interface bus chip, FPGA, gpib bus driver with
And gpib bus interface, described FPGA realizes configuring by IP core design, realizes the conversion of pci bus and gpib bus.
Described TRIG interface circuits include the I being sequentially connected2C I/O expansions chip, logic bus switch, front panel
TRIG, caching driving chip and case back plate；
TRIG interface circuits pass through I2C I/O expansion chips expand 8 railway digital IO, as the enable signal that logic bus are switched,
The input/output signal that front panel TRIG interfaces are switched with 8 road TRIG signals of case back plate as logic bus, by control
The enable signal of logic bus switch, realizes the 8 road two-way Trigger Functions of TRIG signals of above plate interface and case back plate.
Described DVI-Integrated circuit includes that HDMI level translators, level conversion and sync buffering device and DVI-I connect
Connect device；Wherein, the output of HDMI level translators is directly connected with the DVI-D signals of DVI-I connectors, level conversion with it is same
The output for walking buffer is connected with the VGA signals of DVI-I connectors.
The technical effects of the invention are that：
PXIePXIe bus embedded type Zero greeve controller integrated computers and PXIe chain circuit functions, it is flexible and convenient to use, improve
The integrated level of system, advantage is had more in portable system.
Brief description of the drawings
Fig. 1 is PXIe bus embedded type Zero greeve controller general principles block diagrams.
Fig. 2 is PXIe bus embedded type Zero greeve controller core board theory diagrams.
Fig. 3 is the PXI e interface schematic block circuit diagram of mainboard.
Fig. 4 is the gpib interface schematic block circuit diagram of mainboard.
Fig. 5 is the TRIG interface circuit theory diagrams of mainboard.
Fig. 6 is the DVI-Integrated schematic block circuit diagram of mainboard.
Fig. 7 is the simulation ATX power supply timing schematic block circuit diagrams of mainboard.
Fig. 8 is other interface circuit theory diagrams of mainboard.
Specific embodiment
PXIe bus embedded type Zero greeve controllers, including core board and mainboard, lead between described core board and mainboard
Cross connector AB and connector CD connections；Described core board includes CPU, internal memory and Intel QM77 chipsets；Intel
QM77 chipsets draw VGA signals, LVDS signals, 8 × USB2.0 signals, 6 road PCIe bus signals, GPIs/GPOs
Signal, 4 × SATA signals, Ethernet signals, LPC bus signals, SMBUS signals, power management and control signal and
I2C signal is to AB connectors；It is total that Intel QM77 chipsets draw 3 × HDMI/DVI/DisplayPort signals, PCI
Line signal, IDE signals and fan governor signal are to CD connectors.
Described mainboard draws core partitioned signal by connector AB and connector CD, realizes DVI-Integrated circuit, RS-
232 serial port circuits, gigabit Ethernet mouth, USB interface, gpib interface circuit, TRIG interface circuits, PXI e interface circuit portions
Function and reset function；And ATX power supply timings circuit provides power supply needed for core board and voltage transformation is provided by simulating
Power supply needed for mainboard.
Described PXI e interface circuit includes PXIe system grooves connector, clock circuit and PCIe alteration switches, wherein,
PXI e interface circuit by PCIe alteration switches connector AB is drawn × 4 PCIe signal extensions be 4 tunnel × 4 PCIe signals
Deliver to PXIe system grooves；Wherein, clock circuit expands 5 road reference clocks by PCIe clock buffer, and 1 tunnel supply PCIe is handed over
Switch is changed, 4 roads supply 4 tunnel × 4 PCIe links in addition；4 tunnels of PXI e interface and PCIe clock circuit realiration and case back plate ×
4PCIe is linked, and provides PCIe link work required clock.
Described gpib interface circuit include be sequentially connected pci interface bus chip, FPGA, gpib bus driver with
And gpib bus interface, described FPGA realizes configuring by IP core design, realizes the conversion of pci bus and gpib bus.
Described TRIG interface circuits include the I being sequentially connected2C I/O expansions chip, logic bus switch, front panel
TRIG, caching driving chip and case back plate；
TRIG interface circuits pass through I2C I/O expansion chips expand 8 railway digital IO, as the enable signal that logic bus are switched,
The input/output signal that front panel TRIG interfaces are switched with 8 road TRIG signals of case back plate as logic bus, by control
The enable signal of logic bus switch, realizes the 8 road two-way Trigger Functions of TRIG signals of above plate interface and case back plate.
Described DVI-Integrated circuit includes that HDMI level translators, level conversion and sync buffering device and DVI-I connect
Connect device；Wherein, the output of HDMI level translators is directly connected with the DVI-D signals of DVI-I connectors, level conversion with it is same
The output for walking buffer is connected with the VGA signals of DVI-I connectors.
It is illustrated in figure 7 the simulation ATX power supply timing schematic block circuit diagrams of PXIe embedded controller mainboards, PXIe cabinets
When connecting alternating current ,+5Vaux power supplys are powered for PXIe bus embedded type Zero greeve controllers；When PXIe chassis power supplys switch is pressed,
Its backboard exports PWR_BTN# signals to PXIe bus embedded type Zero greeve controllers, and PXIe bus embedded types Zero greeve controller is produced
SUS_S3# signals, are connected to the PS_ON signals of case back plate after being changed through negater circuit, after PXIe cabinets detect the signal,
Start+12V ,+5V, the output of+3.3V power supplys；PXIe bus embedded types Zero greeve controller by power monitoring chip to backboard+
Three kinds of power supplys of 12V ,+5V ,+3.3V are monitored simultaneously, when+12V ,+5V ,+3.3V power supplys stablize output, PXIe case back plates system
System groove output PWR_OK signals, control delay circuit sends into PXIe bus embedded types after making PWR_OK signal delays at least 100ms
Zero greeve controller；After PXIe bus embedded type Zero greeve controllers detect PWR_OK signals, represent that each road power supply output is normal,
PXIe bus embedded type Zero greeve controllers start normal upper electricity, and BIOS operations, generation system reset and peripheral hardware reset.
It is illustrated in figure 8 other interface circuit theory diagrams of PXIe embedded controller mainboards, including network interface, USB2.0
The design of interface, serial ports, reset and indicator lamp.LAN Magnetic in gigabit ethernet interface are used for electrical isolation and common mode presses down
System, strengthens transmission range and antijamming capability.The power distribution circuit of USB interface is used for the overcurrent protection of USB interface；Protection electricity
Road is used for the ESD protections to USB circuit.Serial port circuit turns UART bridging chips and realizes USB to RS232 rs 232 serial interface signals by USB
Conversion.Reset circuit mainly realizes the reset of whole system by outer SR.Indicator lamp includes power supply indicator, hard disk
Indicator lamp, 2 user lamps and 2 network state indicator lamps, are easy to user to observe the working condition of Zero greeve controller.
Claims (6)
1.PXIe bus embedded type Zero greeve controllers, it is characterised in that：Including core board and mainboard, described core board and master
Connected by connector AB and connector CD between plate；Described core board includes CPU, internal memory and Intel QM77 chips
Group；Intel QM77 chipsets draw VGA signals, LVDS signals, 8 × USB2.0 signals, 6 road PCIe bus signals,
GPIs/GPOs signals, 4 × SATA signals, Ethernet signals, LPC bus signals, SMBUS signals, power management and control
Signal processed and I2C signal is to AB connectors；Intel QM77 chipsets draw 3 × HDMI/DVI/DisplayPort letters
Number, PCI bus signals, IDE signals and fan governor signal to CD connectors.
2. PXIe bus embedded types Zero greeve controller according to claim 1, it is characterised in that：Described mainboard is by connecting
Meet device AB and connector CD and draw core partitioned signal, realize DVI-Integrated circuit, RS-232 serial port circuits, gigabit Ethernet mouthful,
USB interface, gpib interface circuit, TRIG interface circuits, PXI e interface circuit portions function and reset function；And by mould
Intend ATX power supply timings circuit and power supply needed for core board and power supply needed for voltage transformation offer mainboard are provided.
3. PXIe bus embedded types Zero greeve controller according to claim 2, it is characterised in that：Described PXI e interface electricity
Road includes PXIe system grooves connector, clock circuit and PCIe alteration switches, wherein, PXI e interface circuit is exchanged by PCIe
Switch connector AB is drawn × 4 PCIe signal extensions deliver to PXIe system grooves for 4 tunnel × 4 PCIe signals；Wherein, clock
Circuit expands 5 road reference clocks by PCIe clock buffer, and 1 road supplies PCIe alteration switches, and 4 roads supply 4 tunnel × 4 in addition
PCIe link；PXI e interface and PCIe clock circuit realiration are linked with the 4 tunnels × 4PCIe of case back plate, and provide PCIe link
Clock needed for work.
4. PXIe bus embedded types Zero greeve controller according to claim 2, it is characterised in that：Described gpib interface electricity
Road includes the pci interface bus chip, FPGA, gpib bus driver and the gpib bus interface that are sequentially connected, described
FPGA realizes configuring by IP core design, realizes the conversion of pci bus and gpib bus.
5. PXIe bus embedded types Zero greeve controller according to claim 2, it is characterised in that：Described TRIG interfaces electricity
Road includes the I being sequentially connected2C I/O expansions chip, logic bus switch, front panel TRIG, caching driving chip and the cabinet back of the body
Plate；
TRIG interface circuits pass through I2C I/O expansion chips expand 8 railway digital IO, as the enable signal that logic bus are switched,
The input/output signal that front panel TRIG interfaces are switched with 8 road TRIG signals of case back plate as logic bus, by control
The enable signal of logic bus switch, realizes the 8 road two-way Trigger Functions of TRIG signals of above plate interface and case back plate.
6. PXIe bus embedded types Zero greeve controller according to claim 2, it is characterised in that：Described DVI-Integrated
Circuit includes HDMI level translators, level conversion and sync buffering device and DVI-I connectors；Wherein, HDMI level conversions
The output of device is directly connected with the DVI-D signals of DVI-I connectors, and level conversion connects with the output of sync buffering device with DVI-I
Connect the VGA signals connection of device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611255336.8A CN106776445B (en) | 2016-12-30 | 2016-12-30 | PXIe bus embedded zero-slot controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611255336.8A CN106776445B (en) | 2016-12-30 | 2016-12-30 | PXIe bus embedded zero-slot controller |
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| Publication Number | Publication Date |
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| CN106776445A true CN106776445A (en) | 2017-05-31 |
| CN106776445B CN106776445B (en) | 2024-04-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113886304A (en) * | 2021-09-06 | 2022-01-04 | 浪潮集团有限公司 | PXIe measurement and control backboard |
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-
2016
- 2016-12-30 CN CN201611255336.8A patent/CN106776445B/en active Active
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| CN103023823A (en) * | 2012-11-26 | 2013-04-03 | 北京航天测控技术有限公司 | Five-slot shaped backboard for PXI (pulsed xenon illuminator) portable platform |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113886304A (en) * | 2021-09-06 | 2022-01-04 | 浪潮集团有限公司 | PXIe measurement and control backboard |
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