CN106776367B - Method for realizing consistency of instruction Cache based on position corresponding relation - Google Patents

Abstract

The invention relates to a method for realizing consistency of an instruction Cache based on a position corresponding relation, wherein an instruction Cache management component and a secondary Cache management component are provided with an Itag array and an FB filling buffer with the same organization structure, wherein the instruction Cache management component adopts a virtual address, and the secondary Cache management component adopts a physical address. When the instruction access instruction Cache is missing, applying for an item of a V-FB filling buffer, applying for an item of a P-FB filling buffer according to the item of the V-FB filling buffer, after the data of the instruction Cache block completely returns to the instruction Cache management part, starting filling the V-Itag array by the V-FB filling buffer, filling contents into a corresponding position of the P-Itag array by the P-FB filling buffer according to the position of filling the V-Itag array after filling, and finally sequentially invalidating the item of the P-FB filling buffer and the item of the V-FB filling buffer. The invention realizes the consistency of the instruction Cache.

Description

Method for realizing consistency of instruction Cache based on position corresponding relation

Technical Field

The invention relates to the technical field of Cache consistency of microprocessors, in particular to a method for realizing the Cache consistency of an instruction based on a position corresponding relation.

Background

In modern microprocessors, caches are standard configurations, and generally include an instruction Cache (abbreviated as "I-Cache"), a data Cache (abbreviated as "D-Cache"), a secondary Cache (abbreviated as "L2-Cache"), a tertiary Cache (abbreviated as "L3-Cache"), and the like. To implement data intercommunication between caches, data consistency between caches must be maintained. Usually, the D-Cache, L2-Cache or L3-Cache all have writable copies and store them as physical addresses. And the I-Cache is a read-only copy and can be stored in a physical address mode or a virtual address mode.

To obtain the writable right, the copy needs to invalidate other caches that also have the copy. Generally, the criterion for determining whether the copies have the same authority is to see whether the physical address of the copy and the physical address of the copy which is acquiring the writable authority belong to the same Cache block.

The instruction in the instruction address space stores data. In general, the instructions are compiled in advance, and the CPU does not need to modify the contents stored in the instruction space. However, for executing an interpreted program such as Java, the instructions that the CPU needs to execute are temporarily generated, rather than being compiled in advance, so the CPU "consumes" the instructions while "producing" the instructions. The process of "producing" an instruction, which is actually writing to the instruction space, requires that the old copy be removed from the instruction space. If the old copy is in the I-Cache, the old copy needs to be invalidated from the I-Cache. For a CPU which does not support the consistency of the instruction Cache, the I-Cache invalidation mode is usually that the I-Cache is completely refreshed and software intervention is needed, but the defect of the method is that the efficiency is low, and some copies which do not need to be cleaned are cleaned out by refreshing the I-Cache, so that unnecessary I-Cache loss is caused, and the performance is influenced.

The consistency of the hardware supporting the instruction Cache can better support the execution of the interpretative program such as Java, namely, the hardware ensures that when the CPU writes data in the instruction space, the hardware automatically invalidates the corresponding old instruction in the I-Cache. Therefore, when the CPU "consumes" self "production" instruction, the CPU can obtain correct new instruction without the action of invalidation by software.

For an I-Cache stored by a physical address, when the consistency of an instruction Cache is realized by hardware, since the L2-Cache is also stored by the physical address, a secondary request is generated according to the physical address. However, when the instruction Cache stored by the physical address is accessed, a virtual address and real address substitution step of the I-TLB is added compared with the instruction Cache directly stored by the virtual address. For the I-Cache stored by using the virtual address, since the L2-Cache is stored according to the physical address, the secondary request cannot be directly generated according to the address, and a new method needs to be found when the hardware realizes the consistency of the instruction Cache.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a method for realizing the consistency of the instruction Cache based on the position corresponding relation, so that the consistency of the instruction Cache is realized on the premise that the I-Cache is used for virtual address storage and the L2-Cache is used for physical address storage.

The technical scheme adopted by the invention for solving the technical problems is as follows: a method for realizing the consistency of an instruction Cache based on a position corresponding relation is provided, a V-Itag array and a V-FB filling buffer are arranged in an instruction Cache management part, a P-Itag array and a P-FB filling buffer are arranged in a secondary Cache management part, wherein the V-FB filling buffer and the P-FB filling buffer have the same organization structure, the V-FB filling buffer and the P-FB filling buffer store the information of the same Cache line at the same position, and the V-FB filling buffer records a virtual address and a physical address recorded by the P-FB filling buffer; the V-Itag array and the P-Itag array have the same organization structure, the same position in the V-Itag array and the P-Itag array stores the information of the same Cache line, the V-Itag array adopts a virtual address mark, and the P-Itag array adopts a physical address mark;

when the instruction Cache is lost, the instruction Cache is filled, and the method specifically comprises the following steps: firstly applying for the entry of a V-FB filling buffer and recording required information, then applying for the entry of a P-FB filling buffer and recording the required information according to the entry of the V-FB filling buffer, after instruction Cache block data completely returns to an instruction Cache management part, the V-FB filling buffer starts to fill a V-Itag array, after filling is finished, the P-FB filling buffer fills contents to the corresponding position of the P-Itag array according to the position of filling the V-Itag array, and finally, the entry of the P-FB filling buffer and the entry of the V-FB filling buffer are invalidated in sequence.

The application for the entry of the V-FB filling buffer and the entry of the P-FB filling buffer corresponding thereto and recording the required information are specifically: firstly applying for a V-FB filling buffer entry, recording required information in the V-FB filling buffer entry, then acquiring the physical address of a missing Cache block, then sending a request to a secondary Cache management component, applying for a P-FB filling buffer entry corresponding to the V-FB filling buffer entry, and recording the required information in the P-FB filling buffer entry.

And after the V-FB filling buffer is filled with the V-Itag array, sending a copy request to the secondary Cache management component, and filling the content into the P-Itag array by the P-FB filling buffer, wherein the position filled into the P-Itag array corresponds to the position filled into the V-Itag array.

When the V-FB filling buffer fills the V-Itag array, the V-Itag at the original position is invalidated when the first flag data of the Cache block is filled, and the new address is filled into the V-Itag and is validated when the last flag data of the Cache block is filled.

When data errors occur, the instruction Cache management part sends a abandon request to the secondary Cache management part, the secondary Cache management part invalidates corresponding entries of the P-FB filling buffer, and then sends response information to the instruction Cache management part; and after receiving the response information of the abandon request, the instruction Cache management part invalidates the corresponding entry of the V-FB filling buffer.

In the filling process, when a secondary Cache management part receives a write-type request or an external invalidation-type secondary request, inquiring a P-Itag array and a P-FB filling buffer according to physical addresses of the write-type request and the external invalidation-type secondary request, when finding that the P-Itag array or the P-FB filling buffer has a copy of the physical address, invalidating a corresponding position of the P-Itag array or a corresponding entry of the P-FB filling buffer, and sending the position of the P-Itag array or the entry of the P-FB filling buffer as information to an instruction Cache management part.

If the instruction Cache management part receives an invalidation secondary request taking the entry of the P-FB filling buffer as information, the processing procedure is as follows:

if the content in the V-FB filling buffer is in the state of sending the abandon request and waiting for the response returned by the secondary Cache management part, not processing;

if the content in the V-FB filling buffer is in the state of sending the copy request and waiting for the response of the secondary Cache to return the management part, the V-FB filling buffer is not processed, and the corresponding copy in the V-Itag array is invalidated;

if the content in the V-FB filling buffer has already filled the instruction Cache, but has not sent the copy request, have not abandoned the request either, put the V-FB filling buffer invalid, put the corresponding duplicate in the V-Itag array invalid at the same time;

and if the contents in the V-FB filling buffer are not filled with the instruction Cache and no copy class request or abandon class request is sent, invalidating the V-FB filling buffer.

If the instruction Cache management component receives the invalidation secondary request taking the position of the P-Itag array as the information, the processing process is as follows:

if the position of the V-Itag array is not completely covered by the content in the V-FB filling buffer, namely the content in the V-FB filling buffer does not start filling or the filling instruction Cache is not finished, invalidating the content in the position of the V-Itag array;

if the contents of the V-FB fill buffer have completed filling the location of the V-Itag array, the invalidate secondary request is ignored.

Advantageous effects

Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the method is not based on the address corresponding relation, does not need TLB (translation lookaside buffer) substitution, does not need the L2-Cache and the I-Cache to be in an inclusion relation, and can realize the consistency of the I-Cache and the L2-Cache by utilizing the buffer which is arranged in the L2-Cache management part and corresponds to the instruction Tag in a position distinguishing mode under the condition that the I-Cache is marked by a virtual address and the L2-Cache is marked by a physical address. The method has less mutual constraint requirements on the I-Cache and the L2-Cache, and can improve the performance of the microprocessor under the application mode of producing instructions and consuming instructions.

Drawings

FIG. 1 is a schematic diagram of a memory hierarchy to which the present invention relates;

FIG. 2 is a diagram illustrating allocation of V-FB entries and application of P-FB entries with the same allocation number when an instruction fetch request misses in I-Cache and V-FB;

FIG. 3 is a schematic diagram of a V-FB entry filling a V-Itag;

FIG. 4 is a schematic diagram illustrating a processing flow of a copy request CP and its response;

FIG. 5 is a schematic diagram of a processing flow of a castout request EV and its response;

FIG. 6 is a flow chart illustrating a process of receiving a put V-FB invalidation secondary request when a V-FB entry has not started or completed filling a V-Itag;

FIG. 7 is a schematic view showing a process flow of receiving a V-FB invalidation secondary request when a V-FB entry completes V-Itag filling but does not issue a shellfish copying request;

FIG. 8 is a schematic diagram illustrating a process flow of a simultaneous presence of a set V-FB invalidation secondary request and a copy request;

FIG. 9 is a flow chart illustrating a process for a simultaneous V-FB invalidation secondary request and castout request;

FIG. 10 is a flowchart illustrating a process of invalidating the V-Itag secondary request when the V-FB has not completed loading the V-Itag;

FIG. 11 is a flow chart illustrating the processing of a secondary invalidation request to set V-Itag after the V-FB finishes filling the V-Itag.

Detailed Description

The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.

The embodiment of the invention relates to a method for realizing the consistency of an instruction Cache based on a position corresponding relation, the memory hierarchy related to the invention is shown in figure 1 and comprises structures such as an I-Cache management component, a D-Cache management component, an L2-Cache management component, an L3-Cache management component, a memory and the like, and Itag arrays and FB filling buffers with the same organization structure are arranged in the I-Cache management component and the L2-Cache management component. The V-FB filling buffer and the P-FB filling buffer store the information of the same Cache line at the same position, except that the V-FB filling buffer records a virtual address and the P-FB filling buffer records a physical address. The same position (same index and same way) in the V-Itag array and the P-Itag array also stores the information of the same Cache line, wherein the V-Itag array adopts a virtual address mark, and the P-FB array adopts a physical address mark. Within a few short beats of the fill entry, the contents of the V-Itag array and the P-Itag array, and the V-FB fill buffer and the P-FB fill buffer are allowed to be inconsistent, but the processing flow will ensure the correctness of the beats and finally make the records in the L2-Cache management component and the records in the I-Cache management component consistent.

Both the write class request of the D-Cache and the secondary request of the external invalidation class may hit the P-FB or the P-Itag, so that invalidation of the corresponding entry is caused, and at this time, the V-FB and the V-Itag in the I-Cache management component need to be notified to perform corresponding operation. In addition, the I-Cache management component can also send a copy request or a discard request to the L2-Cache management component and obtain a response, so that the consistency of the I-Cache is maintained.

As shown in FIG. 2, when the instruction fetch request misses in the instruction Cache, and also hits in the V-FB load buffer, an entry in the V-FB load buffer is applied, as shown by the black shaded block in the figure; the L2-Cache management component is then asked for an entry for the P-FB fill buffer that is numbered the same as the V-FB fill buffer. At the time of filing a buffered entry for a V-FB, the location of the V-Itag array that the entry will fill in the future has been determined, as indicated by the vertical hatching in the figure. At this time, the position of the V-Itag array may not be valid or may be valid and is information of other Cache lines.

Specifically, when an instruction access instruction Cache misses, a request is always applied for a V-FB filling buffer entry, assuming that the entry is an entry I, after required information is recorded in the applied entry I, the I-TLB is inquired, the physical address of the missing Cache block is obtained, a request is sent to an L2-Cache management unit, the request is applied for a P-FB filling buffer entry I corresponding to the V-FB filling buffer, and the required information is recorded. The L2-Cache management component is then queried, waiting for data to return.

As shown in FIG. 3, when instruction data is returned by the L2-Cache management component into the V-FB fill buffer, the data in the V-FB fill buffer is filled into the V-Itag array at an appropriate timing, such as when the write port of the instruction Cache management component is free. The process of packing needs to last for multiple clock cycles. Specifically, when the data of the instruction Cache block is completely returned to the I-Cache management component, the V-FB filling buffer starts to fill the instruction Cache and modifies the V-Itag array. Since a plurality of cycles are needed to load one Cache block, in general loading processing, when the first flag data of the Cache block is loaded, the V-Itag at the original position is invalidated, and when the last flag data of the Cache block is loaded, a new address is loaded into the V-Itag and is validated.

As shown in FIG. 4, when the entry of the V-FB filling buffer finishes filling the V-Itag array, a copy class request CP is sent to the L2-Cache management component, the content in the P-FB filling buffer is filled into the entry corresponding to the P-Itag array, after filling is finished, the entry of the P-FB filling buffer is invalidated, and meanwhile, a response of the copy class request is sent to the I-Cache management component. When the I-Cache management part receives the response, the corresponding entry of the V-FB filling buffer is invalidated, and a filling process is completed. That is, after the V-FB filling buffer finishes filling the data of the whole Cache block, a copy class request CP is sent to the L2-Cache management component, the entry number I of the V-FB filling buffer is carried, the index number X and the path number W of the filled V-Itag, the P-FB filling buffer of the ith entry is informed, the physical address is written into the P-Itag array of the index number X and the path number W and is enabled, then the entry I of the P-FB filling buffer is deleted, a completion response is returned to the I-Cache management component, and after the V-FB filling buffer receives the completion response, the entry I is deleted.

As shown in FIG. 5, when a certain V-FB entry needs to be discarded due to data errors and the like, the I-Cache management component sends a discarding type request EV to the L2-Cache management component, the L2-Cache management component invalidates the corresponding P-FB entry, and then sends response information to the I-Cache management component. And after receiving the response of the abandon request, the I-Cache management part invalidates the corresponding V-FB entry to complete the processing flow of the abandon request.

That is, when the entry i of the V-FB fill buffer does not need to fill the instruction Cache for some reason (the filled data has an error or the filled data is invalid data on an error path), a castout request EV is issued to the L2-Cache management section. The P-FB filling buffer deletes the entry i after receiving the request, and then returns a completion response to the V-FB filling buffer, and then the V-FB filling buffer deletes the entry i.

Assuming that the data of the new Cache block to be filled stored in the entry i of the V-FB filling buffer is W, and the data of the old Cache block to be covered in the V-Itag array is D, the invalidation secondary request may be received as follows:

after the data W is completely loaded into the entry I of the V-FB filling buffer, no matter whether the data W is loaded into the V-Itag array or not, the I-Cache management component may receive an invalidation secondary request sent by the L2-Cache management component for the data W; before data W has not completely loaded into entry i of the V-FB fill buffer, then L2-Cache management component does not issue a secondary request for W.

For data D, after entry I of the V-FB fill buffer completes filling of the V-Itag array, a copy class request is issued to the L2-Cache management component, and a response of the L2-Cache management component is received, the I-Cache management component does not receive an invalidate secondary request for data D. It is possible that an invalidating secondary request for data D is received before the response of the above-mentioned L2-Cache management component is received.

In the time period that the invalidation secondary request can be received, when the L2-Cache management component receives a write class request sent by the D-Cache management component or an external invalidation request sent by the memory/third-level Cache management component, the P-Itag array and the P-FB filling buffer are simultaneously inquired through the physical address A of the write class request or the external invalidation request. When any one of the following conditions is met, the I-Cache management component receives an invalidation secondary request: (1) if the copy of the address A exists in the P-Itag array, recording the index number X and the way number W of the copy of the address A, and sending the index number X and the way number W to the I-Cache management component as the information of a secondary request; (2) and if finding that the copy of the address A is buffered in the P-FB filling buffer, recording the entry number I of the copy of the address A, and sending the entry number I to the I-Cache management component as the information of the secondary request.

The I-Cache management component has different processing modes aiming at the invalidation secondary requests of the received data W and the data D at different stages.

If the I-Cache management component receives an invalidate secondary request for entry I (i.e., data W) of the V-FB load buffer, the process is as follows:

if the data W is not filled with the instruction Cache and the copy request CP or the abandon request EV is not sent, only the W needs to be invalidated. As shown in FIG. 6, when a write-type request or an external invalidation-type secondary request hits an entry of a certain P-FB load buffer, the entry of the P-FB load buffer needs to be invalidated, and a V-FB load buffer invalidation secondary request is sent to the I-Cache management component. And if the corresponding entry of the V-FB filling buffer is not filled with the instruction Cache and no copy class request or abandon class request is sent currently, invalidating the entry of the V-FB filling buffer.

If the data W has been filled with the instruction Cache, but the copy class request CP has not been sent yet, and the castout class request EV has not been sent yet, the data W needs to be invalidated, and the copies of the index number X and the way number W in the V-Itag need to be invalidated, because the position of the data D is already covered by the data W at this time. As shown in FIG. 7, when a write-type request or an external invalidation-type secondary request hits an entry of a certain P-FB load buffer, the entry of the P-FB load buffer needs to be invalidated, and an invalidation secondary request for placing a V-FB load buffer is sent to the I-Cache management component. If the corresponding V-FB filling buffer is filled with the instruction Cache, but the copy class request CP is not sent yet, and the class request EV is not discarded, the entry of the V-FB filling buffer is invalidated, and the contents in the index number and the way number corresponding to the V-Itag array filled with the V-FB entry are also invalidated. After the action of invalidating the V-Itag array is completed, the corresponding P-Itag array may: one is invalid; the other is a valid and old address. If the P-Itag array is valid, the I-Cache management component may receive an invalid secondary request for setting the V-Itag array, and since the content of the corresponding position of the V-Itag array is invalid at this time, setting the invalid again does not produce any effect, and does not affect the correctness.

If the data W is in the state of having sent the copy shellfish request CP and waiting for the L2Cache to return the management part response, the V-FB filling buffer is not processed, but the copy of the index number X and the way number W in the V-Itag array is invalidated because the position of the data D is already covered by the data W at this time. As shown in FIG. 8, when a write-type request or an external invalidation-type secondary request hits a certain P-FB entry, the entry of the P-FB filling buffer needs to be invalidated, and an invalidation secondary request for setting a V-FB filling buffer is sent to the I-Cache management component. When the I-Cache management component receives the secondary request, the corresponding V-FB filling buffer entry is found to send out a copy type request CP, and the L2-Cache management component is waiting for the response, and the content in the V-Itag array filled by the V-FB filling buffer entry is invalidated. The L2-Cache management component processes the copy class request and sends a response to the I-Cache management component. The I-Cache management component invalidates the entry of the V-FB load buffer in response to the copy class request.

If the data W is in the state of having sent the castout request EV and waiting for the L2-Cache management component to return a response, no processing is performed. As shown in FIG. 9, when a write-type request or an external invalidation-type secondary request hits an entry of a certain P-FB load buffer, the entry of the P-FB load buffer needs to be invalidated, and an invalidation secondary request for placing a V-FB load buffer is sent to the I-Cache management component. When the I-Cache management component receives the secondary request, the corresponding entry is found to send out a castout request EV, and the response of the L2-Cache management component is waited, and then the invalid secondary request of the V-FB filling buffer is ignored. And the L2Cache management component processes the abandon request and sends a response to the I-Cache end. The I-Cache management component invalidates the V-FB entry upon receiving a response to the castout type request.

If the I-Cache management component receives an invalidation secondary request aiming at the copy of the index number X and the way number W (namely data D) in the V-Itag array, the processing is as follows:

and if the data D is not completely covered by the data W at the moment, namely the data W does not start to fill or does not finish filling the I-Cache, invalidating the D in the I-Cache. As shown in FIG. 10, when a write-type request or an external invalidation-type secondary request hits a position corresponding to a certain P-Itag array, it is necessary to invalidate the position corresponding to the P-Itag array and send an invalidation secondary request for setting the V-Itag array to the I-Cache management component. When the I-Cache management component receives the secondary request, the entry of the V-FB filling buffer corresponding to the V-Itag array is found not to be in the filling completion state, and the content in the position corresponding to the V-Itag array is invalidated. At this time, if the filling process is in progress, since the corresponding position of the V-Itag array is invalidated at the beginning of the filling process, the invalidation again does not produce any effect, and the filling process can still be continued.

If data W has completed the padding of index number X and way number W in V-Itag, the invalidate secondary request is ignored. As shown in FIG. 11, when a write-type request or an external invalidation-type secondary request hits a position corresponding to a certain P-Itag array, it is necessary to invalidate the position corresponding to the P-Itag and send an invalidation secondary request for setting the V-Itag array to the I-Cache management component. When the I-Cache management component receives the secondary request, the V-FB filling buffer entry corresponding to the V-Itag array is found to be in a filling completion state, so that the L2-Cache management component hits the entry before filling, and the entry is already covered by new content, and therefore the V-Itag array invalid secondary request can be directly ignored.

The consistency between the I-Cache and the L2-Cache can be realized by utilizing the buffer corresponding to the instruction Tag arranged in the L2-Cache management component in a position distinguishing mode without address corresponding relation, TLB substitution and inclusion relation between the L2-Cache and the I-Cache, and under the condition that the I-Cache is marked by a virtual address and the L2-Cache is marked by a physical address. The method has less mutual constraint requirements on the I-Cache and the L2-Cache, and can improve the performance of the microprocessor under the application mode of producing instructions and consuming instructions.

Claims (8)

1. A method for realizing the consistency of an instruction Cache based on a position corresponding relation is characterized in that a V-Itag array and a V-FB filling buffer are arranged in an instruction Cache management part, and a P-Itag array and a P-FB filling buffer are arranged in a secondary Cache management part, wherein the V-FB filling buffer and the P-FB filling buffer have the same organization structure, the V-FB filling buffer and the P-FB filling buffer store the information of the same Cache line at the same position, and the V-FB filling buffer records a virtual address and a physical address recorded by the P-FB filling buffer; the V-Itag array and the P-Itag array have the same organization structure, the same position in the V-Itag array and the P-Itag array stores the information of the same Cache line, the V-Itag array adopts a virtual address mark, and the P-Itag array adopts a physical address mark;

when the instruction Cache is lost, the instruction Cache is filled, and the method specifically comprises the following steps: firstly applying for the entry of a V-FB filling buffer and recording required information, then applying for the entry of a P-FB filling buffer and recording the required information according to the entry of the V-FB filling buffer, after instruction Cache block data completely returns to an instruction Cache management part, the V-FB filling buffer starts to fill a V-Itag array, after filling is finished, the P-FB filling buffer fills contents to the corresponding position of the P-Itag array according to the position of filling the V-Itag array, and finally, the entry of the P-FB filling buffer and the entry of the V-FB filling buffer are invalidated in sequence.

2. The method for implementing consistency of instruction caches based on location mapping relationships as claimed in claim 1, wherein the applying for entries of V-FB fill buffers and corresponding entries of P-FB fill buffers and recording required information specifically comprises: firstly applying for a V-FB filling buffer entry, recording required information in the V-FB filling buffer entry, then acquiring the physical address of a missing Cache block, then sending a request to a secondary Cache management component, applying for a P-FB filling buffer entry corresponding to the V-FB filling buffer entry, and recording the required information in the P-FB filling buffer entry.

3. The method for implementing the consistency of the instruction Cache based on the position correspondence relationship as claimed in claim 1, wherein the V-FB filling buffer sends a copy class request to the secondary Cache management component after filling the V-Itag array, and the P-FB filling buffer fills the content into the P-Itag array, wherein the position filled into the P-Itag array corresponds to the position filled into the V-Itag array.

4. The method as claimed in claim 1, wherein when the V-FB fill buffer fills the V-Itag array, the V-Itag in the original location is invalidated when the first flag data of the Cache block is filled, and the new address is filled into the V-Itag and is validated when the last flag data of the Cache block is filled.

5. The method for implementing the consistency of the instruction Cache based on the position corresponding relation as claimed in claim 1, wherein when a data error occurs, the instruction Cache management component sends a castout request to the secondary Cache management component, the secondary Cache management component invalidates the entry of the corresponding P-FB filling buffer, and then sends a response message to the instruction Cache management component; and after receiving the response information of the abandon request, the instruction Cache management part invalidates the corresponding entry of the V-FB filling buffer.

6. The method as claimed in claim 1, wherein in the filling process, when the secondary Cache management component receives a write-class request or an externally-invalid-class secondary request, querying a P-Itag array and a P-FB filling buffer according to physical addresses of the write-class request and the externally-invalid-class secondary request, when finding that there is a copy of the physical address in the P-Itag array or the P-FB filling buffer, invalidating a corresponding position of the P-Itag array or a corresponding entry of the P-FB filling buffer, and sending a position of the P-Itag array or an entry of the P-FB filling buffer as information to the instruction Cache management component.

7. The method of claim 6, wherein if the instruction Cache management component receives a secondary invalidation request with the entry of the P-FB fill buffer as information, the processing procedure is as follows:

if the content in the V-FB filling buffer is in the state of sending the abandon request and waiting for the response returned by the secondary Cache management part, not processing;

if the content in the V-FB filling buffer is in the state of sending the copy request and waiting for the response of the secondary Cache to return the management part, the V-FB filling buffer is not processed, and the corresponding copy in the V-Itag array is invalidated;

if the content in the V-FB filling buffer has already filled the instruction Cache, but has not sent the copy request, have not abandoned the request either, put the V-FB filling buffer invalid, put the corresponding duplicate in the V-Itag array invalid at the same time;

and if the contents in the V-FB filling buffer are not filled with the instruction Cache and no copy class request or abandon class request is sent, invalidating the V-FB filling buffer.

8. The method for implementing the consistency of the instruction Cache based on the position corresponding relation as claimed in claim 6, wherein if the instruction Cache management component receives the invalidation secondary request using the position of the P-Itag array as the information, the processing procedure is as follows:

if the position of the V-Itag array is not completely covered by the content in the V-FB filling buffer, namely the content in the V-FB filling buffer does not start filling or the filling instruction Cache is not finished, invalidating the content in the position of the V-Itag array;

if the contents of the V-FB fill buffer have completed filling the location of the V-Itag array, the invalidate secondary request is ignored.

Images