CN106774630A - A kind of compensation Direct Digital Frequency Synthesizers - Google Patents
A kind of compensation Direct Digital Frequency Synthesizers Download PDFInfo
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- CN106774630A CN106774630A CN201710034227.1A CN201710034227A CN106774630A CN 106774630 A CN106774630 A CN 106774630A CN 201710034227 A CN201710034227 A CN 201710034227A CN 106774630 A CN106774630 A CN 106774630A
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- phase
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- penalty coefficient
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
- G06F1/0328—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers in which the phase increment is adjustable, e.g. by using an adder-accumulator
Abstract
The invention provides a kind of compensation Direct Digital Frequency Synthesizers (DDS).The Direct Digital Frequency Synthesizers are compensated to phase truncation and amplitude quantization error.In addition to its phase accumulator in including traditional DDS, sine lookup table, digital analog converter and low pass filter, also include：Phase accumulator register, phase truncation penalty coefficient calculator, time delay alignment unit 1, phase truncation compensator, sine lookup errors table, adder, time delay alignment unit 2, amplitude quantization error penalty coefficient calculator, time delay alignment unit 3, amplitude quantization error compensator.These modules are mainly for generation of error signal, standard signal and align data, then calculate penalty coefficient, and then the data to sine lookup table output carry out linear processes compensation, are finally conveyed to digital analog converter.Present invention employs parallel open-loop compensation mode, the frequency switching time of DDS is not interfered with, can further reduce the output factors of DDS.
Description
Technical field
Closed the present invention relates to Digital Signal Processing, microelectronics technology, more particularly to a kind of Direct Digital frequency
Grow up to be a useful person.
Background technology
Direct digital synthesis technique (DDS) is that modern digital signal processing theory is combined and produces with microelectric technique
A kind of novel frequency synthetic technology.Obtained in the field such as frequency hopping and spread spectrum communication, linear frequency modulation, Doppler response simulation in recent years
Extensive use, and turned into the first-selection of frequency synthesis in the systems such as radar, electronic warfare, it is the third generation scheme of frequency synthesis.
The operation principle of DDS is the generation according to SIN function, from phase, different electricity is provided by different phases
Pressure amplitude degree, i.e. phase are converted to sine amplitude, are finally filtered, the frequency required for smoothing output.It is different from because DDS is employed
The numeric structure of legacy frequencies synthetic method, thus possess many direct-type and the spy not available for indirect frcquency synthetic technology
Point.
DDS mainly has following outstanding advantages：Advantage one, high frequency resolution.If the digit of phase accumulator isN, then output frequency can reach the 2 of system clock N / mono-, and current DDS chip phase accumulator digits reach 48,
With high frequency resolution；Advantage two, frequency error factor speed is fast.DDS is an open cycle system, feedback-less loop.Therefore
Its frequency switching time is only dependent upon the response time for putting yard control time and device.Current DDS can be pre- by multiple registers
Frequency control word is deposited, selects different frequencies to export by control code, depend primarily on the response time of device, it is general up to nanosecond
Magnitude；Advantage three, Phase Continuation characteristic.The change of DDS output frequencies is mainly by controlling phase-accumulated speed, in frequency
During agile, if not removing phase accumulation device, new frequency signal phase is directly added in original signal phase, maintains frequency
Phase continuity during rate agile., it is necessary to the Phase Continuation of frequency agility signal in many application systems, to avoid phase information
Loss and there is discrete frequency component, this in other frequency combining methods be difficult to realize.
But the structure of traditional DDS also determines its inevitable defect：Defect one, the spuious more difficult raising of index.By
In the limitation of current device technology and cost of manufacture, the phase in phase accumulator is often carried out into cut position, to save ROM appearances
Amount.Amplitude quantizing there is also error, and DAC cannot total Linearization.These can bring different degrees of spuious, be distributed in signal
It is more difficult to be suppressed by wave filter during frequency near-end；Defect two, highest output frequency receives DAC rate limits.
To sum up, though DDS has many advantages, also intrinsic some limitation, often combine the mixing of phaselocked loop in engineering
Formula frequency synthesis technique carries out complementation, but when system output bandwidth is wider, spuious index is more easy to deteriorate, and influences systematic function.
It is of the invention then be to employ parallel open-loop compensation mode to carry out linear processes to Phase Truncation Error and amplitude quantization error
Compensation, the advantages of do not interfere with the frequency switching time of DDS, can further reduce the output factors of DDS.
The content of the invention
The embodiment provides it is a kind of can open-loop compensation formula parallel Direct Digital Frequency Synthesizers, compensation system
Number according to output frequency self-adaptative adjustment, can further reduce the output factors of DDS.
Compensation Direct Digital Frequency Synthesizers structure and compensation method that embodiments of the invention are provided, except including passing
Outside phase accumulator, sine lookup table, digital analog converter and low pass filter in system DDS, also include：
Phase accumulator, sine lookup table, phase accumulator register；Phase truncation penalty coefficient calculator；Time delay alignment unit
1；Phase truncation compensator；Sine lookup errors table；Adder；Time delay alignment unit 2；Amplitude quantization error penalty coefficient is calculated
Device；Time delay alignment unit 3；Amplitude quantization error compensator uses same clock frequency, nth clock cycle, correspondence n-th group number
According to wherein n=0,1,2 ....It is primary data during n=0, all primary datas are 0 in addition to particular/special requirement.
The data bits of phase accumulator is N, then the storage bit number of phase accumulator register is also N, each of which
N data of clock output are standard signal X [n], and P high of phase accumulator used as sine lookup table ROM and sine lookup
The addressable address of errors table ROM.Low N-P of phase accumulator, i.e., block low N-P of two described ROM addressable address
Data, as the error signal e [n] of phase truncation.
Phase truncation penalty coefficient calculator, the mistake of standard signal X [n] and phase truncation according to phase accumulator register
Difference signal e [n] calculates the coefficient C of phase truncation compensatork[n], (k=1,2,3 ...).
Time delay alignment unit 1, for the second data flow of time delay sine lookup table output so that by the data after time delay
D [n] and phase truncation penalty coefficient Ck[n] align, its amount of delay be equal to phase truncation penalty coefficient calculator produced by when
The amount of prolonging, is the integral multiple of clock cycle.
Phase truncation compensator, the phase truncation penalty coefficient C according to the calculatingk[n] is to second after time delay alignment
Data flow carries out linear processes compensation.
Sine lookup errors table ROM, working frequency and memory capacity are just the same with sine lookup table ROM, but each is deposited
Storage unit stores the quantization error e of respective amplitude value’[n]。
Adder, is obtained by the data accumulation of sine lookup table ROM and sine lookup errors table ROM identical address units
Standard signal before three data flows, i.e. amplitude quantizing.
Time delay alignment unit 2, for the amplitude quantization error e that aligns’Standard signal X before [n] and amplitude quantizing’[n], its
Amount of delay is equal to the clock number needed for adder calculates the 3rd data flow, and the 3rd data flow after time delay before drawing amplitude quantizing
Standard signal X’[n]。
Amplitude quantizing penalty coefficient calculator, according to the 3rd data flow X after time delay alignment’[n] and quantization error e’[n]
Calculate amplitude quantization error penalty coefficient.
Time delay alignment unit 3, system is compensated for the data flow that alignment phase truncation and compensation device is produced with amplitude quantization error
Number；Its amount of delay is equal to the amount of delay of time delay alignment unit 1 and adds the amount of delay that phase truncation compensator is produced to subtract time delay alignment again
The amount of delay of unit 2.So that C’ kThe data D that [n] is produced with phase truncation compensator’[n] aligns.
Amplitude quantization error compensator, according to the amplitude quantization error penalty coefficient C after time delay alignment’ k[n], (k=1,2,
3 ...), the data to the output of phase truncation compensator further carry out linear processes compensation, finally by the data after compensation
D’’[n] is conveyed to digital analog converter.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, it is therefore apparent that describe below
In accompanying drawing be only some embodiments of the present invention, for one of ordinary skill in the art, do not paying creativeness
On the premise of work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of prior art Direct Digital Frequency Synthesizers.
Fig. 2 is the structural representation according to the compensation Direct Digital Frequency Synthesizers of the embodiment of the present invention.
Fig. 3 is that the phase accumulator register designed according to the embodiment of the present invention produces the standard signal X [n] before phase truncation
With error signal e [n] schematic diagram after phase truncation.
Fig. 4 is amplitude quantization error schematic diagram.
【Main element symbol description】101-phase accumulator register R；102-phase truncation penalty coefficient calculator；
103-time delay alignment unit 1；104-phase truncation compensator；105-sine lookup errors table ROM；106-adder；
107-time delay alignment unit 2；108-amplitude quantization error penalty coefficient calculator；109-time delay alignment unit 3；110-width
Metrization error compensator.
Specific embodiment
To make the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.It should be noted that in accompanying drawing or specification description, similar or identical part
All use identical figure number.The implementation for not illustrated in accompanying drawing or being described, is those of ordinary skill institute in art
The form known.
Fig. 1 is the structural representation of prior art Direct Digital Frequency Synthesizers；Fig. 2 is to be compensated according to the embodiment of the present invention
For the embodiment of the present invention increases module newly in the structural representation of formula Direct Digital Frequency Synthesizers, wherein dotted line frame.
Fig. 3 is the phase accumulator register R designed according to the embodiment of the present invention, its total N-bit data, whole N-bit
Data are to produce the standard signal X [n] before phase truncation, and P data high are sine lookup table ROM and sinusoidal error look-up table
The addressable address of ROM, low N-P data are the error signal e [n] after phase truncation.
Phase truncation penalty coefficient calculator computing formula is：Ck[n]=Ck[n-1]+uk×|X[n-1]|k×e[n-1]。
Wherein Ck[n] is nth clock kth rank phase truncation penalty coefficient, Ck[n-1] is that (n-1)th clock kth rank phase truncation is mended
Repay coefficient, ukFor the step-length that penalty coefficient updates, X [n-1] is (n-1)th standard signal of the phase accumulator register of clock, e
[n-1] is (n-1)th error information of the phase accumulator register of clock, k=1,2,3 ....Single order phase truncation penalty coefficient
Initial value C1[0] it is 1, the coefficient outside single order phase truncation penalty coefficient is 0.
Depending on phase truncation penalty coefficient exponent number is according to system index, if requiring that phase truncation is spuious lower, it is required that
Coefficient exponent number is higher, but the calculation resources for needing are also higher, can be balanced in system index and calculation resources.
Time delay alignment unit 1 is mainly the data delay amount for exporting sine lookup table ROM and is equal to phase truncation compensation system
Time delay produced by number calculator, gained phase truncation penalty coefficient Ck[n] acts on n-th in sine lookup table ROM just
In group data.
Phase truncation compensator to sine lookup table ROM output datas by time delay alignment unit 1 alignment after obtain n-th
Group data D [n] carries out linear processes compensation, and the formula of compensation is：D’[n]=C1[n]×D[n]+C2[n]×|D[n]|2+C3
[n]×|D[n] |3+ ..., wherein Section 1 is linear compensation, and other are nonlinear compensation.
Fig. 4 is amplitude quantization error schematic diagram.Amplitude quantization error is corresponding each phase in sine lookup table ROM
Amplitude subtract correspondence each phase standard sine amplitude value；These values can in advance be counted according to two look-up table memory capacity
Calculate good and store in amplitude quantization error table, nth clock amplitude quantization error e’[n] is represented.
The sine lookup table ROM of identical address unit is added approximate obtaining with sine lookup errors table ROM data by adder
Standard signal before to amplitude quantizing, nth clock amplitude quantizing standard signal x’[n] is represented.But because adder is present
Time delay, therefore added a time delay alignment unit 2 after adder, for the standard signal x before amplitude quantizing of aliging’[n] and by mistake
Difference signal e’[n]。
Amplitude quantization error penalty coefficient calculator computing formula is：C’ k[n]=C’ k[n-1]+u’ k×|X’[n-1]|k×e’
[n-1], wherein C’ k[n] is nth clock kth rank amplitude quantization error penalty coefficient, C’ k[n-1] is (n-1)th clock kth
Rank amplitude quantization error penalty coefficient, u’ kIt is the step-length that penalty coefficient updates, X’[n-1] is (n-1)th amplitude quantizing of clock
Preceding standard signal, e’[n-1]] it is (n-1)th amplitude quantization error data of clock, k=1,2,3 ....Single order amplitude quantizing
The initial value C of error compensation coefficient’ 1[0] it is 1, the coefficient outside single order metrization error compensation coefficient is 0.
Time delay alignment unit 3 is used for time delay amplitude quantization error penalty coefficient, and its amount of delay prolongs equal to time delay alignment unit 1
When the amount of delay that produces of amount plus phase truncation compensator subtract the amount of delay of time delay alignment unit 2 again.So that C’ k[n] cuts with phase
The data D that disconnected compensator is produced’[n] aligns.
The data D that amplitude quantization error compensator is exported to phase truncation compensator’[n] carries out linear processes benefit
Repay, compensation formula is：D’’[n]=C’ 1[n]×D’[n]+C’ 2[n]×|D’[n]|2+C’ 3[n]×|D’[n]|3+ ..., wherein first
Item is linear compensation, and other are nonlinear compensation；Finally by W data D’’[n] is transported to digital analog converter.
In sum, the invention provides a kind of parallel open-loop compensation formula Direct Digital frequency for being suitable for large-scale integrated
Synthesizer solution.The program makes full use of existing module in traditional DDS, has increased some simple modules newly and has produced standard signal
And error signal, penalty coefficient is calculated in an efficient way, and to the data between sine lookup table and digital analog converter
Phase truncation compensation and amplitude quantization error compensation are carried out, the output factors of DDS are reduce further.
Particular embodiments described above, should be understood that specific embodiment only of the invention, be not used to
The limitation present invention, all within spirit of the invention and principle, any modification, equivalent substitution and improvements done etc. are being included in
Within protection scope of the present invention.
Claims (10)
1. a kind of compensation Direct Digital Frequency Synthesizers, it is characterised in that except including traditional Direct Digital Frequency Synthesizers
In phase accumulator, sine lookup table ROM, outside digital analog converter DAC and low pass filter LPF, also include：
Phase accumulator register（101）, cut for generating the standard signal X [n] before the first data flow, i.e. phase truncation and phase
The error signal e [n] having no progeny；
Phase truncation penalty coefficient calculator (102), according to the coefficient C of the first data-flow computation phase truncation compensatork
[n], (k=1,2,3 ...)；
Time delay alignment unit 1（103）, for the phase truncation compensator coefficient C that alignsk[n] and sine lookup table produce the
Two data flows；
Phase truncation compensator（104）, the phase truncation penalty coefficient C according to the calculatingkThe second number after [n] time delay alignment
According to flowing into line and nonlinear compensation；
Sine lookup errors table ROM（105）, working frequency and memory capacity is just the same with sine lookup table ROM, but each is deposited
Storage unit stores the quantization error e of respective amplitude value’[n]；
Adder（106）, the data accumulation of sine lookup table ROM and sine lookup errors table ROM identical address units is obtained
3rd data flow；
Time delay alignment unit 2（107）, for the amplitude quantization error e that aligns’[n] and the 3rd data flow；
Amplitude quantization error penalty coefficient calculator（108）, according to the 3rd data flow X after time delay alignment’[n] and quantization error
e’[n] calculates amplitude quantization error penalty coefficient；
Time delay alignment unit 3（109）, system is compensated with amplitude quantization error for the data flow that alignment phase truncation and compensation device is produced
Number；
Amplitude quantization error compensator（110）, according to the amplitude quantization error penalty coefficient C after time delay alignment’ k[n], (k=1,2,
3 ...), the data to the output of phase truncation compensator further carry out linear processes compensation, finally by the data after compensation
It is conveyed to digital analog converter.
2. compensation Direct Digital Frequency Synthesizers according to claim 1, it is characterised in that phase accumulator, it is sinusoidal
Look-up table, phase accumulator register, phase truncation penalty coefficient calculator, time delay alignment unit 1, phase truncation compensator, just
String searches errors table, adder, time delay alignment unit 2, amplitude quantization error penalty coefficient calculator, time delay alignment unit 3, width
Metrization error compensator use same clock frequency, the nth clock cycle, correspondence n-th group of data, wherein n=0,1,2,
3 ...；During n=0, primary data is represented, all primary datas are 0 in addition to particular/special requirement.
3. according to claim 1, the compensation Direct Digital Frequency Synthesizers described in 2, it is characterised in that described phase-accumulated to post
The output data of storage is specifically included：
The data bits of phase accumulator is N, then the storage bit number of phase accumulator register is also N, each of which clock
N data of output are standard signal X [n], and P high of phase accumulator used as sine lookup table ROM and sine lookup error
The addressable address of table ROM；Low N-P of phase accumulator, i.e., the low N-P data that two described ROM addressable address are blocked,
As the error information e [n] of phase truncation.
4. data creating method according to claim 3, it is characterised in that phase truncation penalty coefficient calculator utilizes
One formula calculates phase truncation penalty coefficient, and the first described formula is specially：
Ck[n] = Ck[n-1]+uk×|X[n-1]|k×e[n-1]
Wherein Ck[n] is nth clock kth rank phase truncation penalty coefficient, Ck[n-1] is that (n-1)th clock kth rank phase is cut
Disconnected penalty coefficient, ukIt is the step-length that penalty coefficient updates, X [n-1] is (n-1)th standard letter of the phase accumulator register of clock
Number, e [n-1]] it is (n-1)th error information of the phase accumulator register of clock, k=1,2,3 ...；Single order phase truncation is mended
Repay the initial value C of coefficient1[0] it is 1, the coefficient outside single order phase truncation penalty coefficient is 0.
5. compensation Direct Digital Frequency Synthesizers according to claim Isosorbide-5-Nitrae, it is characterised in that time delay alignment unit 1
For the second data flow of time delay sine lookup table output so that by the data D [n] after time delay and phase truncation penalty coefficient
Ck[n] aligns, and its amount of delay is equal to the delay volume produced by phase truncation penalty coefficient calculator, is clock cycle integral multiple.
6. according to claim Isosorbide-5-Nitrae, the compensation Direct Digital Frequency Synthesizers described in 5, it is characterised in that phase truncation is compensated
Device carries out linear processes compensation and obtains output data D to described input data D [n] using the second formula’[n], it is described
The second formula be specially：
D’[n]=C1[n]×D[n]+C2[n]×|D[n] |2+C3[n]×|D[n] |3 + …。
7. compensation Direct Digital Frequency Synthesizers according to claim 1, it is characterised in that time delay alignment unit 2, its
Amount of delay is equal to the clock number needed for adder calculates the 3rd data flow, to the 3rd data flow by drawing amplitude after time delay
Standard signal X before quantization’[n]；Sine lookup errors table draws according to P high data of phase accumulator register as address
Amplitude quantization error data e’[n]。
8. data creating method according to claim 7, it is characterised in that amplitude quantization error penalty coefficient calculator profit
Amplitude quantization error penalty coefficient is calculated with the 3rd formula, the 3rd described formula is specially：
C’ k[n]=C’ k[n-1]+u’ k×|X’[n-1]|k×e’[n-1]
Wherein C’ k[n] is nth clock kth rank amplitude quantization error penalty coefficient, C’ k[n-1] is (n-1)th clock kth rank width
Metrization error compensation coefficient, u’ kIt is the step-length that penalty coefficient updates, X’Before [n-1] is (n-1)th amplitude quantizing of clock
Standard signal, e’[n-1] is (n-1)th amplitude quantization error data of clock, k=1,2,3 ...；Single order amplitude quantization error is mended
Repay the initial value C of coefficient’ 1[0] it is 1, the coefficient outside single order metrization error compensation coefficient is 0.
9. according to claim 1, the compensation Direct Digital Frequency Synthesizers described in 7,8, it is characterised in that time delay alignment unit
3 are used for time delay amplitude quantization error penalty coefficient, and its amount of delay adds phase truncation compensator equal to the amount of delay of time delay alignment unit 1
The amount of delay of generation subtracts the amount of delay of time delay alignment unit 2 again；So that C’ kThe data D that [n] is produced with phase truncation compensator’
[n] aligns.
10. according to claim 1, the compensation Direct Digital Frequency Synthesizers described in 7,8,9, it is characterised in that amplitude quantizing
Error compensator is to described input data D’[n] carries out linear processes compensation and draws its output data using the 4th formula
D’’[n], the 4th described formula is specially：
D’’[n]=C’ 1[n]×D’[n]+C’ 2[n]×|D’[n]|2+C’ 3[n]×|D’[n] |3+…。
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| CN109347504A (en) * | 2018-09-26 | 2019-02-15 | 西安烽火电子科技有限责任公司 | A kind of short-wave radio frequency digital processing system |
| CN114253343A (en) * | 2021-12-23 | 2022-03-29 | 中国航空工业集团公司西安航空计算技术研究所 | Arbitrary amplitude modulation subassembly |
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| CN114253343A (en) * | 2021-12-23 | 2022-03-29 | 中国航空工业集团公司西安航空计算技术研究所 | Arbitrary amplitude modulation subassembly |
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