CN106774627B - DDS frequency point tailing removing processing device and method - Google Patents
DDS frequency point tailing removing processing device and method Download PDFInfo
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Abstract
a DDS frequency point tailing removing processing device comprises a power divider, a program-controlled frequency divider, an FPGA, two DDSs, a main path low-pass filter, an auxiliary path low-pass filter, a frequency mixer and a switch filter; the DDS clock is connected with the input end of the power divider, the output end of the power divider is respectively connected with the DDS of the main circuit and the program-controlled frequency divider, the output end of the program-controlled frequency divider is connected with the DDS of the auxiliary circuit, the DDS of the main circuit is connected to the frequency mixer through the main circuit low-pass filter, the DDS of the auxiliary circuit is connected to the frequency mixer through the auxiliary circuit low-pass filter, the output end of the frequency mixer is connected to the switch filter, the FPGA is connected with the program-controlled frequency divider, the two DDS circuits and the switch filter, and the output end of the switch. The invention also discloses a DDS frequency point tailing removing processing method. Compared with the prior art, the invention has the following advantages: and the frequency mantissas of the two paths of DDS signals are offset, so that an accurate DDS frequency signal is obtained.
Description
Technical Field
The invention relates to a direct digital frequency synthesis (DDS) technology, in particular to a DDS frequency point tailing removing processing technology.
background
The DDS is essentially in phase accumulation in a digital domain, obtains a digital waveform by table look-up, and outputs the digital waveform through DA conversion, and the frequency relation between a DDS output signal f 0 and a clock f clk is
The DDS device has the advantages that the frequency control word of the DDS device is FTW, the frequency control word is 32 bits, the value range is 0-2 31 -1, the frequency control word number of the modern DDS device is large, so that the DDS output signal can have high precision, but in practical use, the DDS device is limited by the power-of-2 effect of the digital device, cannot generate any required accurate frequency and usually has small bits which cannot be eliminated, for example, the DDS frequency stepping precision of a 1GHz reference clock is below 0.233Hz, but cannot generate accurate 100MHz signals, namely f clk/7, f clk/9 and other fractional frequency signals, and the defect of the DDS restricts the application of the DDS device in some systems needing accurate timing.
Disclosure of Invention
The invention aims to provide a DDS frequency point tailing processing device and a DDS frequency point tailing processing method capable of generating required any accurate frequency signals.
The invention solves the technical problems through the following technical scheme: a DDS frequency point tailing removing processing device comprises a power divider, a program-controlled frequency divider, an FPGA, two DDSs, a main path low-pass filter, an auxiliary path low-pass filter, a frequency mixer and a switch filter;
The DDS clock is connected with the input end of the power divider, the output end of the power divider is respectively connected with the DDS of the main circuit and the program-controlled frequency divider, the output end of the program-controlled frequency divider is connected with the DDS of the auxiliary circuit, the DDS of the main circuit is connected to the frequency mixer through the main circuit low-pass filter, the DDS of the auxiliary circuit is connected to the frequency mixer through the auxiliary circuit low-pass filter, the output end of the frequency mixer is connected to the switch filter, the FPGA is connected with the program-controlled frequency divider, the two DDS circuits and the switch filter, and the output end of the switch.
the method for carrying out DDS frequency point tailing removal treatment by using the DDS frequency point tailing removal treatment device comprises the following steps:
firstly, setting parameters;
After the parameter setting is finished, the DDS clock signal is divided into two paths by the power divider, wherein the main path clock signal is directly sent to the input end of the DDS of the main path, the other path of the auxiliary path clock signal after frequency division by the programmable frequency divider is sent to the input end of the DDS of the auxiliary path, the output signal of the DDS of the main path is filtered by the low-pass filter and then is output to the mixer, the output signal of the DDS of the auxiliary path is filtered by the low-pass filter and then is output to the mixer, the frequency mantissa is removed from the mixer, and the mixing result is output by the switch filter;
the frequency relationship between the DDS output signal f 0 and the clock f clk is
Where FTW is the frequency control word for the DDS device.
The parameter setting includes:
Determining the frequency dividing ratio N of the programmable frequency divider according to the requirement; determining the main circuit clock frequency after passing through the power divider and the auxiliary circuit clock frequency after passing through the program-controlled frequency divider; determining a DDS frequency control word according to frequency setting, firstly determining a main path DDS frequency control word A by using an equation (2), and then determining a secondary path frequency control word B by using an equation (3); finally, selecting a proper switch filter channel;
B＝232-A·N (3)
Where f A is the main path frequency, A is the main path frequency control word, fs is the main path clock frequency, B is the auxiliary path frequency control word, both A and B can only take integers, and N is the division ratio of the programmable frequency divider.
Optimally, the frequency of the auxiliary road is set to be 28-35MHz, and the frequency of the main road is the target frequency +/-30 MHz.
Assuming that the main circuit clock frequency is fs and the frequency dividing ratio is N, the auxiliary circuit clock frequency is fs/N, and the output frequencies of the two DDSs are obtained according to the formula (1)
Wherein f A is main road frequency, A is main road frequency control word, f B is auxiliary road frequency, B is auxiliary road frequency control word, A and B can only take integer, two DDS signals are mixed, and output frequency is
In equation (6), AN ± B is a continuous integer, and there must be a suitable A, B, so that AN ± B is 2 32 and the output frequency is exactly fs/N.
The invention also discloses a method for carrying out DDS frequency point tailing removing treatment by adopting the DDS frequency point tailing removing treatment device, which comprises the following steps:
Firstly, setting parameters;
after parameter setting is finished, the DDS clock signal is divided into two paths through the power divider, wherein the main path clock signal is directly sent to the input end of the DDS of the main path, the other path of the auxiliary path clock signal after frequency division through the programmable frequency divider is sent to the input end of the DDS of the auxiliary path, the output signal of the DDS of the main path is filtered by the low-pass filter and then is output to the frequency mixer, the frequency mantissa is removed from the frequency mixer, and the frequency mixing result is output through the switch filter.
The parameter setting includes:
Determining the frequency dividing ratio N of the programmable frequency divider according to the requirement; determining the frequency of a main path clock after passing through the power divider and an auxiliary path clock after passing through the program-controlled frequency divider; determining a DDS frequency control word according to frequency setting, firstly determining a main path DDS frequency control word A by using an equation (2), and then determining a secondary path frequency control word B by using an equation (3); finally, selecting a proper switch filter channel;
B＝232-A·N (3)
where f A is the main path frequency, A is the main path frequency control word, fs is the main path clock, B is the auxiliary path frequency control word, both A and B can only take integers, and N is the frequency division ratio of the programmable frequency divider.
The frequency of the auxiliary road is set to be 28-35MHz, and the frequency of the main road is the target frequency +/-30 MHz.
Assuming that the main circuit clock is fs and the frequency dividing ratio is N, the auxiliary circuit clock is fs/N, and the output frequency of the two DDS paths is obtained according to the formula (1)
wherein f A is main road frequency, A is main road frequency control word, f B is auxiliary road frequency, B is auxiliary road frequency control word, A and B can only take integer, two DDS signals are mixed, and output frequency is
In equation (6), AN ± B is a continuous integer, and there must be a suitable A, B, so that AN ± B is 2 32 and the output frequency is exactly fs/N.
Compared with the prior art, the invention has the following advantages: and the frequency mantissas of the two paths of DDS signals are offset, so that an accurate DDS frequency signal is obtained. The DDS frequency point tailing removing processing technology can control the frequency dividing ratio N to obtain the accurate frequency of fs which is arbitrarily multiplied by a decimal number, and is a key technology in signal generation.
The frequency dividing ratio of the frequency divider in the DDS frequency point tailing removing technology can be adjusted according to needs, the accurate frequency of fs/3 can be obtained by 3 times of frequency dividing ratio, the accurate frequency of fs/5 can be obtained by 5 times of frequency dividing ratio, the accurate frequency of fs/7 can be obtained by 7 times of frequency dividing ratio, the accurate frequency of fs/9 can be obtained by 9 times of frequency dividing ratio, and the accurate frequency of fs/25 can be obtained by 25 times of frequency dividing ratio.
Drawings
fig. 1 is a schematic block diagram of a DDS frequency point tailing processing apparatus according to an embodiment of the present invention.
Detailed Description
The following examples are given for the detailed implementation and specific operation of the present invention, but the scope of the present invention is not limited to the following examples.
referring to fig. 1, the DDS frequency point tailing processing apparatus in the embodiment of the invention includes a power divider 1, a programmable frequency divider 2, an FPGA 3, two DDS4 paths, a main path low-pass filter 5, an auxiliary path low-pass filter 6, a mixer 7, and a switch filter 8.
The DDS clock is connected with the input end of the power divider 1, the output end of the power divider 1 is respectively connected with the DDS4 of the main circuit and the programmable frequency divider 2, the output end of the programmable frequency divider 2 is connected with the DDS4 of the auxiliary circuit, the DDS4 of the main circuit is connected with the frequency mixer 7 through the main circuit low-pass filter 5, the DDS4 of the auxiliary circuit is connected with the frequency mixer 7 through the auxiliary circuit low-pass filter 6, the output end of the frequency mixer 7 is connected with the switch filter 8, the FPGA 3 is connected with the programmable frequency divider 2, the two DDS4 circuits and the switch filter 8, and the output end of the switch filter 8 is used as the signal.
The method for carrying out DDS frequency point tailing removal treatment by using the DDS frequency point tailing removal treatment device comprises the following steps:
firstly, parameter setting is carried out, the frequency dividing ratio N of the program-controlled frequency divider 2 is determined according to requirements, the main road clock frequency after passing through the power divider 1 and the auxiliary road clock frequency after passing through the program-controlled frequency divider 2 are determined, the main road clock frequency and the auxiliary road clock frequency are convenient for frequency mixing and filtering, the auxiliary road frequency is generally set to be 28-35MHz, the main road frequency is target frequency +/-30 MHz, thus being beneficial to clutter suppression, the DDS frequency control word is determined according to the frequency setting, and the frequency relation between the DDS output signal f 0 and the clock f clk is that
Wherein FTW is a frequency control word of the DDS device;
Firstly, determining a main road DDS frequency control word A by using an equation (2), and then determining a secondary road frequency control word B by using an equation (3); finally, selecting a proper switch filter channel;
B＝232-A·N (3)
Wherein f A is the main road frequency, A is the main road frequency control word, fs is the main road clock frequency, B is the auxiliary road frequency control word, A and B can only take the integer, N is the frequency dividing ratio of the programmable frequency divider 2;
After parameter setting is finished, a DDS clock signal is divided into two paths by the power divider 1, wherein the main path clock signal is directly sent to the input end of the DDS4 of the main path, the other path of the auxiliary path clock signal after frequency division by the programmable frequency divider 2 is sent to the input end of the DDS4 of the auxiliary path, the signal is sent to the programmable frequency divider 2 to reduce the clock frequency and improve the frequency precision, the output signal of the DDS4 of the main path is filtered by the low-pass filter 5 and then output to the mixer 7, the output signal of the DDS4 of the auxiliary path is filtered by the low-pass filter 6 and then output to the mixer 7, frequency mantissas are removed in the mixer 7, and the mixing result is output by the switch filter.
Assuming the main clock frequency is fs and the divide ratio is N, the auxiliary clock frequency is fs/N. The output frequency of two DDSs can be obtained according to the formula (1)
Wherein f A is main road frequency, A is main road frequency control word, f B is auxiliary road frequency, B is auxiliary road frequency control word, A and B can only take integer
in equation (6), AN ± B is a continuous integer, and there must be a suitable A, B, so that AN ± B is 2 32 and the output frequency can be exactly fs/N.
And the frequency mantissas of the two DDS signals are offset, so that the accurate frequency is obtained. The DDS frequency point tailing removing processing technology can control the frequency dividing ratio N to obtain the accurate frequency of fs which is arbitrarily multiplied by a decimal number, and is a key technology in signal generation.
the frequency dividing ratio of the frequency divider in the DDS frequency point tailing removing technology can be adjusted according to needs, the accurate frequency of fs/3 can be obtained by 3 times of frequency dividing ratio, the accurate frequency of fs/5 can be obtained by 5 times of frequency dividing ratio, the accurate frequency of fs/7 can be obtained by 7 times of frequency dividing ratio, the accurate frequency of fs/9 can be obtained by 9 times of frequency dividing ratio, and the accurate frequency of fs/25 can be obtained by 25 times of frequency dividing ratio.
taking the main DDS clock as 1GHz and needing to generate accurate 1000/7MHz frequency as an example, N is 7. The master clock is about 113MHz and the slave clock is about 30 MHz. The main road frequency control word a is calculated according to the formula (2) and is 485331304, the auxiliary road frequency control word B is calculated according to the formula (3) and is 897648168, and A, B is substituted into the formula (6), so that: fo is 1000/7MHz, but the actual output frequencies of the two DDSs are 112.99999989569187164306640625MHz and 29.857142961450986MHz respectively. Because of the factor 7 in the denominator, the auxiliary frequency cannot be accurately described in a decimal way, but the accurate 1000/7MHz frequency can be obtained after mixing.
As a specific example, the model of the power divider (1) is LRPS-2-11J, and the manufacturer is Mini Circuits. The model of the programmable divider (2) is HMC394LP4E, and the manufacturer is Hittite. The FPGA (3) is EP3C10E144, and the manufacturer is Altera. DDS (4) model AD9858, manufacturer ADI. The low-pass filter (5) is built by LC, and the main index is the cut-off frequency of 400 MHz. The low-pass filter (6) is built by LC, and the main index is the cut-off frequency of 40 MHz. The mixer (7) is of the type ADE-1L and manufactured by Mini Circuits. The indexes of the switch filter (8) comprise 16 filters, the center frequency is 60-380 MHz, the stepping is 20MHz, the 3dB bandwidth is 20MHz, and the +/-30 MHz position is inhibited by 40 dB. Of course, one of ordinary skill in the art can readily select an appropriate device in accordance with the principles of the present invention.
the above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A DDS frequency point tailing removing processing device is characterized by comprising a power divider, a program-controlled frequency divider, an FPGA, two DDSs, a main path low-pass filter, an auxiliary path low-pass filter, a frequency mixer and a switch filter;
The DDS clock is connected with the input end of the power divider, the output end of the power divider is respectively connected with the DDS of the main circuit and the program-controlled frequency divider, the output end of the program-controlled frequency divider is connected with the DDS of the auxiliary circuit, the DDS of the main circuit is connected to the frequency mixer through the main circuit low-pass filter, the DDS of the auxiliary circuit is connected to the frequency mixer through the auxiliary circuit low-pass filter, the output end of the frequency mixer is connected to the switch filter, the FPGA is connected with the program-controlled frequency divider, the two DDS circuits and the switch filter, and the output end of the switch.
2. the DDS frequency point tailing removal device of claim 1, wherein the DDS frequency point tailing removal method using the DDS frequency point tailing removal device comprises the steps of:
firstly, setting parameters;
After the parameter setting is finished, the DDS clock signal is divided into two paths by the power divider, wherein the main path clock signal is directly sent to the input end of the DDS of the main path, the other path of the auxiliary path clock signal after frequency division by the programmable frequency divider is sent to the input end of the DDS of the auxiliary path, the output signal of the DDS of the main path is filtered by the low-pass filter and then is output to the mixer, the output signal of the DDS of the auxiliary path is filtered by the low-pass filter and then is output to the mixer, the frequency mantissa is removed from the mixer, and the mixing result is output by the switch filter;
The frequency relationship between the DDS output signal f 0 and the clock f clk is
where FTW is the frequency control word for the DDS device.
3. The DDS frequency point tailing removing device as claimed in claim 2, wherein the parameter setting comprises:
Determining the frequency dividing ratio N of the programmable frequency divider according to the requirement; determining the main circuit clock frequency after passing through the power divider and the auxiliary circuit clock frequency after passing through the program-controlled frequency divider; determining a DDS frequency control word according to frequency setting, firstly determining a main path DDS frequency control word A by using an equation (2), and then determining a secondary path frequency control word B by using an equation (3); finally, selecting a proper switch filter channel;
B＝232-A·N (3)
where f A is the main path frequency, A is the main path frequency control word, fs is the main path clock frequency, B is the auxiliary path frequency control word, both A and B can only take integers, and N is the division ratio of the programmable frequency divider.
4. The DDS frequency point tailing processing device according to claim 3, wherein the secondary frequency is set at 28-35MHz, and the primary frequency is the target frequency ± 30 MHz.
5. The DDS frequency point tailing removing device of claim 3, wherein assuming that the main circuit clock frequency is fs and the frequency dividing ratio is N, the auxiliary circuit clock frequency is fs/N, and the output frequency of two DDS paths is obtained according to the formula (1)
Wherein f A is main road frequency, A is main road frequency control word, f B is auxiliary road frequency, B is auxiliary road frequency control word, A and B can only take integer, two DDS signals are mixed, and output frequency is
in equation (6), AN ± B is a continuous integer, and there must be a suitable A, B, so that AN ± B is 2 32 and the output frequency is exactly fs/N.
6. The DDS frequency point tailing removing device of claim 1, wherein the model of the power divider is LRPS-2-11J, the model of the programmable frequency divider is HMC394LP4E, the model of the FPGA is EP3C10E144, and the model of the mixer is ADE-1L.
7. A method for performing DDS frequency point tailing removal processing by using the DDS frequency point tailing removal processing apparatus in claim 2, comprising the steps of:
Firstly, setting parameters;
After parameter setting is finished, the DDS clock signal is divided into two paths through the power divider, wherein the main path clock signal is directly sent to the input end of the DDS of the main path, the other path of the auxiliary path clock signal after frequency division through the programmable frequency divider is sent to the input end of the DDS of the auxiliary path, the output signal of the DDS of the main path is filtered by the low-pass filter and then is output to the frequency mixer, the frequency mantissa is removed from the frequency mixer, and the frequency mixing result is output through the switch filter.
8. The DDS frequency point tailing removing method of claim 7, wherein the setting of the parameters includes:
determining the frequency dividing ratio N of the programmable frequency divider according to the requirement; determining the frequency of a main path clock after passing through the power divider and an auxiliary path clock after passing through the program-controlled frequency divider; determining a DDS frequency control word according to frequency setting, firstly determining a main path DDS frequency control word A by using an equation (2), and then determining a secondary path frequency control word B by using an equation (3); finally, selecting a proper switch filter channel;
B＝232-A·N (3)
Where f A is the main path frequency, A is the main path frequency control word, fs is the main path clock, B is the auxiliary path frequency control word, both A and B can only take integers, and N is the frequency division ratio of the programmable frequency divider.
9. the DDS frequency point tailing processing method of claim 7, wherein the secondary road frequency is set at 28-35MHz, and the primary road frequency is the target frequency ± 30 MHz.
10. The DDS frequency point tailing removing method of claim 7, wherein assuming the main clock is fs and the frequency dividing ratio is N, the auxiliary clock is fs/N, and the output frequency of two DDS paths is obtained according to the formula (1)
Wherein f A is main road frequency, A is main road frequency control word, f B is auxiliary road frequency, B is auxiliary road frequency control word, A and B can only take integer, two DDS signals are mixed, and output frequency is
in equation (6), AN ± B is a continuous integer, and there must be a suitable A, B, so that AN ± B is 2 32 and the output frequency is exactly fs/N.
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