CN106772484B - Adjustment method of power ratio and carrier phase relationship among multiple components of satellite navigation signal - Google Patents

Abstract

The method of adjusting the power ratio and carrier phase relationship among multiple components of the satellite navigation signal, first generates a constant envelope lookup table and injects it into the satellite signal generation load, and then controls the navigation signal generation load to use a triple-mode redundant receiver with a feedback branch The latch circuit receives and stores the constant envelope lookup table, puts the constant envelope lookup table into FPGA internal Slice, and finally controls the navigation signal generation load to use the constant envelope lookup table to generate the navigation signal. The present invention solves the problem of correction after single-event reversal by performing triple-mode redundancy design on the circuit with feedback branch. When the constant envelope lookup table is corrected due to single-event reversal, the single-event reversal will not accumulate. It ensures the stable and continuous broadcast of navigation signals.

Description

Adjustment method of power ratio and carrier phase relationship among multiple components of satellite navigation signal

technical field

The invention relates to satellite navigation technology, in particular to a method for adjusting the power ratio among multiple components of satellite navigation signals and the carrier phase relationship.

Background technique

There are multiple signal components in a single frequency point of the satellite navigation signal. During the generation process of the satellite navigation signal, multiple signal components are synthesized into an orthogonal complex signal through a fixed constant envelope lookup table, and then navigation is realized by orthogonal modulation. Signal generation, this method has the following disadvantages:

(1) Multiple signal components are combined into one signal through a fixed constant envelope lookup table, and the power ratio between signal components and the adjustment of the carrier phase relationship cannot be realized;

(2) The fixed constant-envelope lookup table is vulnerable to the flipping of spatial single events. The lookup table is a single point in the generation of navigation signals. Once the lookup table is overturned by a single event, errors will occur in the generation of downlink navigation signals, resulting in the failure of navigation service functions. Interruption, this problem can be solved by three-mode redundancy, but the general three-mode design method is used to strengthen the key registers, and the error correction function cannot be realized, resulting in the accumulation of single event flips in the constant envelope lookup table. When a certain bit Guidance signal generation is erroneous when a two-digit single event flip error is accumulated.

Contents of the invention

The technical problem solved by the present invention is to overcome the deficiencies of the prior art, provide a method for adjusting the power ratio and carrier phase relationship between multiple components of satellite navigation signals, and solve the problem that the power ratio and carrier phase relationship between signal components cannot be realized. Adjustment, when more than two single-event flip errors occur in a certain bit accumulation, the navigation signal generation error problem can be flexibly adjusted The power ratio and carrier phase relationship between multiple signal components of the navigation signal has high reliability and is not easy Advantage of being affected by single event flips.

The technical solution of the present invention is: a method for adjusting the power ratio between multiple components of satellite navigation signals and the carrier phase relationship, comprising the following steps:

(1) Generate a constant envelope lookup table on the ground; the constant envelope lookup table includes power ratios and carrier phases between all components of the satellite navigation signal, and can be generated according to multiple signal components that exist at a single frequency point of the satellite navigation signal One path of orthogonal complex signals, and perform quadrature modulation to obtain navigation signals;

(2) Add the constant envelope lookup table to the navigation signal generation load, control the navigation signal generation load to receive and store the constant envelope lookup table using a triple-mode redundant receiving latch circuit with a feedback branch, and then transfer the constant envelope The network look-up table is put into FPGA internal Slice; The described three-mode redundant receiving latch circuit with the feedback branch is the triple-mode redundant design of the receiving latch circuit with the feedback branch, realizing the constant envelope search The three-mode judgment result of the table is fed back to the input end of the three-mode redundant receiving latch circuit with a feedback branch, and the constant-envelope look-up table is used to correct the input signal constant-envelope look-up table using the three-mode judgment result; the receiving The latch circuit is implemented through the D flip-flop and LUT inside the FPGA to realize the receiving function of the constant envelope look-up table;

(3) Control the navigation signal generation load and use the constant envelope lookup table to generate the navigation signal;

(4) When it is necessary to change the power ratio and carrier phase between satellite navigation signal components, a new constant envelope lookup table is generated and injected into the satellite signal generation load, and then turn to step (2).

The method of the receiving latch circuit with a feedback branch includes the following steps:

(1) Find out all flip-flops of the receiving latch circuit;

(2) Disconnect the setting gate of the trigger of the receiving latch circuit, and then connect the setting port to a low level;

(3) Connect the output signal of the D flip-flop to the input port of the LUT in the FPGA to implement CPU placement;

(4) Modify the truth table of the LUT until when the control signal written into the FPGA is valid and the address is correct, the LUT output is a signal placed on the ground. When the control signal written into the FPGA is invalid or the address is incorrect, the LUT output is Input the level of port 1, and then connect the LUT output port to the input port of the D flip-flop.

The three-mode redundant receiving latch circuit with feedback branch adopts TMRTool tool.

The advantage of the present invention compared with prior art is:

(1) The present invention allows the ground to change the content of the lookup table by injecting command parameters without interrupting the satellite navigation signal by adding an injection interface in the constant envelope lookup table, which solves the problem that the ground control system cannot change the navigation satellite The problem of the constant envelope lookup table realizes the flexible adjustment of the power ratio and carrier phase relationship between multiple signal components;

(2) The present invention solves the correction problem after the single event flipping by carrying out the three-mode redundant design to the circuit with the feedback branch, when the constant envelope lookup table can be corrected because of the single event flipping, the single event flipping does not It will accumulate to ensure the stable and continuous broadcast of navigation signals.

Description of drawings

Fig. 1 is a schematic flow chart of a method for adjusting the power ratio and carrier phase relationship between multiple components of a satellite navigation signal of the present invention;

Fig. 2 is the FPGA receiving and storing circuit of common constant envelope look-up table;

Fig. 3 is the full three-mode redundant design of the FPGA receiving and storage circuit of common constant envelope look-up table;

Fig. 4 is the part triple-mode redundant design of the FPGA receiving and storing circuit of common constant envelope look-up table;

Fig. 5 is the FPGA reception and storage circuit with the constant envelope look-up table of feedback branch;

Fig. 6 is the full three-mode or part three-mode redundant design circuit of the FPGA receiving and storage circuit with the constant envelope look-up table of the feedback branch.

Detailed ways

The present invention overcomes the deficiencies in the prior art, and proposes a method for adjusting the power ratio and carrier phase relationship between multiple components of satellite navigation signals, which solves the problem that the adjustment of the power ratio and carrier phase relationship between signal components cannot be realized. When there are more than two single-event flip errors accumulated, the navigation signal generation error problem can flexibly adjust the power ratio and carrier phase relationship between multiple signal components of the navigation signal, which has high reliability and is not easily affected by single-event flip Advantages, the method of the present invention will be described below in conjunction with the accompanying drawings.

As shown in Figure 1, it is a flow chart of the method for adjusting the power ratio between multiple components of satellite navigation signals and the carrier phase relationship disclosed by the present invention, including the following steps:

(1) A constant envelope lookup table is pre-stored in the navigation signal generation load to realize the multiplexing of multiple signal components of the navigation signal. Assuming that the number of signal components in the inventive method is N, then the number of rows of the constant envelope look-up table is 2 ^N rows, and the column number is 1 column; the level of each signal component is +1 or -1, so each Signal components can be represented by 1bit binary numbers; N signal components can be represented by N binary numbers; at a certain moment, each signal component is a certain fixed state (+1 or -1), composed of N signal components The binary number of is any number between m=0～ ^2N -1, and this number corresponds to the content of the mth row and the first column in the constant envelope lookup table. The constant envelope lookup table takes the power ratio between signal components and the carrier phase relationship as input conditions, and uses mature technology, such as the POCET algorithm, to generate a table with 2 ^N rows and 1 column.

(2) If the ground user needs to change the carrier phase relationship and power ratio of multiple signal components, generate a new constant envelope lookup table, and use the ground control system to inject the new constant envelope lookup table into the navigation satellite;

(3) The navigation signal generation load receives a new look-up table and puts it into the FPGA in order.

(4) After the FPGA receives the constant envelope lookup table, store it in the slice inside the FPGA, and design a circuit with a feedback branch to realize the reception and storage of the constant envelope lookup table.

(5) Partial triple-mode redundant design is carried out to the above-mentioned circuit with the feedback branch; the triple-mode redundant design process in the method of the present invention is realized by using a TMRTool tool.

(6) Check whether the three-mode judgment result is fed back to the input terminal by designing a circuit to ensure that the three-mode judgment result corrects the input signal, and realizes the correction of 1-bit single event flip.

(7) The ground-injected lookup table replaces the original lookup table to realize the constant envelope modulation of the navigation signal.

The realization method of the circuit with feedback branch in step (4), comprises the steps:

(1) The constant envelope look-up table injected into the ground is received by the CPU of the navigation satellite payload, and then the content of the look-up table is forwarded to the FPGA;

(2) FPGA realizes the circuit that receives constant envelope look-up table data from CPU;

(3) Find out all flip-flops in this part of the circuit;

(4) Fig. 2 shows the FPGA receiving and storing circuit of common constant envelope lookup table, this circuit can realize the function of receiving the constant envelope lookup table injected from the ground, carry out full three-mode redundancy design to this part of the circuit, get as follows The circuit shown in Figure 3, as shown in Figure 3, is the full triple-mode redundant design of the FPGA receiving and storage circuit of the common constant envelope look-up table; the partial triple-mode redundant design is carried out to this part of the circuit, and it is obtained as shown in Figure 4 As shown in Figure 4, it is a part of the triple-mode redundant design of the FPGA receiving and storage circuit of the common constant envelope look-up table; it can be seen that the triple-mode redundant design shown in Figure 3 and Figure 4 only searches for the LUT The meter circuit and the D trigger circuit have been designed with triple-mode redundancy, and there is no feedback correction function. If a single event flip occurs, it will lead to the accumulation of error bits over time.

(5) Disconnect the set gate of the flip-flop, and then connect the set port to low level.

(6) Connect the output signal of the D flip-flop to the input port 1 of the LUT inside the FPGA, and use the feedback loop to realize the CPU insertion function. As shown in Figure 5, the FPGA receiving the constant envelope look-up table with the feedback branch and memory circuits.

(7) Modify the content of the truth table of the LUT to achieve the following functions:

If the control signal written by the CPU to the FPGA is valid and the address is correct, the LUT output is a signal placed on the ground; if the control signal written by the CPU to the FPGA is invalid or the address is incorrect, the LUT output is the level of the input port 1.

(8) Connect the LUT output to the input of the D flip-flop.

As shown in Fig. 2, it is the FPGA receiving and storing circuit of common constant envelope look-up table, carries out full three-mode redundancy design to this circuit, obtains the circuit as shown in Fig. 3, carries out partial three-mode redundancy design to this circuit, Get the circuit shown in Figure 4. Although Figure 3 and Figure 4 have carried out the triple-mode redundancy design, because there is no feedback loop, the correction of single event flipping cannot be realized. Figure 6 shows the FPGA reception and storage of the constant envelope look-up table with the feedback branch Full three-mode or part of the three-mode redundant design circuit of the circuit, because there is a feedback loop in Figure 6, there is still a feedback loop after the three-mode redundancy, which can realize the correction of single event flipping. It can be seen that whether it is a full three-mode redundant design or a partial three-mode redundant design method, the error correction function cannot be realized by strengthening the key registers, resulting in the accumulation of single event flips in the constant envelope lookup table. When a certain When a bit accumulates a two-bit single-event flip error, the navigation signal generation generates an error.

Figure 5 shows the FPGA receiving and storage circuit with a constant envelope look-up table of the feedback branch. The circuit is designed with full triple-mode redundancy or partial triple-mode redundancy to obtain the circuit shown in Figure 6. It can be seen that the circuit feeds back the output result after triple redundancy to the input terminal, corrects the single event upset fault at the input end, and ensures that the single event upset will not accumulate over time.

The content that is not described in detail in the description of the present invention belongs to the well-known technology of those skilled in the art.

Claims (3)

1. power ratio and carrier phase relationship method of adjustment between satellite navigation signals multi -components, it is characterised in that including walking as follows It is rapid:

(1) permanent envelope look-up table is generated on ground；The permanent envelope look-up table include satellite navigation signals important Power ratio and carrier phase, multiple signal components according to existing for satellite navigation signals single frequency point generate orthogonal all the way Complex signal, and carry out orthogonal modulation and obtain navigation signal；

(2) note on permanent envelope look-up table to navigation signal is generated into load, control navigation signal generates load and uses with feedback The triplication redundancy of branch receives latch cicuit and receives and stores permanent envelope look-up table, and then permanent envelope look-up table is placed in FPGA Portion Slice；It is the reception latch cicuit with feedback branch that the triplication redundancy with feedback branch, which receives latch cicuit, Triplication redundancy design, realize by permanent three mould court verdict of envelope look-up table feed back to the triplication redundancy with feedback branch receive The input terminal of latch cicuit is corrected input signal perseverance envelope look-up table using permanent three mould court verdict of envelope look-up table； The latch cicuit that receives is to be realized by d type flip flop, the LUT inside FPGA, realizes the reception function to permanent envelope look-up table Energy；

(3) control navigation signal generates load and generates navigation signal using permanent envelope look-up table；

(4) it when needing to change the power ratio and carrier phase between satellite navigation signals component, generates new permanent envelope and searches Table and it is upper note to satellite-signal generate load, be then transferred to step (2).

2. power ratio and carrier phase relationship method of adjustment between satellite navigation signals multi -components according to claim 1, It is characterized by: the implementation method of the reception latch cicuit with feedback branch includes the following steps:

(1) it finds out and receives all triggers of latch cicuit；

(2) the set port for receiving latch cicuit trigger is disconnected, set port is then connected into low level；

(3) output signal of d type flip flop is connect to the input port of LUT in FPGA, realizes CPU merging；

(4) truth table of LUT is modified, until LUT output is ground when the control signal that FPGA is written is effective and address is correct The signal of merging, when the control invalidating signal or incorrect address that FPGA is written, the electricity for the input port that LUT output is LUT It is flat, then LUT output port is connect to the input port of d type flip flop.

3. power ratio and carrier phase relationship adjustment side between satellite navigation signals multi -components according to claim 1 or 2 Method, it is characterised in that: the triplication redundancy with feedback branch receives latch cicuit and uses TMRTool tool.