CN106712307B - Dynamic time delay sequential closing system and method for avoiding damage to circuit breaker by bias current - Google Patents
Dynamic time delay sequential closing system and method for avoiding damage to circuit breaker by bias current Download PDFInfo
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- CN106712307B CN106712307B CN201710176208.2A CN201710176208A CN106712307B CN 106712307 B CN106712307 B CN 106712307B CN 201710176208 A CN201710176208 A CN 201710176208A CN 106712307 B CN106712307 B CN 106712307B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J13/00—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
- H02J13/00006—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment
- H02J13/00019—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment using optical means
Abstract
The invention relates to a dynamic time delay sequence switching-on system and a method for avoiding damage to a circuit breaker by bias current, wherein the dynamic time delay sequence switching-on system comprises a dynamic time delay sequence switching-on device, a bus voltage transformer for respectively inducing bus three-phase voltages, a line voltage transformer for respectively inducing line three-phase voltages, a line current transformer for inducing line three-phase currents and a circuit breaker mechanism; the dynamic time delay sequential switching-on device comprises a power supply, a CPU system, an A/D sampling module, a photoelectric isolator, an alternating current converter and a solid-state relay.
Description
Technical Field
The invention relates to a dynamic time delay sequential switching-on system and a method for avoiding damage to a breaker by bias current.
Background
In order to solve the problems of overvoltage and capacitive reactive unbalance generated by long-distance line distributed capacitance in a 500kV and above voltage class power grid transmission line, a reactor needs to be connected in parallel at one side or two sides of the line. With the development of the power grid and the engineering reconstruction and extension, after the original line break is connected to a new transformer substation, the originally configured reactor forms 'overcompensation' for the new short circuit, namely the capacity of the reactor exceeds the capacity of the distributed capacitance of the new short circuit. Therefore, in the process of transmitting power from one side or operating and closing a new line, the inductive current cannot be suddenly changed, and the non-periodic component current causes the charging current of the line to be unable to cross the zero point, namely the bias current, for a long time. If a circuit has one-phase or two-phase short circuit fault in the power transmission process, the circuit relay protection will instantaneously act on the three-phase tripping of the circuit breaker, and because the bias current of the non-fault phase is not zero, the circuit breaker trips, but the arc extinguishing chamber of the circuit breaker with the fault phase cannot extinguish, so that the contact of the circuit breaker is extremely likely to be damaged, even the circuit breaker explodes, and the safe operation of a power grid is threatened.
The traditional breaker switching-on mode is that three phases are switched on at random and simultaneously, the switching-on is performed on a line fault, relay protection is fast to act to drop the switching-on, and the direct current bias problem of a non-fault phase cannot be avoided. If the reactor is changed from the line to the bus, or the breaker is replaced by a resistor with closing, the equipment and construction cost are huge.
Disclosure of Invention
According to the method, the angle of the circuit breaker control switching-on loop is determined, and when the circuit bias current is attenuated to a zero crossing point or after preset time delay, the three-phase circuit breaker is sequentially controlled to be switched on, so that the bias current is avoided. The safety risk of the circuit breaker for switching off the bias current is scientifically and economically avoided. The technical problems to be solved in detail and the advantages to be achieved are described in detail below and in conjunction with the detailed description.
In order to solve the problems, the invention adopts the following technical scheme:
by adopting a dynamic time-delay split-phase sequential closing control method, the A, B, C phase circuit breaker is sequentially subjected to closing control: according to a dynamic time delay sequence switching-on system and a method for avoiding damage to a breaker by bias current, firstly, a phase A breaker is controlled to switch on according to a preset voltage phase angle, and after the dynamic time delay sequence switching-on system and the method for avoiding damage to the breaker by bias current judge that the phase A current decays to a zero crossing point, or after the set time delay is reached, a phase B breaker is controlled to switch on. And similarly, after judging that the B phase current crosses the zero point or reaches the set time delay, controlling the C phase switching on and off. The sequential switching-on strategy is switched on according to an optimized phase angle as far as possible, so that the occurrence of bias current is avoided as much as possible, and the zero crossing point judgment of the current of the switching-on phase and the specified time delay judgment are added. Therefore, once the switching-on operation is performed on a certain phase fault of a circuit and the relay protection operation trips, the bias current of the first switching-on phase has zero crossing, the fault current of the fault phase has zero crossing very fast, and the risk that the current of the certain phase does not cross zero and the circuit breaker does not quench the arc does not exist at the tripping moment of the circuit breaker.
The dynamic time-delay split-phase sequential switching-on device inputs a switching-on command of the measurement and control device and outputs three split-phase switching-on commands. And introducing bus three-phase voltage quantity and line three-phase voltage quantity, line three-phase current quantity and three-phase breaker position state quantity. And selecting a closing phase angle according to the three-phase bus voltage, and judging a breaker which is closed after zero crossing of the current of the first closing phase and then closing the following phase by adopting the three-phase current of the circuit. The dynamic delay current distinguishing and sequential closing functions are realized.
The beneficial effects of adopting above-mentioned technical scheme to produce lie in:
the method for avoiding damage to the circuit breaker by the bias current by dynamic time delay sequential switching-on is suitable for sequential switching-on control of the split-phase high-voltage circuit breaker. The popularization and application of the method have obvious economic benefits. Taking 500kV transmission line engineering as an example, if a scheme of moving a reactor from a line to a bus is adopted, additional equipment such as a breaker, a transformer, an isolating switch and the like needs to be purchased, and the investment is about 600 ten thousand yuan; by adopting the dynamic time delay sequential closing control scheme, only 4 sets of control devices are needed to be purchased, and the investment is only 60 ten thousand yuan. Saving the engineering investment by 540 ten thousand.
Compared with the control circuit relay protection delay tripping, the dynamic delay sequence switching-on device has the following differences and advantages:
1. the time delay sequential switching-on is to respectively and sequentially control the switching-on time of the circuit breaker; the circuit relay protection delay tripping is the time for controlling the tripping of the circuit breaker by split phases;
2. the delay sequence closing is safer than a delay tripping control strategy. In actual operation of the power grid, the newly-built line transmits power or recovers power transmission after line maintenance, the risk of latent faults on the line is high, relay protection is required to be fast and free of delay tripping and fault removal when power is transmitted to the fault line, stability of the power grid can be guaranteed, and the power failure range is prevented from being enlarged. If the delay closing strategy fails accidentally, repeated operation can be tried again, and the safe operation of the power grid is not affected. The delay tripping overtakes the existing mature relay protection rapid delay-free tripping function, if the relay protection of the circuit is misplaced for fault phase, uncertain delay fault removal can be caused, the stability of a power grid is threatened, and the power failure area is enlarged.
The advantages of the present invention are not limited to this description, but are described in more detail in the detailed description section for better understanding.
Drawings
Fig. 1 is a control block diagram of the present invention.
Fig. 2 is a flow chart of the operation of the present invention.
Fig. 3 is a schematic diagram of a bias current decay process.
Detailed Description
1-3, a dynamic time delay sequential closing system comprises a dynamic time delay sequential closing device, a bus voltage transformer for respectively inducing bus three-phase voltages, a line voltage transformer for respectively inducing line three-phase voltages, a line current transformer for inducing line three-phase currents and a circuit breaker mechanism;
the dynamic time delay sequential switching-on device comprises a power supply, a CPU system, an A/D sampling module, a photoelectric isolator, an alternating current converter and a solid-state relay;
the power supply is used for providing electric energy for the CPU system, the CPU system is electrically connected with the photoelectric isolator, the secondary coil of the line current transformer is electrically connected with the input end of the A/D sampling module, and the output end of the A/D sampling module is electrically connected with the input end of the CPU system;
the circuit breaker mechanism comprises an A-phase circuit breaker, a B-phase circuit breaker and a C-phase circuit breaker which are controlled independently, wherein an A-phase bus is connected with an A-phase circuit through the A-phase circuit breaker, a B-phase bus is connected with a B-phase circuit through the B-phase circuit breaker, and a C-phase bus is connected with a C-phase circuit through the C-phase circuit breaker;
the photoelectric isolator converts the opening and closing position state information of the A-phase circuit breaker, the B-phase circuit breaker and the C-phase circuit breaker into high and low level information respectively and transmits the high and low level information to the CPU system; the CPU system respectively controls the closing of the A-phase circuit breaker, the B-phase circuit breaker and the C-phase circuit breaker through the solid-state relay;
the line current transformer comprises an A-phase current transformer for inducing an A-phase line current, a B-phase current transformer for inducing a B-phase line current and a C-phase current transformer for inducing a C-phase line current;
the secondary coil of the bus voltage transformer and the secondary coil of the line voltage transformer are respectively and electrically connected with the input end of the alternating current converter, and the output end of the alternating current converter is electrically connected with the input end of the A/D sampling module. Thus, the phase angle of the closing can be accurately determined.
Further, the system also comprises a measurement and control device for sending a closing command to the CPU system through the photoelectric isolator. The measurement and control device is a common device such as a silicon controlled rectifier or an intermediate relay.
A method for avoiding damage to a circuit breaker by a bias current, by means of the dynamic time delay sequential closing system described above, comprising the steps of:
step a: firstly, a measurement and control device sends a closing command to a CPU system through a photoelectric isolator; next, the photo-isolator transmits the open/close state information of the circuit breaker mechanism to the CPU system, and when the circuit breakers of the circuit breaker mechanism are all in the open state, step b is performed.
Step b, firstly, respectively sensing three-phase voltages of a line by a line voltage transformer, and respectively transmitting the three-phase voltages of the line to an A/D sampling module by the line voltage transformer; secondly, the A/D sampling module carries out analog-to-digital conversion on the signal and transmits the signal to the CPU system; thirdly, the CPU system judges the received voltage, and when the voltage exists in the three phases of the circuit, the CPU system controls the A-phase circuit breaker, the B-phase circuit breaker and the C-phase circuit breaker of the circuit breaker mechanism to be directly switched on at the same time; c, when the three phases of the line have no voltage, performing the step;
as a person skilled in the art can obviously know, when the voltages of three phases of the circuit are all not normal, the circuit is not electrified, and the power transmission switching-on logic, namely the split-phase sequential switching-on, is to be executed; when the three-phase voltages of the circuit have normal voltages, the circuit is electrified from the breaker on the other side, and the logic of closing the circuit is to be executed and is to be directly closed.
Step C, firstly, setting a switching-on sequence to be an A-phase circuit breaker, a B-phase circuit breaker and a C-phase circuit breaker by people, wherein three paths of switching-on can be set in sequence; secondly, the CPU system controls the switching-on of the A-phase breaker through the solid-state relay;
step d: the phase A zero crossing judgment, wherein the phase A current transformer transmits the induced phase A line current information to the CPU system through the A/D sampling module, and the CPU system carries out zero judgment; if no zero point exists, the CPU system continues to carry out current zero crossing judgment on the phase A line current within the preset delay time, and when the phase A line current crosses zero or reaches the preset time, the step e is executed;
step e: the CPU system controls the B-phase breaker to be switched on through the solid-state relay;
step f: b phase zero crossing judgment, the B phase current transformer transmits the induced B phase line current information to a CPU system through an A/D sampling module, and the CPU system carries out zero point judgment; if no zero point exists, the CPU system continues to carry out current zero crossing judgment on the B-phase line current within the preset delay time, and when the B-phase line current crosses zero or reaches the preset time, the step g is executed;
step g: the CPU system controls the C-phase breaker to be switched on through the solid-state relay;
step h: c phase zero crossing judgment, the C phase current transformer transmits the induced C phase line current information to a CPU system through an A/D sampling module, and the CPU system carries out zero point judgment; if no zero point exists, the CPU system continues to carry out current zero crossing judgment on the C-phase line current within the preset delay time, and when the C-phase line current crosses zero or reaches the preset time, the step j is executed;
step j; the photoelectric isolator transmits the position state information of the A-phase circuit breaker, the B-phase circuit breaker and the C-phase circuit breaker to the CPU system, the CPU system judges that the A-phase circuit breaker, the B-phase circuit breaker and the C-phase circuit breaker are at the closing position and/or the line current transformer transmits the current information of the line three phases to the CPU system through the A/D sampling module, the CPU system judges that the line three phases have current, and the CPU system returns to lock the non-full-phase protection signal, and execution is finished.
Further, when the step c is executed, the bus voltage transformer respectively selects an A-phase bus on three phases of the bus as a reference voltage, and the CPU system controls the A-phase circuit breaker to be closed according to a preset A-phase voltage phase angle;
further, while executing the step e, the bus voltage transformer respectively selects a B-phase bus on three phases of the bus as a reference voltage, and the CPU system controls the B-phase breaker to be closed according to a preset B-phase voltage phase angle;
further, while executing step g, the bus voltage transformer respectively selects a C-phase bus on three phases of the bus as a reference voltage, and the CPU system controls the C-phase breaker to be closed according to a preset C-phase voltage phase angle.
Further, after performing step c and before step d, step β: the CPU system outputs a locking non-full-phase protection signal to the circuit breaker mechanism through the solid relay to control the non-full-phase protection in the circuit breaker mechanism to exit; non-full phase protection is also called three-phase inconsistent protection.
Further, after step beta and before step d, when the A-phase switching-on and switching-off fails, the A-phase breaker is tripped, the non-full-phase protection signal is reset and blocked, and the step b is re-executed; when the phase A switching-on is normal, executing the step d;
further, after the step e and before the step f, when the B-phase switching-on and switching-off fails, the B-phase breaker bounces off the reset lockout non-full-phase protection signal, and returns to execute the step B again; and when the phase B switching is normal, executing the step f.
Further, after the step g and before the step h, when the C-phase switching-on and switching-off fails, the C-phase breaker bounces off the reset lockout non-full-phase protection signal, and returns to execute the step b again; and when the phase C is normally closed, executing the step h.
The present invention has been fully described for the purposes of clarity and disclosure, but is not limited to the prior art.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some of the technical features thereof can be replaced by equivalents; it is obvious to a person skilled in the art to combine several embodiments of the invention. Such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (6)
1. A method of avoiding damage to a circuit breaker by a bias current, comprising: by means of a dynamic time delay sequential closing system, comprising the steps of:
step b, firstly, respectively sensing three-phase voltages of a line by a line voltage transformer, and respectively transmitting the three-phase voltages of the line to an A/D sampling module by the line voltage transformer; secondly, the A/D sampling module carries out analog-to-digital conversion on the signal and transmits the signal to the CPU system; thirdly, the CPU system judges the received voltage, and when the voltage exists in the three phases of the circuit, the CPU system controls the A-phase circuit breaker, the B-phase circuit breaker and the C-phase circuit breaker of the circuit breaker mechanism to be directly switched on at the same time; c, when the three phases of the line have no voltage, performing the step;
step C, firstly, setting a switching-on sequence to be an A-phase circuit breaker, a B-phase circuit breaker and a C-phase circuit breaker by people, wherein three paths of switching-on can be set in sequence; secondly, the CPU system controls the switching-on of the A-phase breaker through the solid-state relay;
step d: the phase A zero crossing judgment, wherein the phase A current transformer transmits the induced phase A line current information to the CPU system through the A/D sampling module, and the CPU system carries out zero judgment; if no zero point exists, the CPU system continues to carry out current zero crossing judgment on the phase A line current within the preset delay time, and when the phase A line current crosses zero or reaches the preset time, the step e is executed;
step e: the CPU system controls the B-phase breaker to be switched on through the solid-state relay;
step f: b phase zero crossing judgment, the B phase current transformer transmits the induced B phase line current information to a CPU system through an A/D sampling module, and the CPU system carries out zero point judgment; if no zero point exists, the CPU system continues to carry out current zero crossing judgment on the B-phase line current within the preset delay time, and when the B-phase line current crosses zero or reaches the preset time, the step g is executed;
step g: the CPU system controls the C-phase breaker to be switched on through the solid-state relay;
step h: c phase zero crossing judgment, the C phase current transformer transmits the induced C phase line current information to a CPU system through an A/D sampling module, and the CPU system carries out zero point judgment; if no zero point exists, the CPU system continues to carry out current zero crossing judgment on the C-phase line current within the preset delay time, and when the C-phase line current crosses zero or reaches the preset time, the step j is executed;
step j; the photoelectric isolator transmits the position state information of the A-phase circuit breaker, the B-phase circuit breaker and the C-phase circuit breaker to the CPU system, the CPU system judges that the A-phase circuit breaker, the B-phase circuit breaker and the C-phase circuit breaker are at the closing position and/or the line current transformer transmits the current information of the line three phases to the CPU system through the A/D sampling module, the CPU system judges that the line three phases have current, and the CPU system resets the locking non-full-phase protection signal, and the execution is finished;
the dynamic time delay sequence closing system comprises a dynamic time delay sequence closing device, a bus voltage transformer for respectively inducing bus three-phase voltages, a line voltage transformer for respectively inducing line three-phase voltages, a line current transformer for inducing line three-phase currents and a circuit breaker mechanism;
the dynamic time delay sequential switching-on device comprises a power supply, a CPU system, an A/D sampling module, a photoelectric isolator, an alternating current converter and a solid-state relay;
the power supply is used for providing electric energy for the CPU system, the CPU system is electrically connected with the photoelectric isolator, the secondary coil of the line current transformer is electrically connected with the input end of the A/D sampling module, and the output end of the A/D sampling module is electrically connected with the input end of the CPU system;
the circuit breaker mechanism comprises an A-phase circuit breaker, a B-phase circuit breaker and a C-phase circuit breaker which are controlled independently, wherein an A-phase bus is connected with an A-phase circuit through the A-phase circuit breaker, a B-phase bus is connected with a B-phase circuit through the B-phase circuit breaker, and a C-phase bus is connected with a C-phase circuit through the C-phase circuit breaker;
the photoelectric isolator converts the position state information of the A-phase circuit breaker, the B-phase circuit breaker and the C-phase circuit breaker into high-low level information respectively and transmits the high-low level information to the CPU system; the CPU system respectively controls the closing of the A-phase circuit breaker, the B-phase circuit breaker and the C-phase circuit breaker through the solid-state relay;
the line current transformer comprises an A-phase current transformer for inducing an A-phase line current, a B-phase current transformer for inducing a B-phase line current and a C-phase current transformer for inducing a C-phase line current;
the secondary coil of the bus voltage transformer and the secondary coil of the line voltage transformer are respectively and electrically connected with the input end of the alternating current converter, and the output end of the alternating current converter is electrically connected with the input end of the A/D sampling module.
2. The method of avoiding damage to a circuit breaker by a bias current of claim 1, wherein: the dynamic time delay sequential closing system also comprises a measurement and control device which is used for sending a closing command to the CPU system through the photoelectric isolator.
3. The method of avoiding damage to a circuit breaker by a bias current of claim 2, wherein: the measurement and control device is a silicon controlled rectifier or an intermediate relay.
4. A method of avoiding damage to a circuit breaker by a bias current as claimed in claim 3, wherein: further comprising step a: firstly, a measurement and control device sends a closing command to a CPU system through a photoelectric isolator; next, the photo-isolator transmits the open/close position state information of the circuit breaker mechanism to the CPU system, and when the circuit breakers of the circuit breaker mechanism are all in the open state, the step b is executed.
5. The method of avoiding damage to a circuit breaker by a bias current of claim 4, wherein: c, respectively selecting an A-phase bus on three phases of buses as reference voltage by the bus voltage transformer while executing the step c, and controlling the A-phase circuit breaker to be closed by the CPU system according to a preset A-phase voltage phase angle;
c, when the step e is executed, the bus voltage transformer respectively selects a B-phase bus on three phases of the bus as a reference voltage, and the CPU system controls the B-phase breaker to be closed according to a preset B-phase voltage phase angle;
and g, respectively selecting a C-phase bus on three phases of buses as reference voltage by the bus voltage transformer while executing the step g, and controlling the C-phase circuit breaker to be closed by the CPU system according to a preset C-phase voltage phase angle.
6. The method of avoiding damage to a circuit breaker by a bias current of claim 5, wherein:
after performing step c and before step d, further comprises step β: the CPU system outputs a locking non-full-phase protection signal to the circuit breaker mechanism through the solid relay to control the non-full-phase protection in the circuit breaker mechanism to exit; non-full phase protection is also called three-phase inconsistent protection;
after the step beta and before the step d, when the A-phase switching-on and switching-off fails, the A-phase breaker is tripped, the non-full-phase protection signal is reset and blocked, and the step b is re-executed; when the phase A switching-on is normal, executing the step d;
after the step e and before the step f, when the B-phase switching-on gate fails, the B-phase breaker spring-open and returns to reset the locking non-full-phase protection signal, and the step B is re-executed; when the phase B switching-on and switching-off are normal, executing the step f;
after the step g and before the step h, when the C-phase switching-on and switching-off faults occur, the C-phase breaker spring-open and returns to reset the locking non-full-phase protection signal, and the step b is re-executed; and when the phase C is normally closed, executing the step h.
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| CN111208418B (en) * | 2020-01-10 | 2022-05-13 | 中国南方电网有限责任公司超高压输电公司广州局 | Phase selection switching-on and switching-off state monitoring system and method for converter station alternating current filter |
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| CN102412568A (en) * | 2011-11-18 | 2012-04-11 | 中国电力科学研究院 | Method for adjusting line protection motion sequential solution breaker current delay zero crossing |
| CN103000409A (en) * | 2012-11-30 | 2013-03-27 | 西安交通大学 | Low frequency breaker with phase-selection brake-separating function |
| CN203352193U (en) * | 2013-06-26 | 2013-12-18 | 桂林电子科技大学 | Intelligent controller of vacuum circuit breaker phase selection operation |
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