CN106710512A - Display device and display method - Google Patents
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- CN106710512A CN106710512A CN201710114496.9A CN201710114496A CN106710512A CN 106710512 A CN106710512 A CN 106710512A CN 201710114496 A CN201710114496 A CN 201710114496A CN 106710512 A CN106710512 A CN 106710512A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The embodiment of the invention provides a display device and a display method. A display drive chip is connected with an FPGA (field programmable gate array) through a VDO (video digital output) link; the display drive chip receives video data, transmits the video data to the FPGA through the VDO link and transmits the video data to a local display for displaying; the FPGA compresses the video data so as to obtain first compressed data and transmits the first compressed data to remote equipment through a network. The local display of the video data is realized by the display drive chip, the display drive chip transmits the video data to the FPGA, the FPGA compresses the video data and transmits the data to the remote equipment, and then the remote display of the video data is realized. The display function is realized by hardware, the software processing function is realized by the FPGA, the display function is separated from the software processing function, the development difficulty of the display function realized by the software is reduced, the development cycle is shortened, and the development cost is further reduced.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of display device and display methods.
Background technology
With the development of network technology, network management can be divided into outband management (out-of-band) and in-band management
(in-band).Realize the outband management system of outband management by console server, long-range KVM (Keyboard Video
Mouse), power supervisor, and network base station manager composition.
, it is necessary to set a managing chip in outband management system, the managing chip is integrated with display processing function, can
Enough is that offer display data is locally displayed, it is also possible to which local display data is supplied to the equipment of distal end.But, the management core
Piece development difficulty is big, and the construction cycle used is long, causes development cost high.
The content of the invention
Present invention solves the technical problem that being to provide a kind of display device and display methods such that it is able to provide it is a kind of into
This cheap long-range display design.
Therefore, the technical scheme that the present invention solves technical problem is：
A kind of display device, described device includes：
Display driver chip, and field programmable gate array FPGA；
The display driver chip exports VDO links and is connected with the FPGA by digital video；
The display driver chip receives video data, and the display driver chip is by the video data by described
VDO links are sent to the FPGA, and the video data transmitting is delivered to local display and shown by the display driver chip；
The video data is compressed the first compressed data of acquisition by the FPGA, and first compressed data is passed through
Network is sent to remote equipment.
In one example,
The FPGA receives peration data, and the peration data includes keyboard data and/or mouse data；
The display driver chip receives view data, and the display driver chip is by described image data by described
VDO links are sent to the FPGA, and the display driver chip is shown described image data is activation to local display,
Described image data are used to characterize the operation content of the peration data；
The peration data and described image data are compressed the second compressed data of acquisition by the FPGA, by described the
Two compressed datas are sent to remote equipment by network.
In one example, described device also includes：
Credible chip；
The credible chip obtains the log-on data of the FPGA, and the log-on data according to the FPGA measures the FPGA
Confidence level.
In one example, described device also includes：
Signal connector, the signal connector is connected by a PCIE links with the display driver chip, described
Signal connector is connected by a LPC links with the credible chip, is included between the signal connector and the FPGA
First general-purpose serial bus USB link and the 2nd LPC links；
The display driver chip receives the video that the signal connector is sent by a PCIE links
Data and/or described image data；
The FPGA receives the peration data that the signal connector is sent by first USB link；
The FPGA sends to the signal connector log-on data by a LPC links, the letter
Number connector sends to the credible chip log-on data by the 2nd LPC links.
In one example, described device also includes：
South Bridge chip；
The South Bridge chip receives the peration data, and described image data are obtained according to the peration data, by the
Signal connector described in two PCIE chain road directions sends the video data and/or described image data, by the second USB link to
The signal connector sends peration data.
A kind of display methods, methods described includes：
Display driver chip receives video data；
The display driver chip sends to FPGA the video data by the VDO links；
The video data transmitting is delivered to local display and is shown by the display driver chip；
The video data is compressed the first compressed data of acquisition by the FPGA, and first compressed data is passed through
Network is sent to remote equipment.
In one example, methods described also includes：
The FPGA receives peration data, and the peration data includes keyboard data and/or mouse data；
The display driver chip receives view data, and described image data are used to characterize in the operation of the peration data
Hold；
The display driver chip sends to the FPGA described image data by the VDO links；
The display driver chip is shown described image data is activation to local display；
The peration data and described image data are compressed the second compressed data of acquisition by the FPGA, by described the
Two compressed datas are sent to remote equipment by network.
In one example, methods described also includes：
Credible chip obtains the log-on data of the FPGA, and the log-on data measurement FPGA's according to the FPGA can
Reliability.
In one example,
The display driver chip receives video data to be included：
The display driver chip receives the video data that signal connector is sent by a PCIE links；
The display driver chip receives view data to be included：
The display driver chip receives the described image that the signal connector is sent by a PCIE links
Data；
The FPGA receives peration data to be included：
The FPGA receives the peration data that the signal connector is sent by the first USB link.
The log-on data that the credible chip obtains the FPGA includes：
The FPGA sends to the signal connector log-on data by a LPC links, the letter
Number connector sends to the credible chip log-on data by the 2nd LPC links.
In one example,
The South Bridge chip receives the peration data, and described image data are obtained according to the peration data, by the
Signal connector described in two PCIE chain road directions sends the video data and/or described image data, by the second USB link to
The signal connector sends peration data.
According to the above-mentioned technical solution, the method have the advantages that：
Display device and display methods are the embodiment of the invention provides, display driver chip exports VDO by digital video
Link is connected with FPGA；Display driver chip receives video data, and display driver chip sends video data by VDO links
To the FPGA, video data transmitting is delivered to local display and is shown by display driver chip；FPGA carries out video data
Compression obtains the first compressed data, and the first compressed data is sent to remote equipment by network.Using display driver chip reality
Now video data is locally displayed, video data transmitting is delivered to FPGA by display driver chip, by FPGA by video data compression
After be sent to remote equipment, realize the distal displayed of video data.Display function is realized using hardware, software processing function is adopted
Realized with FPGA, display function is separated with software processing function, the development difficulty of display function, contracting are realized in reduction using software
The short construction cycle, and then reduce development cost.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is display device structure schematic diagram provided in an embodiment of the present invention；
Fig. 2 is another exemplary construction schematic diagram of display device provided in an embodiment of the present invention；
Fig. 3 is the another exemplary construction schematic diagram of display device provided in an embodiment of the present invention；
Fig. 4 is display device yet another embodiment structural representation provided in an embodiment of the present invention；
Fig. 5 is display device yet another embodiment structural representation provided in an embodiment of the present invention；
Fig. 6 is display methods schematic flow sheet provided in an embodiment of the present invention；
Fig. 7 is another example process schematic diagram of display methods provided in an embodiment of the present invention.
Specific embodiment
In order to provide the implementation of long-range display with low cost, the embodiment of the invention provides a kind of display device and
The preferred embodiments of the present invention are illustrated by display methods below in conjunction with Figure of description.
In the prior art, in order to realize long-range display in outband management system, base is set in the outband management system
Board management controller (Baseboard Management Controller, BMC), the BMC is used by believing that Hua scientific ＆ technical corporation produces
AST family chips (AST2300, AST2400, or AST2500), the chip provide software realize display processing function,
Can realize being locally displayed；The chip also provides data processing function, it is also possible to realize long-range display.But, the chip cost
Height, and then improve the cost of implementation of BMC systems.
The invention provides a kind of display device with low cost, the display device can substitute the AST systems in BMC systems
Row chip, so as to reduce the cost of implementation of BMC systems.
Fig. 1 is a kind of display device structure schematic diagram provided in an embodiment of the present invention, including：
Display driver chip 101, and field programmable gate array (Field-Programmable Gate
Array, FPGA) 102.
Display driver chip 101 exports (Video Digital Output, VDO) link and FPGA by digital video
102 are connected.
Display driver chip 101 receives video data, and display driver chip 101 sends video data by VDO links
To FPGA 102, video data transmitting is delivered to local display and is shown by display driver chip 101.
Video data is compressed the first compressed data of acquisition by FPGA 102, and first compressed data is passed through into network
Send to remote equipment.
Display driver chip 101 can be using the chip of the model SM750 of Hui Rong science and technology (Silicon Motion).Should
Display driver chip 101 is connected with FPGA 102 by VDO links.Display driver chip 101 receives video data, by the video
Data is activation is locally displayed to local display, and also video data is sent to FPGA 102 by VDO links.
Display driver chip 101 and local display by Video Graphics Array ((Video Graphics Array,
VGA) link is connected with local display, and video data, the video data are sent by the local display of the VGA chain road directions
Shown in local display, realize being locally displayed.
FPGA 102 can realize to video data be compressed acquisition the first compressed data, by the first compressed data via
Network is sent to remote equipment.FPGA 102 is sent to remote equipment the first compressed data by KVM links.
Remote equipment has two kinds of display modes after KVM links receive the first compressed data：
The first display mode, after the FPGA of remote equipment receives the first compressed data, is carried out to the first compressed data
Decompression obtains the video data.The FPGA of remote equipment is delivered to the South Bridge chip of remote equipment by the video data transmitting.Distal end
The South Bridge chip of equipment is delivered to the display driver chip of remote equipment, the display driver chip of remote equipment by the video data transmitting
The video data transmitting is delivered to the display of remote equipment again, is shown by the display of remote equipment.
Second display mode, remote equipment using the BMC of display processing function is integrated with, then the BMC receive this first
Compressed data, decompression is carried out to the first compressed data and obtains the video data.The video data transmitting is delivered to remote equipment by BMC
Display, shown by the display of remote equipment.
FPGA 102 is using Joint Photographic Experts Group (Joint Photographic Experts Group, JPEG) pressure
Contracting mode is compressed to video data.It is, of course, also possible to select other compress modes to enter video data according to actual needs
Row compression, no longer repeats one by one here.
In an example, the display device can not only realize being locally displayed and distal displayed for video data, the display
Device can also realize being locally displayed and distal displayed for mouse data and/or keyboard data.
FPGA receives peration data, and peration data includes keyboard data and/or mouse data.
Display driver chip receives view data, and view data is sent to FPGA by VDO links, and by view data
Send to local display and shown, view data is used to characterize the operation content of peration data.
Peration data and view data are compressed the second compressed data of acquisition by FPGA, and the second compressed data is passed through into net
Network is sent to remote equipment.
FPGA 102 receives peration data, and the peration data includes that mouse data and/or keyboard data, i.e. user pass through mouse
The peration data of mark and/or input through keyboard.
Display driver chip 101 receives view data, and the view data is at mouse data and/or keyboard data
Reason, what is obtained represents the location drawing picture information of mouse and/or keyboard operation content.For example, user's movement mouse, webpage clicking
Chained address, opens a webpage, then the view data is mouse and is moved to webpage link address, opens network connection ground
The sequence of images of the corresponding webpage in location.Again for example, user passes through input through keyboard word, then the view data is user input
The sequence of images of word process.The view data is sent to local display and entered by display driver chip 101 by VGA links
Row is locally displayed, and the view data is sent to FPGA 102.
The peration data that FPGA 102 will be received, and represent that the view data of the operation content of the peration data is carried out
Compression, obtains the second compressed data, and the second compressed data is sent to remote equipment by network.FPGA 102 passes through KVM chains
Road sends to remote equipment the second compressed data.FPGA 102 is compressed to peration data and view data, it is also possible to adopt
With the compress mode of JPEG.
Remote equipment has two kinds of display modes after KVM links receive the first compressed data：
The first display mode, after the FPGA of remote equipment receives the second compressed data, is carried out to the second compressed data
Decompression obtains the peration data and view data.The peration data and view data are sent remote to this by the FPGA of remote equipment
The South Bridge chip of end equipment.The South Bridge chip of remote equipment sends the view data to the display driver chip of remote equipment,
The display driver chip of remote equipment sends the view data to the display of remote equipment, is entered by the display of remote equipment
Row display.
Second display mode, remote equipment using the BMC of display processing function is integrated with, then the BMC receive this second
Compressed data, decompression is carried out to the second compressed data and obtains the peration data and view data.BMC sends the view data
To the display of remote equipment, shown by the display of remote equipment.
So as to realize being locally displayed and distal displayed for mouse data and/or keyboard data.
Explanation is needed exist for, if FPGA 102 receives video data, view data and peration data simultaneously, can be with
By video data, after view data and peration data are compressed together, it is sent to remote equipment and realizes distal displayed.That is,
FPGA 102 will only can send to remote equipment after video data compression, it is also possible to only compress view data and peration data
After be sent to remote equipment, can also be by video data, view data and peration data are sent to remote equipment after compressing together.
In one example, as shown in Fig. 2 the device also includes a credible chip 201：
Credible chip obtains the log-on data of FPGA, and the log-on data according to FPGA measures the confidence level of FPGA.
Before FPGA startups, credible chip is obtained in that the log-on data of FPGA, measures FPGA's according to the log-on data
Confidence level.If FPGA is credible, upper electricity is carried out to the FPGA, the FPGA can use；If FPGA is insincere, to not using this
FPGA。
In the embodiment of the present invention, the credible chip both includes reliable platform module (Trusted Platform
Module, TPM), and including credible password module (Trusted Cryptography Module, TCM).
In another example, as shown in figure 3, the device also includes a signal connector 301.：
Signal connector by a PCIE (Peripheral Component Interconnect Express,
PCIE) link is connected with the display driver chip, signal connector by a LPC (Low Pin Count) links with can
Letter chip is connected, and the first USB (Universal Serial Bus, USB) is included between signal connector and FPGA
Link and the 2nd LPC links.
Display driver chip receives video data and/or the picture number that signal connector is sent by a PCIE links
According to.
FPGA receives the peration data that signal connector is sent by the first USB link.
FPGA sends to signal connector log-on data by a LPC links, and signal connector leads to log-on data
The 2nd LPC links are crossed to send to credible chip.
As shown in figure 3, signal connector 301 receives video data, the video data is sent out by a PCIE links
Deliver to display driver chip 101.In actual applications, if the device is not provided with signal connector 301, display driver chip
101 can be directly connected to South Bridge chip by PCIE links, receive the video counts that the South Bridge chip is sent by PCIE links
According to.
As shown in figure 3, signal connector 301 receives view data and peration data.Signal connector 301 is by picture number
Sent to display driver chip 101 according to by a PCIE links.In actual applications, if the device is not provided with signal connector
301, then display driver chip 101 can be directly connected to by PCIE links with South Bridge chip, receive the South Bridge chip and pass through
The view data that PCIE links send.Signal connector 301 sends to FPGA 102 peration data by the first USB link.
In actual applications, if the device is not provided with signal connector 301, FPGA 102 can pass through USB link with South Bridge chip
It is directly connected to, receives the peration data that the South Bridge chip is sent by USB link.
As shown in figure 3, FPGA 102 sends to signal connector 301 log-on data by a LPC links, signal connects
Device 301 is connect to send to credible chip 201 log-on data by the 2nd LPC links.In actual applications, if the device is not provided with
Signal connector 301, then FPGA 102 can be directly connected to by LPC links with credible chip 201, receiving FPGA 102 can be with
Log-on data is directly sent by LPC chain road directions credible chip 201.
As shown in figure 3, signal connector 301 is a transferring device for data transfer, signal connector 301 and FPGA
It is connected by polytype link between 102, polytype data message can be interacted.As shown in figure 4, signal connector
Also include IC bus (Inter-Integrated Circuit, IIC) link between 301 and FPGA 102, it is general different
Step receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter, UART) link, serial peripheral connects
Mouth (Serial Peripheral Interface, SPI) link, platform environment formula control interface (Platform
Environment Control Interface, PECI) link, simplify Gigabit Media stand-alone interface (Reduced
Gigabit Media Independent Interface, RGMII) link etc..
Explanation is needed exist for, when implementing, the signal connector 301 can use direct insertion memory modules
(Small Outline Dual In-line Memory Module, SODIMM) is realized, certainly can also be using other realizations
Mode, no longer repeats one by one here.
As shown in figure 5, the device also includes South Bridge chip 501：
South Bridge chip receives peration data, view data is obtained according to peration data, by the 2nd PCIE chain road direction signals
Connector sends video data and/or view data, and peration data is sent to signal connector by the second USB link.
South Bridge chip 501 is connected by USB interface with mouse and keyboard, can receive mouse and/or key by USB interface
The peration data of disk, and treatment acquisition view data is carried out to peration data.South Bridge chip 501 is by the 2nd PCIE links and letter
Number connector 301 is connected, and South Bridge chip 501 is connected by the second USB link with signal connector 301.South Bridge chip 501 passes through
2nd PCIE chain road directions signal connector 301 sends video data and/or view data, and South Bridge chip 501 passes through the 2nd USB chains
Road direction signal connector 301 sends peration data.
In device shown in Fig. 5, South Bridge chip 501 sends to signal connector video data by the 2nd PCIE links
301, signal connector 301 is again sent to display driver chip 101 video data by a PCIE links, and display drives
Video data is sent to local display and is locally displayed by chip 101 by VGA links, and display driver chip 101 will also
Video data is sent to FPGA 201 by VDO links, and the video data is compressed acquisition first and compresses number by FPGA 201
According to, the first compressed data is sent to remote equipment, realize the distal displayed of video data.
In device shown in Fig. 5, South Bridge chip 501 obtains the peration data of mouse and/or keyboard from USB interface, to behaviour
Treatment is carried out as data obtain view data.View data is sent to signal and connected by South Bridge chip 501 by the 2nd PCIE links
Device 301 is connect, signal connector 301 is again sent to display driver chip 101, display the view data by a PCIE links
View data is sent to local display and is locally displayed by driving chip 101 by VGA links, display driver chip 101
Also view data is sent to FPGA 201 by VDO links, peration data is also passed through the second USB link by South Bridge chip 501
Send to signal connector 301, signal connector 301 is again sent to FPGA 201 peration data by the first USB link.
The view data and peration data are compressed the second compressed data of acquisition by FPGA 201, and the second compressed data is sent to remote
End equipment, realizes the distal displayed of peration data.
As shown in the above, realized to the local aobvious of video data using display driver chip in the embodiment of the present invention
Show, video data transmitting is delivered to FPGA by display driver chip, remote equipment will be sent to by FPGA after video data compression, realize
The distal displayed of video data.Display function is realized using hardware, software processing function is realized using FPGA, by display function
Separated with software processing function, the development difficulty of display function is realized in reduction using software, shorten the construction cycle, and then reduction is opened
Hair cost.
Fig. 6 is display methods flow chart provided in an embodiment of the present invention, including：
601：Display driver chip receives video data.
602：The display driver chip sends to FPGA the video data by the VDO links.
603：The video data transmitting is delivered to local display and is shown by the display driver chip.
604：The video data is compressed the first compressed data of acquisition by the FPGA, by first compressed data
Sent to remote equipment by network.
In one example, as shown in fig. 7, methods described also includes：
701：The FPGA receives peration data, and the peration data includes keyboard data and/or mouse data.
702：The display driver chip receives view data, and described image data are used to characterize the behaviour of the peration data
Make content.
703：The display driver chip sends to the FPGA described image data by the VDO links.
704：The display driver chip is shown described image data is activation to local display.
705：The peration data and described image data are compressed the second compressed data of acquisition by the FPGA, by institute
The second compressed data is stated to be sent to remote equipment by network.
In one example, methods described also includes：
Credible chip obtains the log-on data of the FPGA, and the log-on data measurement FPGA's according to the FPGA can
Reliability.
In one example, the display driver chip receives video data and includes：
The display driver chip receives the video data that signal connector is sent by a PCIE links；
The display driver chip receives view data to be included：
The display driver chip receives the described image that the signal connector is sent by a PCIE links
Data；
The FPGA receives peration data to be included：
The FPGA receives the peration data that the signal connector is sent by the first USB link.
The log-on data that the credible chip obtains the FPGA includes：
The FPGA sends to the signal connector log-on data by a LPC links, the letter
Number connector sends to the credible chip log-on data by the 2nd LPC links.
In one example, the South Bridge chip receives the peration data, and the figure is obtained according to the peration data
As data, the video data and/or described image data are sent by signal connector described in the 2nd PCIE chain road directions, passed through
Second USB link sends peration data to the signal connector.
Method shown in Fig. 6 and Fig. 7, is method corresponding with the device shown in Fig. 1, shown in concrete methods of realizing and Fig. 1
Device be similar to, the description of the method with reference to shown in Fig. 1 is repeated no more here.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of display device, it is characterised in that described device includes：
Display driver chip, and field programmable gate array FPGA；
The display driver chip exports VDO links and is connected with the FPGA by digital video；
The display driver chip receives video data, and the video data is passed through the VDO chains by the display driver chip
Road is sent to the FPGA, and the video data transmitting is delivered to local display and shown by the display driver chip；
The video data is compressed the first compressed data of acquisition by the FPGA, and first compressed data is passed through into network
Send to remote equipment.
2. device according to claim 1, it is characterised in that
The FPGA receives peration data, and the peration data includes keyboard data and/or mouse data；
The display driver chip receives view data, and described image data are passed through the VDO chains by the display driver chip
Road is sent to the FPGA, and the display driver chip is shown described image data is activation to local display, described
View data is used to characterize the operation content of the peration data；
The peration data and described image data are compressed the second compressed data of acquisition by the FPGA, by the described second pressure
Contracting data are sent to remote equipment by network.
3. the device according to claim 1-2 any one, it is characterised in that described device also includes：
Credible chip；
The credible chip obtains the log-on data of the FPGA, and the log-on data measurement FPGA's according to the FPGA can
Reliability.
4. device according to claim 3, it is characterised in that described device also includes：
Signal connector, the signal connector is connected by a PCIE links with the display driver chip, the signal
Connector is connected by a LPC links with the credible chip, and first is included between the signal connector and the FPGA
General-purpose serial bus USB link and the 2nd LPC links；
The display driver chip receives the video data that the signal connector is sent by a PCIE links
And/or described image data；
The FPGA receives the peration data that the signal connector is sent by first USB link；
The FPGA sends to the signal connector log-on data by a LPC links, and the signal connects
Device is connect to send to the credible chip log-on data by the 2nd LPC links.
5. method according to claim 4, it is characterised in that described device also includes：
South Bridge chip；
The South Bridge chip receives the peration data, described image data is obtained according to the peration data, by second
Signal connector described in PCIE chain road directions sends the video data and/or described image data, by the second USB link to institute
State signal connector and send peration data.
6. a kind of display methods, it is characterised in that methods described includes：
Display driver chip receives video data；
The display driver chip sends to FPGA the video data by the VDO links；
The video data transmitting is delivered to local display and is shown by the display driver chip；
The video data is compressed the first compressed data of acquisition by the FPGA, and first compressed data is passed through into network
Send to remote equipment.
7. method according to claim 6, it is characterised in that methods described also includes：
The FPGA receives peration data, and the peration data includes keyboard data and/or mouse data；
The display driver chip receives view data, and described image data are used to characterize the operation content of the peration data；
The display driver chip sends to the FPGA described image data by the VDO links；
The display driver chip is shown described image data is activation to local display；
The peration data and described image data are compressed the second compressed data of acquisition by the FPGA, by the described second pressure
Contracting data are sent to remote equipment by network.
8. the method according to claim 6-7 any one, it is characterised in that methods described also includes：
Credible chip obtains the log-on data of the FPGA, and the log-on data according to the FPGA measures the credible of the FPGA
Degree.
9. method according to claim 8, it is characterised in that
The display driver chip receives video data to be included：
The display driver chip receives the video data that signal connector is sent by a PCIE links；
The display driver chip receives view data to be included：
The display driver chip receives the described image data that the signal connector is sent by a PCIE links；
The FPGA receives peration data to be included：
The FPGA receives the peration data that the signal connector is sent by the first USB link.
The log-on data that the credible chip obtains the FPGA includes：
The FPGA sends to the signal connector log-on data by a LPC links, and the signal connects
Device is connect to send to the credible chip log-on data by the 2nd LPC links.
10. method according to claim 9, it is characterised in that
The South Bridge chip receives the peration data, described image data is obtained according to the peration data, by second
Signal connector described in PCIE chain road directions sends the video data and/or described image data, by the second USB link to institute
State signal connector and send peration data.
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| CN201710114496.9A CN106710512A (en) | 2017-02-28 | 2017-02-28 | Display device and display method |
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