CN106709187A - Method and device for establishing CPU on basis of model - Google Patents
Method and device for establishing CPU on basis of model Download PDFInfo
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- CN106709187A CN106709187A CN201611229754.XA CN201611229754A CN106709187A CN 106709187 A CN106709187 A CN 106709187A CN 201611229754 A CN201611229754 A CN 201611229754A CN 106709187 A CN106709187 A CN 106709187A
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Abstract
Embodiments of the invention provide a method and device for establishing a CPU on the basis of a model. The method comprises the following steps of: generating an instruction data path corresponding to each instruction according to a structure and a function of each instruction in an instruction set; inserting a multipath selector between a source end and a destination end of each instruction data path; combining items in same instruction data paths, and carrying out a logical sum operation on a control signal expression so as to obtain a CPU data path; determining structure information of the CPU according to the CPU data path; and determining structure information of a control unit of the CPU according to the control signal expression. According to the method disclosed by the embodiments of the invention, the data path and the control signal of the CPU are automatically generated according to the data path of each instruction through an engineering comprehensive method, so that the designs of different instructions in the instruction set are mutually independent and the dependency of the data path of each instruction is relatively low, thereby simplifying the method for simplifying the CPU and reducing the error rate in the process of establishing the CPU.
Description
Technical field
The present embodiments relate to field of computer technology, more particularly to a kind of method and dress that CPU is set up based on model
Put.
Background technology
Central processing unit (Central Processing Unit, abbreviation CPU) is the engine and core of computer system,
Operating system, the reliability of application software are built upon on the basis of cpu function correctness.
In the prior art, CPU design method is to draw on the diagram data path, and the data path of all instructions is drawn in one
Open on figure so that the data path correlation of each instruction is higher, cause data path to design sufficiently complex, design difficulty is big, and
Error rate is higher.
The content of the invention
The embodiment of the present invention provides a kind of method and device that CPU is set up based on model, in the method that CPU is set up in simplification,
The error rate that reduction is set up during CPU.
The one side of the embodiment of the present invention is to provide a kind of method that CPU is set up based on model, including：
According to the 26S Proteasome Structure and Function that each is instructed in instruction set, each corresponding director data path of instruction is generated；
MUX is inserted between the source and destination of each director data path, the control of MUX is generated
Signal expression processed and register enable the logical expression of signal, and the control signal expression formula includes the stage that instruction is performed
Signal, instruction operation code, instruction control code field；
Merge the item in identical director data path, while logic union operation is done to the control signal expression formula,
Obtain cpu data path；
According to the cpu data path, the structural information of the CPU is determined；
According to the control signal expression formula, the structural information of the control unit of the CPU is determined.
The other side of the embodiment of the present invention is to provide a kind of device that CPU is set up based on model, including：
Generation module, for according to the 26S Proteasome Structure and Function that each is instructed in instruction set, generating each corresponding instruction of instruction
Data path；
Insertion module, for inserting MUX between the source and destination of each director data path, generation
The control signal expression formula and register of MUX enable the logical expression of signal, and the control signal expression formula includes
Instruct stage signal, instruction operation code, the instruction control code field for performing；
Merging module, for merging the item in identical director data path, while being done to the control signal expression formula
Logic union operation, obtains cpu data path；
Determining module, for according to the cpu data path, determining the structural information of the CPU；According to the control letter
Number expression formula, determines the structural information of the control unit of the CPU.
The method and device that CPU is set up based on model provided in an embodiment of the present invention, according to every data path of instruction,
Then by engineering comprehensive method, the data path and control signal of CPU are automatically generated so that different instruction in instruction set
Design is separate, and the design of an instruction has no effect on other instructions, is not also influenceed by other instructions so that respectively refer to
The data path correlation of order is relatively low, simplifies the method for setting up CPU, reduces the error rate set up during CPU.
Brief description of the drawings
Fig. 1 is the method flow diagram that CPU is set up based on model provided in an embodiment of the present invention；
Fig. 2 is for cpu data path is comprehensive, the flow chart of Code automatic build；
Fig. 3 is the CPU Modeling and Design flows for meeting DO-178C development process based on model and formal approach；
The method flow diagram that CPU is set up based on model that Fig. 4 is provided for another embodiment of the present invention；
Fig. 5 is the structure chart of CPU code generating methods；
Fig. 6 is the structure chart of the device that CPU is set up based on model provided in an embodiment of the present invention；
The structure chart of the device that CPU is set up based on model that Fig. 7 is provided for another embodiment of the present invention.
Specific embodiment
Fig. 1 is the method flow diagram that CPU is set up based on model provided in an embodiment of the present invention.The embodiment of the present invention is for existing
CPU design method is to draw on the diagram data path in having technology, and the data path of all instructions is drawn on a figure so that
The data path correlation of each instruction is higher, causes data path to design sufficiently complex, and design difficulty is big, and error rate is higher,
Method there is provided CPU is set up based on model is specifically as follows based on the method and step that model sets up CPU：
Step S101, the 26S Proteasome Structure and Function according to each instruction in instruction set, generate each corresponding director data of instruction
Path.
The structural model of the CPU includes：Digital logic component, digital logic component function and control signal logic are public
Formula, data path and clock cycle.
Be expressed as the structural model of CPU by the present embodiment：<S,F,R,C>, wherein, S represents digital logic component (containing multichannel
Selector and control unit), F represents digital logic component function and control signal logical formula, and R represents data path, and C is represented
Clock cycle.
Digital logic component refer to complete certain concrete function circuit block, such as program counter PC, memory Mem,
Command register IR, general-purpose register GPRegs and arithmetic logic unit alu etc..Digital logic component externally only has some defeated
Enter the FPDP and control port of output, but internal structure is relatively complicated, comprising register element, complicated logic
Circuit etc..In general, digital logic component completes the complete set function for certain data, and such as program counter can be with complete
Into functions such as the output for current instruction address, holding, write-in and oneself increasings.In any stage (in a clock cycle) numeral
Logical block only carries out a concrete function, and whether its control signal by control unit to control port effectively selects this
When the function to be completed be specifically output, keep, write-in and from increase in which.
MUX Mux is one kind of digital logic component, but due to there is special role, is individually begged in this model
By.The data selecting section part that Mux is directed to the data flow node of the output of multi input one and exists, according to control signal, a moment
Only one of which input data is delivered to output end.By the quantity point of input port, Mux Fen Wei No. bis- selectors, No. three selectors
Deng.
Control unit (Control Unit, abbreviation CU) is also one kind of digital logic component, and CU is used for controlling example in CPU
Such as MUX, program counter PC, memory Mem, command register IR, general-purpose register GPRegs and arithmetical logic
The digital logic components such as unit ALU, CU external connections to control signal in need digital logic component, herein, it is necessary to control
The digital logic component of signal processed can be MUX, program counter PC, memory Mem, command register IR, general
It is any one or more in register file GPRegs and arithmetic logic unit alu.Control unit can be to the instruction in instruction set
Enter command code and function code that row decoding obtains the instruction, and according to the command code and function code of the instruction, generate the instruction right
The control signal answered, so that control unit controls digital logic component according to the control signal.
Such as register and MUX have control signal receiving port in digital logic component, and the control signal is received
Port is used for the control signal that reception control unit sends, and in the different phase of different instruction, the operation that control unit is performed is
It is different, therefore, the operation that control unit is performed can be represented with control signal expression formula, for example, certain stage instructed at certain,
If the control signal expression formula is true, useful signal is sent to the control signal receiving port of register or MUX,
Otherwise send invalid signals.
Data path refers to the sequence of the operation clause needed for CPU execute instructions, is divided into instruction path and CPU paths.Refer to
It is the operation of execute instruction on the premise of current execute instruction is had determined to make path, it is not necessary to which MUX is participated in, only
The FPDP of digital logic component need to be connected and register control signal is given.CPU paths are to combine all fingers
So that the data path for arriving, comprising MUX, control signal forms expression formula after synthesis.
Fig. 2 is for cpu data path is comprehensive, the flow chart of Code automatic build.CPU structural models will be abstracted into the clock cycle
Five stages, i.e. fetching stage IF, decoding stage ID, execution stage EX, memory access stage MEM and write back stage WB, each stage
It is divided into two parts of data preparation stage and data write phase.The cpu instruction cycle is divided into five ranks in CPU structural models
Section, therefore, each instruction can generate corresponding director data path according to five stages.
In the present embodiment, director data path be operate clause composition set, each clause realize connectivity port or
Person gives the function of register control signal.The model of director data path is triple<Stage,Source,Target>.Its
In, Stage represents the execution stage of instruction, and Source represents source, and Target represents place.Clause in data preparation stage is
Connectivity port type, Source represents source port, and Target represents destination interface；Clause in data write phase is control
Signal type, Source represents register, and Target represents signal code.
Step S102, MUX is inserted between the source and destination of each director data path, generate multichannel
The control signal expression formula and register of selector enable the logical expression of signal, and the control signal expression formula includes instruction
The stage signal of execution, instruction operation code, instruction control code field.
In the present embodiment, program counter PC, memory Mem, command register IR, general-purpose register GPRegs and
Each output port of the digital logic components such as arithmetic logic unit alu configures a MUX, and to MUX
Numbering, obtains the MUX table of comparisons, and the MUX table of comparisons includes which output end of which digital logic component
The corresponding relation of mouth and MUX numbering.
According to the MUX table of comparisons, multichannel choosing is inserted between the source and destination of each director data path
Device is selected, is obtained<Stage,Source,Mux_In,Mux_Out,Target>, wherein, Mux_In represents the input of MUX
Port, Mux_Out represent the output port of MUX.
<Stage,Source,Mux_In,Mux_Out,Target>Middle addition instruction name, obtains<
Instruction,Stage,Source,Mux_In,Mux_Out,Target>, wherein, Instruction represents instruction name.
Step S103, the item merged in identical director data path, while doing logic to the control signal expression formula
Union operation, obtains cpu data path.
For<Instruction,Stage,Source,Mux_In,Mux_Out,Target>, by identical<Source,
Mux_In,Mux_Out,Target>Merge, while generating control signal expression formula.During merging, first will be different
Instruction and Stage is used or symbol " | " connection, then merges Instruction and Stage with symbol " ＆ "
Into Ctrl_Signal, finally remove Instruction and Stage.So, instruction name and execution stage all concentrate on control
Signal expression Ctrl_Signal processed is suffered, and when certain stage instructed at certain, Ctrl_Signal expression formulas are necessarily 1, and
In other stages of this instruction, expression formula is 0.The cpu data path for ultimately producing is by five-tuple<Source,Mux_In,
Mux_Out,Target,Ctrl_Signal>The set of composition.
Then identical destination interface is merged into same MUX output port, and identical destination interface is corresponding
Different source ports be merged into different input ports under same MUX.
Step S104, according to the cpu data path, determine the structural information of the CPU.
Specifically, the five-tuple model according to cpu data path<Source,Mux_In,Mux_Out,Target,Ctrl_
Signal>, it is determined that the MUX of CPU is constituted, because MUX is the portion for connecting other digital logic components
Part, the then annexation between the input according to MUX and output can determine that other digital logic components, other numbers
Annexation between word logical block can be used as the structural information of CPU.
Step S105, according to the control signal expression formula, determine the structural information of the control unit of the CPU.
The control unit of CPU generates control signal according to control signal expression formula Ctrl_Signal, therefore, according to above-mentioned
The control signal expression formula that step draws, it may be determined that the control signal of CPU, while the knot of the control unit of CPU can also be determined
Structure information.
Fig. 3 is the CPU Modeling and Design flows for meeting DO-178C development process based on model and formal approach.CPU structures
Formal modeling technology first proposed a CPU structural model.Secondly, form design method thinks that the design of instruction is only mutually
Vertical, the design of an instruction does not influence another instruction.Form design method only need to be individually designed according to the specification of instruction set
Every data path of instruction, then by engineering comprehensive method, automatically generates the data path and control signal of CPU.
The embodiment of the present invention, then by engineering comprehensive method, automatically generates CPU's according to every data path of instruction
Data path and control signal so that the design of the different instruction in instruction set is separate, and a design for instruction is simultaneously
Do not influence other to instruct, do not influenceed by other instructions yet so that the data path correlation of each instruction is relatively low, simplifies foundation
The method of CPU, reduces the error rate set up during CPU.
The method flow diagram that CPU is set up based on model that Fig. 4 is provided for another embodiment of the present invention.In above-described embodiment
On the basis of, the method and step for setting up CPU based on model that the present embodiment is provided is as follows：
Step S201, the 26S Proteasome Structure and Function according to each instruction in instruction set, the implementation procedure of the instruction is divided successively
Fit over fetching stage, decoding stage, execution stage, memory phase, write back stage.
In the present embodiment, five stages, i.e. fetching stage IF, decoding stage ID will be abstracted into the clock cycle, rank will be performed
Section EX, memory access stage MEM and write back stage WB, accordingly, are dispensed on each implementation procedure for instructing the fetching stage, translate
Code stage, execution stage, memory phase, write back stage.
Instruction is that instruction is introduced as a example by add is instructed in five complete execution flows in stage with additive below.The IF stages,
Process number and IA are sent to command memory, and the sense order from command memory by control unit, and this is instructed
It is sent to command register.ID stages, control unit obtains this and refers to instructing from command register sense order into row decoding
The command code and function code of order, register file, address of the register file according to data storage are sent to by the address of data storage
After reading two data of add operation, two data are sent respectively to A-register and B-register.EX stages, control unit
By the data is activation in the data and B-register in A-register to ALU, and the function code of addition instruction is sent to ALU, ALU
The function code of data in data, B-register and addition instruction in A-register, carries out additional calculation and is calculated
As a result, and by result of calculation it is sent to ALUOut registers.The MEM stages, without operation.In the WB stages, control unit posts ALUOut
Result of calculation in storage is write in register file.Stage,Source,Target
In the present embodiment, instruction path is as shown in table 1 below：
Table 1
Due to share some digital logic components between instruction, therefore in traditional method for designing, the design of instruction
Necessarily affect other instructions or influenceed by other instructions.In the form design method of CPU structures, multiple instruction path can lead to
Cross engineering comprehensive method and be merged into CPU paths.The port of common numbers logical block is connected using MUX, according to decoding
The instruction operation code and function code for obtaining, can control MUX to be switched to correspondence instruction path, so as to complete to refer to
Make function.
Step S202, the fetching stage according to the instruction, decoding stage, execution stage, memory phase, write back stage,
The corresponding director data path of the generation instruction.
The cpu instruction cycle is divided into five stages in CPU structural models, therefore, each instruction can according to this five
The individual stage generates corresponding director data path.
Step S203, MUX is inserted between the source and destination of each director data path, generate multichannel
The control signal expression formula and register of selector enable the logical expression of signal, and the control signal expression formula includes instruction
The stage signal of execution, instruction operation code, instruction control code field.
The model of director data path is triple<Stage,Source,Target>.Wherein, Stage represents instruction
Execution stage, Source represents source, and Target represents place.Clause in data preparation stage is connectivity port type,
Source represents source port, and Target represents destination interface；Clause in data write phase is control signal type,
Source represents register, and Target represents signal code.
Instruction specification and operational semantics in instruction set, the operation that design instruction is respectively necessary for completing in five stages
Clause.Notice that instruction path is the unordered collection for operating clause, execution no shadow of the order of clause to instruction in same stage
Ring.
MUX is inserted between the source and destination of each director data path, is obtained<Stage,Source,
Mux_In,Mux_Out,Target>, wherein, Mux_In represents that the input port of MUX, Mux_Out represent that multichannel is selected
Select the output port of device.
<Stage,Source,Mux_In,Mux_Out,Target>Middle addition instruction name, obtains<
Instruction,Stage,Source,Mux_In,Mux_Out,Target>, wherein, Instruction represents instruction name.
Step S204, with MUX as keyword, the item in the director data path is sorted.
For<Instruction,Stage,Source,Mux_In,Mux_Out,Target>, Instruction,
Stage, Source, Mux_In, Mux_Out, Target are respectively the item in director data path, in the present embodiment, with multichannel
Selector is keyword, and the item in the director data path is sorted.
Step S205, with data source and MUX as keyword, merge identical director data path in item,
Logic union operation is done to the control signal expression formula simultaneously, cpu data path is obtained.
In the present embodiment, with<Source,Mux_In,Mux_Out,Target>It is keyword, merges identical instruction
Item in data path, while doing logic union operation to the control signal expression formula, obtains cpu data path<Source,
Mux_In,Mux_Out,Target,Ctrl_Signal>。
Step S206, according to the cpu data path, determine the structural information of the CPU.
Step S207, according to the control signal expression formula, determine the structural information of the control unit of the CPU.
The A grades of software requirement in DO-178C standards, CPU codes need to according to CPU software framework (software architecture) and
CPU models (low layer demand) are realized.According to research needs, Verilog HDL are selected as the design language of CPU codes.This section
By taking PPC as an example, it is described in detail in terms of CPU software framework and code conversion method two respectively.Fig. 5 gives birth to for CPU codes
Into the structure chart of method.
A kind of Verilog code frame that the characteristics of CPU software framework is the structure and CPU structures according to CPU codes is designed
Frame, wherein being integrated with CPU top layer frames, control unit module and digital logic component module.CPU top layer frames and control unit
Module is incomplete code skeleton, specific access structure to be achieved in top layer frame, tool to be achieved in control unit module
The control signal of body.And digital logic component module is the complete realization of the digital logic component that all CPU needs are used.According to
CPU structures, access structure code and control signal code are generated by code conversion method respectively, are then respectively embedded in top layer
In frame module and control unit module, complete CPU codes are formed.
The embodiment of the present invention, then by engineering comprehensive method, automatically generates CPU's according to every data path of instruction
Data path and control signal so that the design of the different instruction in instruction set is separate, and a design for instruction is simultaneously
Do not influence other to instruct, do not influenceed by other instructions yet so that the data path correlation of each instruction is relatively low, simplifies foundation
The method of CPU, reduces the error rate set up during CPU.
Fig. 6 is the structure chart of the device that CPU is set up based on model provided in an embodiment of the present invention.The embodiment of the present invention is provided
The device that CPU is set up based on model can perform based on model set up CPU embodiment of the method provide handling process, such as scheme
Shown in 6, the device 60 for setting up CPU based on model includes generation module 61, insertion module 62, merging module 63 and determining module
64, wherein, generation module 61 is used for according to the 26S Proteasome Structure and Function that each is instructed in instruction set, generates each corresponding instruction of instruction
Data path；Insertion module 62 is used to insert MUX between the source and destination of each director data path, raw
Control signal expression formula and register into MUX enable the logical expression of signal, the control signal expression formula bag
Include stage signal, instruction operation code, instruction control code field that instruction is performed；Merging module 63 is used to merge identical instruction number
According to the item in path, while doing logic union operation to the control signal expression formula, cpu data path is obtained；Determining module
64 are used for according to the cpu data path, determine the structural information of the CPU；According to the control signal expression formula, institute is determined
State the structural information of the control unit of CPU.
The embodiment of the present invention, then by engineering comprehensive method, automatically generates CPU's according to every data path of instruction
Data path and control signal so that the design of the different instruction in instruction set is separate, and a design for instruction is simultaneously
Do not influence other to instruct, do not influenceed by other instructions yet so that the data path correlation of each instruction is relatively low, simplifies foundation
The method of CPU, reduces the error rate set up during CPU.
The structure chart of the device that CPU is set up based on model that Fig. 7 is provided for another embodiment of the present invention.In above-described embodiment
On the basis of, the device 60 for setting up CPU based on model also includes：Order module 65, order module 65 is used for MUX
It is keyword, the item in the director data path is sorted.
Merging module 63 is led to specifically for data source and MUX as keyword, merging identical director data
Item in road.
Generation module 61 includes allocation unit 611 and generation unit 612, wherein, allocation unit 611 is used for the instruction
Implementation procedure be dispensed on fetching stage, decoding stage, execution stage, memory phase, write back stage；Generation unit 612
For the fetching stage according to the instruction, decoding stage, stage, memory phase, write back stage are performed, generate the instruction right
The director data path answered.
The structural model of the CPU includes：Digital logic component, digital logic component function and control signal logic are public
Formula, data path and clock cycle.
The device for setting up CPU based on model provided in an embodiment of the present invention can be provided specifically for performing above-mentioned Fig. 1
Embodiment of the method, here is omitted for concrete function.
The embodiment of the present invention, then by engineering comprehensive method, automatically generates CPU's according to every data path of instruction
Data path and control signal so that the design of the different instruction in instruction set is separate, and a design for instruction is simultaneously
Do not influence other to instruct, do not influenceed by other instructions yet so that the data path correlation of each instruction is relatively low, simplifies foundation
The method of CPU, reduces the error rate set up during CPU.
In sum, the embodiment of the present invention according to every instruction data path, then by engineering comprehensive method, automatically
Generate the data path and control signal of CPU so that the design of the different instruction in instruction set is separate a, instruction
Design have no effect on other instructions, also do not influenceed by other instructions so that the data path correlation for respectively instructing is relatively low, simple
Change the method for setting up CPU, reduce the error rate set up during CPU.
In several embodiments provided by the present invention, it should be understood that disclosed apparatus and method, can be by it
Its mode is realized.For example, device embodiment described above is only schematical, for example, the division of the unit, only
Only a kind of division of logic function, can there is other dividing mode when actually realizing, such as multiple units or component can be tied
Another system is closed or is desirably integrated into, or some features can be ignored, or do not perform.It is another, it is shown or discussed
Coupling each other or direct-coupling or communication connection can be the INDIRECT COUPLINGs or logical of device or unit by some interfaces
Letter connection, can be electrical, mechanical or other forms.
The unit that is illustrated as separating component can be or may not be it is physically separate, it is aobvious as unit
The part for showing can be or may not be physical location, you can with positioned at a place, or can also be distributed to multiple
On NE.Some or all of unit therein can be according to the actual needs selected to realize the mesh of this embodiment scheme
's.
In addition, during each functional unit in each embodiment of the invention can be integrated in a processing unit, it is also possible to
It is that unit is individually physically present, it is also possible to which two or more units are integrated in a unit.Above-mentioned integrated list
Unit can both be realized in the form of hardware, it would however also be possible to employ hardware adds the form of SFU software functional unit to realize.
The above-mentioned integrated unit realized in the form of SFU software functional unit, can store and be deposited in an embodied on computer readable
In storage media.Above-mentioned SFU software functional unit storage is in a storage medium, including some instructions are used to so that a computer
Equipment (can be personal computer, server, or network equipment etc.) or processor (processor) perform the present invention each
The part steps of embodiment methods described.And foregoing storage medium includes：USB flash disk, mobile hard disk, read-only storage (Read-
Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disc or CD etc. it is various
Can be with the medium of store program codes.
Those skilled in the art can be understood that, for convenience and simplicity of description, only with above-mentioned each functional module
Division carry out for example, in practical application, can distribute complete by different functional modules by above-mentioned functions as needed
Into, will the internal structure of device be divided into different functional modules, to complete all or part of function described above.On
The specific work process of the device of description is stated, the corresponding process in preceding method embodiment is may be referred to, be will not be repeated here.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
Pipe has been described in detail with reference to foregoing embodiments to the present invention, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, or which part or all technical characteristic are entered
Row equivalent；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (10)
1. a kind of method that CPU is set up based on model, it is characterised in that including：
According to the 26S Proteasome Structure and Function that each is instructed in instruction set, each corresponding director data path of instruction is generated；
MUX is inserted between the source and destination of each director data path, the control letter of MUX is generated
Number expression formula and register enable the logical expression of signal, and the control signal expression formula includes the stage letter that instruction is performed
Number, instruction operation code, instruction control code field；
Merge the item in identical director data path, while doing logic union operation to the control signal expression formula, obtain
Cpu data path；
According to the cpu data path, the structural information of the CPU is determined；
According to the control signal expression formula, the structural information of the control unit of the CPU is determined.
2. method according to claim 1, it is characterised in that item in the merging identical director data path it
Before, also include：
With MUX as keyword, the item in the director data path is sorted.
3. method according to claim 2, it is characterised in that the item in the merging identical director data path, bag
Include：
With data source and MUX as keyword, merge the item in identical director data path.
4. the method according to claim any one of 1-3, it is characterised in that the generation each corresponding instruction number of instruction
According to path, including：
The implementation procedure of the instruction is dispensed on fetching stage, decoding stage, the execution stage, memory phase, rank is write back
Section；
Fetching stage, decoding stage according to the instruction, execution stage, memory phase, write back stage, generate the instruction right
The director data path answered.
5. method according to claim 4, it is characterised in that the structural model of the CPU includes：Digital logic component,
Digital logic component function and control signal logical formula, data path and clock cycle.
6. a kind of device that CPU is set up based on model, it is characterised in that including：
Generation module, for according to the 26S Proteasome Structure and Function that each is instructed in instruction set, generating each corresponding director data of instruction
Path；
Insertion module, for inserting MUX between the source and destination of each director data path, generates multichannel
The control signal expression formula and register of selector enable the logical expression of signal, and the control signal expression formula includes instruction
The stage signal of execution, instruction operation code, instruction control code field；
Merging module, for merging the item in identical director data path, while doing logic to the control signal expression formula
Union operation, obtains cpu data path；
Determining module, for according to the cpu data path, determining the structural information of the CPU；According to the control signal table
Up to formula, the structural information of the control unit of the CPU is determined.
7. the device that CPU is set up based on model according to claim 6, it is characterised in that also include：
Order module, for MUX as keyword, being sorted to the item in the director data path.
8. the device that CPU is set up based on model according to claim 7, it is characterised in that the merging module is specifically used
In with data source and MUX as keyword, merge the item in identical director data path.
9. the device that CPU is set up based on model according to claim any one of 6-8, it is characterised in that the generation mould
Block includes：
Allocation unit, for the implementation procedure of the instruction being dispensed on into fetching stage, decoding stage, the execution stage, being deposited
Storage stage, write back stage；
Generation unit, for the fetching stage according to the instruction, decoding stage, performs stage, memory phase, write back stage,
The corresponding director data path of the generation instruction.
10. the device that CPU is set up based on model according to claim 9, it is characterised in that the structural model of the CPU
Including：Digital logic component, digital logic component function and control signal logical formula, data path and clock cycle.
Priority Applications (1)
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