CN106708237B - Power-off protection method, device and computer - Google Patents
Power-off protection method, device and computer Download PDFInfo
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- CN106708237B CN106708237B CN201710043719.7A CN201710043719A CN106708237B CN 106708237 B CN106708237 B CN 106708237B CN 201710043719 A CN201710043719 A CN 201710043719A CN 106708237 B CN106708237 B CN 106708237B
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- signal
- predetermined level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
Abstract
The invention discloses a kind of power-off protection method, device and computers, which comprises detection computer whether there is abnormal power-down；CMOS is reset, and reset signal is from the outer circuits that one includes power supply chip.The technical solution of the embodiment of the present invention is when there are when abnormal power-down for detection computer, then receive the CMOS on the resetting computer motherboard that outer circuits are sent, to reset the signal of the CMOS, the outer circuits include power supply chip, when can detect abnormal power-down in this way to avoid EC, power-off suddenly leads to the risk for sending resetting cmos signal failure.
Description
Technical field
The present invention relates to power-off protection technical field, in particular to a kind of power-off protection method, device and computer.
Background technique
In the use process of computer, sometimes there is the case where abnormal power-down: for example, laptop is in booting mould
Under formula, while removing power supply adaptor and battery.In this case, often will cause system can not normal boot-strap failure.
It in the prior art, can be by resetting complementary metal oxide semiconductor when there is this failure
(Complementary Metal Oxide Semiconductor, CMOS), to eliminate failure.But before and after resetting CMOS
In the process, disassembly and assembly computer is needed.Since the part of computer is very accurate and complicated, in an assembling process, hold very much
Easily there is a situation where lose part or assembly defect etc..
Summary of the invention
In view of this, the purpose of the embodiment of the present invention is that providing a kind of failure caused by repairing computer due to power-off
When, the power-off protection method, device and computer of failure can be repaired by not needing disassembly computer.
To achieve the goals above, the embodiment of the invention provides a kind of power-off protection methods, comprising:
Detecting computer whether there is abnormal power-down；
If it exists, then CMOS is reset, and reset signal is from the outer circuits that one includes power supply chip.
Preferably, resetting CMOS, comprising:
It receives and wakes up the reset signal that south bridge hangs up logic；
Receive the control signal of starting south bridge backup power source.
The reset signal that south bridge hangs up logic is waken up preferably, receiving, comprising:
The first predetermined level is set by the reset signal；
After first predetermined level continues preset time, the second predetermined level is set by the reset signal；It is described
Second predetermined level is higher than first predetermined level.
Preferably, receiving the control signal of starting south bridge backup power source, comprising:
After setting the second predetermined level for the reset signal, the control letter for starting the backup power source of the south bridge is received
Number.
The embodiment of the present invention also provides a kind of power-off protection apparatus, comprising:
Detection module is configured to detection computer with the presence or absence of abnormal power-down；
Receiving module is configured to when there are when abnormal power-down, reset the signal of CMOS, and reset signal for the computer
From the outer circuits in one including power supply chip.
Preferably, the receiving module, comprising:
First receiving submodule is configured to receive the reset signal for waking up south bridge hang-up logic；
Second receiving submodule is configured to receive the control signal of starting south bridge backup power source.
Preferably, first receiving submodule, comprising:
First setting submodule, is configured to set the first predetermined level for the reset signal；
Second setting submodule is configured to after first predetermined level continues preset time, the reset signal is set
It is set to the second predetermined level；Second predetermined level is higher than first predetermined level.
Preferably, second receiving submodule, comprising:
Third receiving submodule is configured to after setting the second predetermined level for the reset signal, is received described in starting
The control signal of the backup power source of south bridge.
The embodiment of the present invention also provides a kind of computer, and the computer includes device as described above, the computer
Mainboard on include outer circuits, the external circuit configuration be to send to reset the control of the CMOS on the computer motherboard and believe
Number.
Preferably, the outer circuits include the first field-effect tube, the second field-effect tube, first resistor and the second electricity
Resistance；The grid of first field-effect tube receives MPWRG signal, and the source electrode of first field-effect tube connects the first resistor
First end, the second end of the first resistor connects power supply, and the source electrode of first field-effect tube is also connected with described second
The grid of effect pipe, the grounded drain of first field-effect tube, the grounded drain of second field-effect tube, described second
The source electrode of effect pipe connects the first end of the second resistance, and the second end of the second resistance exports RSMRST signal.
Compared with prior art, the embodiment of the present invention has the advantages that the technical solution of the embodiment of the present invention is worked as
Detecting computer, there are the letters for when abnormal power-down, then receiving the CMOS on the resetting computer motherboard that outer circuits are sent
Number, to reset the CMOS, the outer circuits include power supply chip, when can detect abnormal power-down in this way to avoid EC, suddenly
Power-off leads to the risk for sending resetting cmos signal failure.
Detailed description of the invention
Fig. 1 be in the prior art abnormal power-down situation when RSMRST# signal power supply signal VCCPRIM corresponding with its illustrate
Figure；
Fig. 2 is the flow chart of the embodiment one of power-off protection method of the invention；
Fig. 3 is the flow chart of the embodiment two of power-off protection method of the invention；
Fig. 4 is the flow chart of the embodiment one of power-off protection apparatus of the invention；
Fig. 5 is the flow chart of the embodiment two of power-off protection apparatus of the invention；
Fig. 6 is the schematic diagram of the outer circuits of embodiment one of computer of the invention；
Fig. 7 is the RSMRST# signal and VCCPRIM signal schematic representation of the embodiment one of computer of the invention.
Specific embodiment
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.Implement below
Example is not intended to limit the scope of the invention for illustrating the present invention.
In the use process of computer, sometimes there is following situations: under power on mode, while removing power adaptation
Device and battery.In this case, it to prevent from causing clock (Real-Time Clock, RTC) to damage, needs to supply by power supply
Each device voltage of electricity exceeds before default normal range of operation, cuts off the RSMRST# signal of each device.It also means that, In
The supply voltage of south bridge is lower than before preset value, cuts off the RSMRST# signal of south bridge.Fig. 1 is in the prior art when being abnormal
When power-off, RSMRST# signal power supply signal VCCPRIM schematic diagram corresponding with its.
Wherein, RSMRST# signal is that south bridge returns to the reset signal for hanging up circuit.RSMRST# signal is for notifying south
The normal signal of bridge 5VSB and 3VSB standby voltage, for this signal if it is low, south bridge receives error information, it is believed that corresponding
There is no mistakes for standby voltage, so not will do it next step powers on movement.
VCCPRIM signal is power rail (power rail) signal of south bridge backup power source (standby power), mainly
Sharp technology is won for support Intel.
As seen from Figure 1, RSMRST# signal declines earlier than VCCPRIM signal, but since RSMRST# signal declines
Duration is too long, this will lead to, and has begun and has dropped in VCCPRIM signal, but RSMRST# signal has not been completed,
I.e. south bridge does not enter into hang-up logic.
By taking Intel chip as an example, the operating voltage of RSMRST# signal is -0.5V to 0.99V, that is to say, that prevent
It has begun and has dropped in VCCPRIM signal, south bridge has not been entered into the generation hung up this case that logic, needs
Before the decline of VCCPRIM signal, make the voltage of RSMRST# signal not less than 0.99V.
Other methods, computer glitch caused by preventing RTC from damaging can also be used.Due to the setting information of computer motherboard
It is stored in the CMOS of mainboard, it is therefore possible to use software mode, removes CMOS.When there are abnormal power-down the case where, if insertion
Formula controller (Embed Controller, EC) still can work normally, and EC, which is then issued, reduces RTCRST# and SRTCRST# letter
The control instruction of number level, so that system restores normal.But in this way, the information for removing CMOS will make computer
In date also remove, user also needs to reset the time.
Based on above analysis, it is as follows that the present invention provides embodiment:
Fig. 2 is the flow chart of the embodiment one of power-off protection method of the invention, as shown in Fig. 2, the power-off of the present embodiment
Guard method can specifically include following steps:
S201, detection computer whether there is abnormal power-down；If it exists, S202 is thened follow the steps, otherwise, is thened follow the steps
S203。
S202 resets CMOS, and reset signal is from the outer circuits that one includes power supply chip.
Specifically, CMOS can also be reset by EC, but when abnormal power-down, it is possible to EC is sending resetting not yet
When instruction, just not enough power supply can not send the instruction of resetting CMOS.And the present embodiment resets computer by outer circuits
CMOS on mainboard is provided with power supply chip in outer circuits, it is ensured that can send the instruction of resetting CMOS.
S203 starts computer.
Specifically, normal to start computer if there is no abnormal power-down situation.
Computer involved in this implementation includes the equipment such as laptop, desktop computer and server.
The technical solution of the embodiment of the present invention is when there are when abnormal power-down, then receive outer circuits transmission for detection computer
The signal of the CMOS on computer motherboard is reset, to reset CMOS, outer circuits include power supply chip, can be examined in this way to avoid EC
It when surveying abnormal power-down, powers off suddenly, leads to the risk for sending resetting cmos signal failure.
Fig. 3 is the flow chart of the embodiment two of power-off protection method of the invention, and the power-off protection method of the present embodiment exists
On the basis of above-described embodiment one, technical solution of the present invention is further introduced in further detail.As shown in figure 3, the present embodiment
Power-off protection method, can specifically include following steps:
S301, detection computer whether there is abnormal power-down；If it exists, S302 is thened follow the steps, otherwise, executes step
S304。
S302 is received and is waken up the reset signal that south bridge hangs up logic.
Specifically, five conditions of south bridge need of work: (1)+3V standby voltage；(2) restore reset signal RSMRST#, it should
Signal is effective when being low level, which is used to reset the sleep awakening logic of south bridge, when RSMRST# signal is if it is low electricity
Flat, then south bridge ACPI controller is in reset state always and can not power on；(3) RTC, real-time clock；(4) RTCRST uses reflex
Logic circuit inside the south bridge of position；(5)CLK(32.768KHZ).As it can be seen that waking up the reset signal that south bridge hangs up logic, i.e., southwards
Bridge sends RSMRST# signal.
Specifically, step S302, comprising: reset signal is set the first predetermined level by A；B, the first predetermined level are held
After continuous preset time, the second predetermined level is set by reset signal；Second predetermined level is higher than the first predetermined level.Namely
Saying reduces the level of RSMRST# signal first draws high again.In the specific implementation, the first predetermined level is 0.5V, the second default electricity
It puts down as 0.99V.
S303 receives the control signal of starting south bridge backup power source.
Specifically, S303 includes: C, after setting the second predetermined level for reset signal, receives the standby electricity of starting south bridge
The control signal in source.
The control signal for starting south bridge backup power source is VCCPRIM signal.
S304 starts computer.
Specifically, normal to start computer if there is no abnormal power-down situation.
Computer involved in this implementation includes the equipment such as laptop, desktop computer and server.
The technical solution of the embodiment of the present invention is when there are when abnormal power-down, then receive outer circuits transmission for detection computer
The signal of the CMOS on computer motherboard is reset, to reset CMOS, outer circuits include power supply chip, can be examined in this way to avoid EC
It when surveying abnormal power-down, powers off suddenly, leads to the risk for sending resetting cmos signal failure.
Fig. 4 is the schematic diagram of the embodiment one of power-off protection apparatus of the invention, as shown in figure 4, the power-off of the present embodiment
Protective device can specifically include detection module 41 and receiving module 43.
Detection module 41 is configured to detection computer with the presence or absence of abnormal power-down.
Receiving module 42 is configured to when there are when abnormal power-down, receive the resetting computer that outer circuits are sent for computer
The signal of CMOS on mainboard, to reset CMOS；Outer circuits include power supply chip.
The power-off protection apparatus of the present embodiment carries out the realization mechanism of power-off protection by using above-mentioned module to computer
It is identical as the realization mechanism of the power-off protection method of above-mentioned embodiment illustrated in fig. 2, above-mentioned embodiment illustrated in fig. 2 can be referred in detail
Record, details are not described herein.
Fig. 5 is the schematic diagram of the embodiment two of power-off protection apparatus of the invention, and the power-off protection apparatus of the present embodiment exists
On the basis of embodiment one as shown in Figure 4, technical solution of the present invention is further introduced in further detail.As shown in figure 5, this
The power-off protection apparatus of embodiment, can further include:
Receiving module 42, comprising:
First receiving submodule 421 is configured to receive the reset signal for waking up south bridge hang-up logic；
Second receiving submodule 422 is configured to receive the control signal of starting south bridge backup power source.
Further, the first receiving submodule 421, comprising:
First setting submodule, is configured to set reset signal to the first predetermined level；
Second setting submodule is configured to after the first predetermined level continues preset time, sets second for reset signal
Predetermined level；Second predetermined level is higher than the first predetermined level.
Further, the second receiving submodule 422, comprising:
Third receiving submodule is configured to after setting the second predetermined level for reset signal, receives the standby of starting south bridge
With the control signal of power supply.
The power-off protection apparatus of the present embodiment, by using above-mentioned module to the realization machine for carrying out power-off protection to computer
Make, in detail with reference to above-mentioned Fig. 3 shown in implementation identical as the realization mechanism of the power-off protection method of above-mentioned embodiment illustrated in fig. 3
The record of example, details are not described herein.
The present invention also provides a kind of computer, which includes the device as shown in Fig. 4 to 5, the mainboard of the computer
Upper includes outer circuits, which is the control signal for sending the CMOS on resetting computer motherboard.
As shown in fig. 6, outer circuits include the first field-effect tube Q1, the second field-effect tube Q2, first resistor R1With the second electricity
Hinder R2；First field-effect tube Q1Grid receive MPWRG signal, the first field-effect tube Q1Source electrode connect first resistor R1
One end, first resistor R1Second end connect power supply VCC, the first field-effect tube Q1Source electrode be also connected with the second field-effect tube Q2's
Grid, the first field-effect tube Q1Grounded drain, the second field-effect tube Q2Grounded drain, the second field-effect tube Q2Source electrode connect
Meet second resistance R2First end, second resistance R2Second end export RSMRST# signal.
Wherein, MPWRG signal is the power supply signal that power supervisor is sent to south bridge, to notify south bridge voltage normal.When
MPWRG signal is high level, then the first field-effect tube Q1Grid receive high level signal, source electrode and drain electrode conducting, power supply
Pass through first resistor R1With the first field-effect tube Q1Start to discharge, the second field-effect tube Q2Grid be low level, therefore,
RSMRST# signal remains high level signal；When being abnormal power-off, MPWRG signal will become low level, the first field-effect
Pipe Q1Source electrode and drain electrode be not turned on, the second field-effect tube Q2Grid receive high level signal, source electrode and drain electrode conducting, this
When, RSMRST# signal becomes low level signal.
As shown in fig. 7, after by above-mentioned external circuit control RSMRST# signal, when notebook abnormal power-down,
The decline of RSMRST# signal voltage, but will rise rapidly before the decline of VCCPRIM signal to 0.99V or more, and south bridge exists
RSMRST# signal, which has to enter when fluctuation, hangs up logic, and will not remove the information stored in CMOS in this way.
Above embodiments are only exemplary embodiment of the present invention, are not used in the limitation present invention, protection scope of the present invention
It is defined by the claims.Those skilled in the art can within the spirit and scope of the present invention make respectively the present invention
Kind modification or equivalent replacement, this modification or equivalent replacement also should be regarded as being within the scope of the present invention.
Claims (8)
1. a kind of power-off protection method characterized by comprising
Detecting computer whether there is abnormal power-down；
If it exists, then CMOS is reset, and reset signal is from the support of the outer circuits including power supply chip；
Wherein, CMOS is reset, comprising:
It receives and wakes up the reset signal that south bridge hangs up logic；
Receive the control signal of starting south bridge backup power source.
2. waking up the reset signal that south bridge hangs up logic the method according to claim 1, wherein receiving, comprising:
The first predetermined level is set by the reset signal；
After first predetermined level continues preset time, the second predetermined level is set by the reset signal；Described second
Predetermined level is higher than first predetermined level.
3. according to the method described in claim 2, it is characterized in that, receiving the control signal of starting south bridge backup power source, comprising:
After setting the second predetermined level for the reset signal, the control signal for starting the backup power source of the south bridge is received.
4. a kind of power-off protection apparatus characterized by comprising
Detection module is configured to detection computer with the presence or absence of abnormal power-down；
Receiving module is configured to when the computer is there are when abnormal power-down, resetting the signal of CMOS, and reset signal from
One includes the support of the outer circuits of power supply chip；
Wherein, the receiving module, comprising:
First receiving submodule is configured to receive the reset signal for waking up south bridge hang-up logic；
Second receiving submodule is configured to receive the control signal of starting south bridge backup power source.
5. device according to claim 4, which is characterized in that first receiving submodule, comprising:
First setting submodule, is configured to set the first predetermined level for the reset signal；
Second setting submodule is configured to after first predetermined level continues preset time, sets the reset signal to
Second predetermined level；Second predetermined level is higher than first predetermined level.
6. device according to claim 5, which is characterized in that second receiving submodule, comprising:
Third receiving submodule is configured to after setting the second predetermined level for the reset signal, is received and is started the south bridge
Backup power source control signal.
7. a kind of computer, which is characterized in that the computer includes the device as described in any one of claim 4 to 6, institute
Stating includes outer circuits on the mainboard of computer, and the external circuit configuration is to send the CMOS reset on the computer motherboard
Control signal.
8. computer according to claim 7, which is characterized in that the outer circuits include the first field-effect tube, second
Field-effect tube, first resistor and second resistance；The grid of first field-effect tube receives MPWRG signal, first effect
Should the source electrode of pipe connect the first end of the first resistor, the second end of the first resistor connects power supply, first effect
Should the source electrode of pipe be also connected with the grid of second field-effect tube, the grounded drain of first field-effect tube, described second
The source electrode of the grounded drain of effect pipe, second field-effect tube connects the first end of the second resistance, the second resistance
Second end export RSMRST# signal.
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| CN106708237B true CN106708237B (en) | 2019-11-12 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038563A (en) * | 2006-03-17 | 2007-09-19 | 联想(北京)有限公司 | Method and device remotely automatic recovering CMOS date with network |
| CN201503569U (en) * | 2009-09-02 | 2010-06-09 | 鸿富锦精密工业（深圳）有限公司 | South bridge chip power supply circuit |
| CN103064486A (en) * | 2011-10-18 | 2013-04-24 | 纬创资通股份有限公司 | Computer device and method for resetting real-time clock signal thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102981585A (en) * | 2011-09-06 | 2013-03-20 | 鸿富锦精密工业（深圳）有限公司 | Complementary metal-oxide-semiconductor (CMOS) chip information clear circuit |
| CN105759663B (en) * | 2014-12-16 | 2019-08-20 | 研祥智能科技股份有限公司 | Industrial device controls treating method and apparatus |
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2017
- 2017-01-19 CN CN201710043719.7A patent/CN106708237B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038563A (en) * | 2006-03-17 | 2007-09-19 | 联想(北京)有限公司 | Method and device remotely automatic recovering CMOS date with network |
| CN201503569U (en) * | 2009-09-02 | 2010-06-09 | 鸿富锦精密工业（深圳）有限公司 | South bridge chip power supply circuit |
| CN103064486A (en) * | 2011-10-18 | 2013-04-24 | 纬创资通股份有限公司 | Computer device and method for resetting real-time clock signal thereof |
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