CN106685461A - Digital intercom terminal - Google Patents
Digital intercom terminal Download PDFInfo
- Publication number
- CN106685461A CN106685461A CN201710073930.3A CN201710073930A CN106685461A CN 106685461 A CN106685461 A CN 106685461A CN 201710073930 A CN201710073930 A CN 201710073930A CN 106685461 A CN106685461 A CN 106685461A
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- China
- Prior art keywords
- voltage
- power
- unit
- intercom terminal
- gradient value
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/3827—Portable transceivers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q5/00—Selecting arrangements wherein two or more subscriber stations are connected by the same line to the exchange
- H04Q5/24—Selecting arrangements wherein two or more subscriber stations are connected by the same line to the exchange for two-party-line systems
Abstract
The invention discloses a digital intercom terminal which comprises an integrated intercom chip with zero middle frequency digital communication. The integrated intercom chip produces the voltage step wave rising along the gradient and falling along the gradient according to the gradient voltage value of the internal storage, the voltage step wave is output as the bias voltage of the power amplifying unit; in this way, the digital intercom terminal generate the bias voltage and control the amplifying power of the amplifying unit through the step wave, since the rising edge and declining edge of the voltage step wave are slowly changed, the corresponding variation of the bias voltage is also gradually changed, and then the amplifying power of power amplifying unit also slowly declines and rises, the corresponding voltage is gradient, and then the amplifying power of the power amplifying unit slowly rises and declines, the DMR requirement for the digital intercom emission power curve which slowly declines and falls is met, the scattering of time slot switch is reduced.
Description
Technical field
The present invention relates to digital intercom field, more particularly to a kind of digital intercom terminal.
Background technology
In existing simulation intercommunication field, it is necessary to be controlled to amplifying power, it is specifically：Micro-control unit MCU is exported
, to computing comparing unit, computing comparing unit is according to square wave and the real-time amplifying power of power amplification unit, output biasing for square wave
Voltage, according to bias voltage, treat process signal carries out power amplification to power amplification unit.
But, it is to carry out at once and moment completion because square wave is when level overturns, this results in the change of bias voltage
Change is also mutation, and then causes the amplifying power of power amplification unit to be also transition.And digital wireless communication technology (DMR)
For digital handset, it is desirable to when its transmission power rapid increase is with declining, power curve needs slow rise and fall on request,
This results in technology of the existing analog-interphone using the changed power of square wave control power amplification unit, it is impossible to meet numeral right
The requirement of machine is said, and then cannot also apply to digital intercom field.
The content of the invention
The invention provides a kind of digital intercom terminal, to provide a kind of digital intercom terminal for meeting DMR requirements.
The invention provides a kind of digital intercom terminal, including：Power supply, the collection for possessing zero intermediate frequency digital communication functions
Into intercommunication chip, power amplification unit；Power supply is integrated talkback chip, power amplification unit is powered；Integrated talkback chip
For the voltage gradient value according to its storage inside, the voltage ladder ripple of generation rising edge gradual change and trailing edge gradual change, by voltage
Staircase waveform is exported as the bias voltage of power amplification unit；Power amplification unit is treated process signal and is entered according to bias voltage
Row power amplification.
Further, the rising edge fade time of voltage ladder ripple is more than 0.5 millisecond, less than 1.5 milliseconds, voltage ladder ripple
Trailing edge fade time be more than 0.5 millisecond, less than 1.5 milliseconds.
Further, the rising edge fade time and trailing edge fade time of voltage ladder ripple are 1 millisecond.
Further, the rising edge grading profile and trailing edge grading profile of staircase waveform are smoothed curve or straight line.
Further, voltage gradient value includes rising voltage gradient value and decline voltage gradient value, rises voltage gradient value
Multiple magnitudes of voltage it is incremented by successively, decline voltage gradient value multiple magnitudes of voltage successively decrease successively.
Further, rise voltage gradient value and decline voltage gradient value number respectively with the smoothness of its grading profile
It is required that corresponding.
Further, the number for rising voltage gradient value and declining voltage gradient value is respectively 128.
Further, integrated talkback chip includes microprocessing unit, memory cell and the digital-to-analogue conversion as peripheral hardware
Unit；Memory cell is used to store voltage gradient value, and microprocessing unit is used to control D/A conversion unit to obtain gradual change successively
Magnitude of voltage, D/A conversion unit is used to produce voltage ladder ripple according to voltage gradient value.
Further, integrated talkback chip includes also including, as the DMA controller of peripheral hardware, directly depositing
The memory register of access to store controller with the first address of memory cell, post by the peripheral hardware of DMA controller
With the address that value register is changed in D/A conversion unit, the transmission means of DMA controller is internal memory to storage
Peripheral hardware and every time one word of transmission are transferred to, the trigger source of DMA controller is timer.
Further, the memory cell is pseudo-static random access memory, the magnitude of voltage being made up of 128 magnitudes of voltage
Table is stored in sequence in the pseudo-static random access memory, and the microprocessing unit is used for when transmitting is started, during by setting
Between, by incremental order take out magnitude of voltage from the magnitude of voltage table, exported by D/A conversion unit, when transmitting is closed, by setting
Fixed time, by successively decreasing, order takes out magnitude of voltage from the magnitude of voltage table, is exported by the D/A conversion unit.
Beneficial effects of the present invention：
The invention provides a kind of new digital intercom terminal, it includes that the collection for possessing zero intermediate frequency digital communication functions is paired
Chip is said, integrated talkback chip is used for the voltage gradient value according to its storage inside, generates rising edge gradual change and trailing edge gradual change
Voltage ladder ripple, using voltage ladder ripple as power amplification unit bias voltage export；So, digital intercom terminal is realized
Bias voltage is generated using staircase waveform, the amplifying power of power amplification unit root is controlled, in whole process, due to ladder
The rising edge and trailing edge of ripple are all slow gradual changes, and the change of the bias voltage of correspondence generation is also gradual change, herein basis
On, the amplifying power of power amplification unit is also the slow digital handset transmitting work(for rising and declining, meet DMR requirements
When rate rapid increase is with declining, power curve needs slow rise and fall on request, meanwhile, the slow rising of this power curve
And decline can also reduce scattering when time slot switches, and reduce the interference to other chips or device.
Brief description of the drawings
The structural representation of the digital intercom terminal that Fig. 1 is provided for first embodiment of the invention；
The structural representation of the digital intercom chip that Fig. 2 is related to for first embodiment of the invention；
The first schematic diagram for the voltage ladder ripple that Fig. 3 is provided for first embodiment of the invention；
Second schematic diagram of the voltage ladder ripple that Fig. 4 is provided for first embodiment of the invention；
The circuit connection diagram of the digital intercom terminal that Fig. 5 is provided for second embodiment of the invention；
The circuit connection diagram of the integrated talkback chip that Fig. 6 is provided for second embodiment of the invention；
The circuit connection diagram of the integrated talkback chip that Fig. 7 is related to for second embodiment of the invention.
Specific embodiment
The further annotation explanation of output is now done to the present invention by way of specific embodiment combination accompanying drawing.
First embodiment：
The structural representation of the digital intercom terminal that Fig. 1 is provided for first embodiment of the invention, as shown in Figure 1, in this reality
Apply in example, the digital intercom terminal that the present invention is provided includes：Power supply 11, the collection for possessing zero intermediate frequency digital communication functions are paired
Say chip SOC (system level chip) 12, power amplification unit 13；Power supply is integrated talkback chip, power amplification unit confession
Electricity；Power supply 11 is integrated talkback chip 12, power amplification unit 13 is powered；Integrated talkback chip 12 is used to be calculated using function
The voltage ladder ripple of method, the voltage gradient value according to its storage inside, generation rising edge gradual change and trailing edge gradual change, by voltage steps
Terraced ripple is exported as the bias voltage of power amplification unit, such as schematic diagram of Fig. 1, and specific signal as shown in figs. 3 and 4
Figure；According to bias voltage, treat process signal carries out power amplification to power amplification unit 13.In actual applications, power amplification
Unit 13 obtains electric energy from power supply, if working and how working is limited by with the presence or absence of bias voltage and bias voltage
Size variation control.
As shown in figure 3 or 4, in certain embodiments, the rising edge fade time of the staircase waveform in above-described embodiment is more than
0.5 millisecond, less than 1.5 milliseconds, the trailing edge fade time of staircase waveform is more than 0.5 millisecond, less than 1.5 milliseconds.
As shown in figure 3 or 4, in certain embodiments, the rising edge fade time of the staircase waveform in above-described embodiment and under
Drop is 1 millisecond along fade time.
As shown in figure 3 or 4, in certain embodiments, the high level lasting time of the staircase waveform in above-described embodiment is
27.5 milliseconds.
As shown in figure 3, in certain embodiments, the rising edge grading profile and trailing edge of the staircase waveform in above-described embodiment
Grading profile includes at least 2 ladders.In actual applications, ladder quantity is more, rises and downward trend is gentler, its effect
Fruit is better.
As shown in figure 4, in certain embodiments, the rising edge grading profile and trailing edge of the staircase waveform in above-described embodiment
Grading profile is smoothed curve or straight line.
As shown in Fig. 2 in certain embodiments, the integrated talkback chip 12 in above-described embodiment includes microprocessing unit
121st, memory cell 122 and the D/A conversion unit 123 as peripheral hardware；Memory cell 122 is used to store voltage gradient
Value, microprocessing unit 121 is used to control D/A conversion unit 123 to obtain voltage gradient value successively, and D/A conversion unit 123 is used for
Voltage ladder ripple is produced according to voltage gradient value.
As shown in Fig. 2 in certain embodiments, the integrated talkback chip 12 in above-described embodiment includes also including as outer
If DMA controller DMA (Direct Memory Access, direct memory access, be one kind without CPU
And directly from the data exchange mode of memory access data) 124, the memory register of DMA controller 124 is write
There is the first address of memory cell, the peripheral hardware register of DMA controller is with conversion value in D/A conversion unit
The address of register, the transmission means of DMA controller is that internal memory is transferred to peripheral hardware and every time one word of transmission,
The trigger source of DMA controller is timer.
In certain embodiments, the memory cell in above-described embodiment is PSRAM (pseudo-static random access memory), by
The magnitude of voltage table of 128 magnitude of voltage compositions is stored in sequence in the pseudo-static random access memory, the microprocessing unit
For when transmitting is started, by setting time (1 millisecond of 128 point, each point interval 7.8us), by incremental order from the electricity
Pressure value table takes out magnitude of voltage, is exported by D/A conversion unit, when transmitting is closed, according to set time (1 millisecond of 128 point,
Each point interval 7.8us), by successively decrease order from the magnitude of voltage table take out magnitude of voltage, exported by the D/A conversion unit.
A kind of new digital intercom terminal is present embodiments provided, it includes possessing the integrated of zero intermediate frequency digital communication functions
Intercommunication chip, integrated talkback chip is used for the voltage gradient value according to its storage inside, and generation rising edge gradual change and trailing edge are gradually
The voltage ladder ripple of change, exports voltage ladder ripple as the bias voltage of power amplification unit；So, digital intercom terminal reality
Show using staircase waveform to generate bias voltage, the amplifying power of power amplification unit root has been controlled, in whole process, due to rank
The rising edge and trailing edge of terraced ripple are all slow gradual changes, and the change of the bias voltage of correspondence generation is also gradual change, in this base
On plinth, the amplifying power of power amplification unit is also the slow digital handset transmitting for rising and declining, meet DMR requirements
Power rapid increase with decline when, power curve need slow rise and fall on request, meanwhile, this power curve it is slow on
Scattering when can also reduce time slot switching is risen and declined, the interference to other chips or device is reduced.
In conjunction with concrete application scene, further annotation explanation is done to the present invention.
Second embodiment：
The present embodiment is illustrated by taking a kind of concrete application of voltage ladder ripple as an example, electricity of the numeral that it is related to terminal
Road is as shown in figure 5, it includes：Possess zero intermediate frequency digital communication functions integrated talkback chip SOC (system level chip) 51 (as
Micro-control unit in above-described embodiment), comparator 52 (as the comparison control circuit in above-described embodiment), pressure difference are relatively put
Big device 53, detection resistance 54 (for 3 resistor coupled in parallel are formed in Fig. 5), 2 stage power amplifier 55-1 and 55-2 are (as above-mentioned reality
Apply the power amplification unit in example), and the power supply not shown in Fig. 5.
In actual applications, the supply voltage of 2 stage power amplifier 55-1 and 55-2 is the magnitude of voltage U of stabilization, and its is real-time
Amplifying power P (real-time)=U*I (real-time)；The resistance R of detection resistance 54 is constant, and the pressure difference U (pressure difference) at its two ends is with power supply
Change, i.e. U (pressure difference)=R*I (real-time) for the change of the supply current I (real-time) of 2 stage power amplifier 55-1 and 55-2；
Therefore, U (pressure difference)=(R/U) * P (real-time), both proportional relations, the i.e. change of U (pressure difference) can reflect P's (real-time)
Change, then, the present embodiment is capable of achieving the detection to P (real-time) by detecting U (pressure difference).
The working mechanism of comparator 52 is negative feedback mechanism, and power threshold (best effort is more than when the P for detecting is (real-time)
Power) when, i.e. when U (pressure difference) is more than voltage threshold (corresponding with best effort power), then need to reduce bias voltage U (partially
Put), it is close to it and is changed into best effort power reduces P (real-time), it is corresponding, it is less than power when the P for detecting is (real-time)
During threshold value (best effort power), i.e. when U (pressure difference) is less than voltage threshold (corresponding with best effort power), then need increase inclined
Voltage U (biasing) is put, it is close to and is changed into best effort power to increase P (real-time), caused by this negative feedback mechanism
Power amplification unit is operated in best effort power as far as possible.
The core of the present embodiment is integrated talkback chip SOC51, and it is used to use function algorithm, generates such as Fig. 3 or Fig. 4 institutes
The staircase waveform (optimal is that rising edge and trailing edge are all smooth curves as shown in Figure 4) for showing, so, digital intercom
System realizes using staircase waveform to generate bias voltage, controls the amplifying power of power amplification unit root, in whole process,
Because the rising edge and trailing edge of staircase waveform are all slow gradual changes, the change of the bias voltage of correspondence generation is also gradual change,
On this basis, the amplifying power of power amplification unit is also slow rising and declines, and meets the digital intercom of DMR requirements
When machine transmission power rapid increase is with declining, power curve needs slow rise and fall on request, meanwhile, this power curve
It is slow to rise and decline scattering when reduce time slot switching, reduce the interference to other chips or device.
Meanwhile, the present embodiment also provides a kind of specific schematic diagram of integrated talkback chip SOC51, as shown in fig. 6, this reality
The integrated talkback chip SOC51 for applying example offer includes：61,16 voice signal codec units of Digital Signal Processing DSP unit
62nd, sound output amplifier unit 63,64,32 reduced instruction microprocessor units 65 of microphone amplifying circuit unit,
Power management PMU units 66,16MB PSRAM memory cells 67,16MB FLASH memories unit 68 and radio frequency mobile wireless
Electric receiver transmitter unit 69, and some unshowned data-interfaces etc.；Wherein, 16MB PSRAM memory cells 67 with
16MB FLASH memories unit 68 can exist simultaneously, it is also possible to only exist one；Radio frequency mobile radio receiver is launched
Machine unit 69 is used to use low pressure (2.4V) wideband (100-500MHz, 700-1000MHz) voltage-controlled technical finesse data, power supply pipe
The extraneous voltage (3.2-4.2V, generally 3.7V) for providing is converted to 1.4V and 2.4V voltages by reason (PMU) unit 66, wherein
1.4V voltages supply Digital Signal Processing (DSP) unit 61,6MB PSRAM memory cells 67,16MB FLASH memory units
68 are used, and 2.4V voltages are used for other units.
Specifically, the circuit connection diagram of integrated talkback chip that the present embodiment is related to is as shown in fig. 7, repeat no more.
In actual applications, DMR protocol requirements must meet power linear in 1.25ms when radio-frequency transmissions are started and be incremented by,
Must meet power linear in 1.25ms when transmitting is closed to successively decrease.And power linear be incremented by be by D/A converter module DA come
Control PA circuit realirations, this is accomplished by DA uniform 128 electrical voltage points of output in 1.25ms from transmitting that time is started, and this 128
Individual point needs linear incremental from 0~3.3V.128 electrical voltage points are uniformly exported from that time in 1.25ms stopping launching, this 128
Individual point needs linearly to successively decrease from 3.3~0V.
And if realizing this function with software merely, then need to go to operate a DA every about 9.7us, this will
Cause in the 1.25ms for starting and stopping transmitting that time, cpu can only process DA functions, and can not process other things.This
Embodiment provide integrated talkback chip realize it is soft or hard work in coordination to complete this function, software only needs to have configured hardware
Afterwards, hardware effort is started.
The principle of the present embodiment is：
First be stored in 128 magnitudes of voltage to be converted in RAM by cpu, and triggering DMA is arrived by RAM by timer count
Data are put into the register to be converted of DA.So circulation achieves that 128 points reach DMR requirements automatically by DA conversions
1.25ms in realize voltage linear export.
In actual applications, the step of realizing includes：
The corresponding data of 128 magnitudes of voltage (generally 2 binary digits) that step 1.cpu will be calculated are stored in RAM；
Step 2. configures DMA；
This step is again detailed to be comprised the following steps：
A. the RAM first address that will have 128 point points is put into DMA memory registers；
B. the address of DA conversion value registers is put into DMA peripheral hardware registers；
C. it is that internal memory is transferred to peripheral hardware to set DMA transfer mode, and configuration is transmitted into a word every time；
D., DMA trigger sources are set, DMA trigger sources are set to timer TIMER；
Step 3. starts TIMER；
Step 4. starts DA.
DA can export 128 voltages to control PA circuits so as to reality uniformly through DA pins PIN so in 1.25ms
The linear power control of existing DMR protocol requirements.Start transmitting with close the linear Power Control of transmitting be as except that
It is linear increment to start emitting voltage, and it is linear decline to stop emitting voltage, therefore it is by incremental to start 128 voltages of transmitting
RAM is stored in, and is stopped 128 voltages of transmitting and is stored in RAM by successively decreasing.
In summary, by implementation of the invention, at least there is following beneficial effect：
The invention provides a kind of new digital intercom terminal, it includes that the collection for possessing zero intermediate frequency digital communication functions is paired
Chip is said, integrated talkback chip is used for the voltage gradient value according to its storage inside, generates rising edge gradual change and trailing edge gradual change
Voltage ladder ripple, using voltage ladder ripple as power amplification unit bias voltage export；So, digital intercom terminal is realized
Bias voltage is generated using staircase waveform, the amplifying power of power amplification unit root is controlled, in whole process, due to ladder
The rising edge and trailing edge of ripple are all slow gradual changes, and the change of the bias voltage of correspondence generation is also gradual change, herein basis
On, the amplifying power of power amplification unit is also the slow digital handset transmitting work(for rising and declining, meet DMR requirements
When rate rapid increase is with declining, power curve needs slow rise and fall on request, meanwhile, the slow rising of this power curve
And decline can also reduce scattering when time slot switches, and reduce the interference to other chips or device.
The above is only specific embodiment of the invention, any formal limitation is not done to the present invention, it is every
Any simple modification made to embodiment of above according to technical spirit of the invention, equivalent variations, with reference to or modification, still
Belong to the protection domain of technical solution of the present invention.
Claims (10)
1. a kind of digital intercom terminal, it is characterised in that including：Power supply, possess the integrated of zero intermediate frequency digital communication functions
Intercommunication chip, power amplification unit；The power supply is the integrated talkback chip, power amplification unit is powered；The collection
It is used for the voltage ladder of the voltage gradient value according to its storage inside, generation rising edge gradual change and trailing edge gradual change into intercommunication chip
Ripple, exports the voltage ladder ripple as the bias voltage of the power amplification unit；The power amplification unit is according to institute
Bias voltage is stated, treating process signal carries out power amplification.
2. digital intercom terminal as claimed in claim 1, it is characterised in that the rising edge fade time of the voltage ladder ripple
More than 0.5 millisecond, less than 1.5 milliseconds, the trailing edge fade time of the voltage ladder ripple is more than 0.5 millisecond, less than 1.5 millis
Second.
3. digital intercom terminal as claimed in claim 2, it is characterised in that the rising edge fade time of the voltage ladder ripple
And trailing edge fade time is 1 millisecond.
4. digital intercom terminal as claimed in claim 1, it is characterised in that the rising edge grading profile of the staircase waveform and under
Drop is smoothed curve or straight line along grading profile.
5. digital intercom terminal as claimed in claim 1, it is characterised in that the voltage gradient value includes rising voltage gradient
Value and decline voltage gradient value, multiple magnitudes of voltage of the rising voltage gradient value are incremented by successively, the decline voltage gradient value
Multiple magnitudes of voltage successively decrease successively.
6. digital intercom terminal as claimed in claim 5, it is characterised in that the rising voltage gradient value and the decline are gradually
Smoothness requirements of the number of time variant voltage value respectively with its grading profile are corresponding.
7. digital intercom terminal as claimed in claim 6, it is characterised in that the rising voltage gradient value and the decline are gradually
The number of time variant voltage value is respectively 128.
8. the digital intercom terminal as described in any one of claim 1 to 7, it is characterised in that the integrated talkback chip includes
Microprocessing unit, memory cell and the D/A conversion unit as peripheral hardware；The memory cell be used to storing it is described gradually
Time variant voltage value, the microprocessing unit is used to control the D/A conversion unit to obtain the voltage gradient value, the number successively
Mould converting unit is used to produce the voltage ladder ripple according to the voltage gradient value.
9. digital intercom terminal as claimed in claim 8, it is characterised in that the integrated talkback chip includes also including conduct
The DMA controller of peripheral hardware, the memory register of the DMA controller is with the memory
The first address of unit, the peripheral hardware register write of the DMA controller has conversion value in the D/A conversion unit
The address of register, the transmission means of the DMA controller is that internal memory is transferred to peripheral hardware and transmits one every time
Individual word, the trigger source of the DMA controller is timer.
10. digital intercom terminal as claimed in claim 8, it is characterised in that the memory cell is that pseudo- static random is deposited
Reservoir, the magnitude of voltage table being made up of 128 magnitudes of voltage is stored in sequence in the pseudo-static random access memory, micro- place
Reason unit is used to, when transmitting is started, magnitude of voltage is taken out from the magnitude of voltage table by setting time, by incremental order, by digital-to-analogue
Converting unit is exported, and when transmitting is closed, order takes out magnitude of voltage from the magnitude of voltage table according to set time, by successively decreasing, and leads to
Cross the D/A conversion unit output.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710073930.3A CN106685461B (en) | 2017-02-10 | 2017-02-10 | Digital talkback terminal |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710073930.3A CN106685461B (en) | 2017-02-10 | 2017-02-10 | Digital talkback terminal |
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| CN106685461A true CN106685461A (en) | 2017-05-17 |
| CN106685461B CN106685461B (en) | 2020-04-17 |
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|---|---|---|---|---|
| CN1596505A (en) * | 2001-11-28 | 2005-03-16 | Ttpcom有限公司 | Transmitter RF power control |
| CN101394195A (en) * | 2008-10-17 | 2009-03-25 | 闻泰集团有限公司 | Method for suppressing GSM stray |
| US20110298540A1 (en) * | 2010-06-04 | 2011-12-08 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | System and method for controlling a power amplifier using a programmable ramp circuit |
| US20120126892A1 (en) * | 2010-09-08 | 2012-05-24 | Stmicroelectronics (Grenoble 2) Sas | Reference voltage generator for biasing an amplifier |
| CN103546958A (en) * | 2007-04-27 | 2014-01-29 | 瑞萨电子株式会社 | Transmitter, RF transmitter signal processor and method for operation of transmitter |
| CN205029811U (en) * | 2015-09-29 | 2016-02-10 | 深圳市万博鑫科技有限公司 | Duplexing intercom of digit |
-
2017
- 2017-02-10 CN CN201710073930.3A patent/CN106685461B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1596505A (en) * | 2001-11-28 | 2005-03-16 | Ttpcom有限公司 | Transmitter RF power control |
| CN103546958A (en) * | 2007-04-27 | 2014-01-29 | 瑞萨电子株式会社 | Transmitter, RF transmitter signal processor and method for operation of transmitter |
| CN101394195A (en) * | 2008-10-17 | 2009-03-25 | 闻泰集团有限公司 | Method for suppressing GSM stray |
| US20110298540A1 (en) * | 2010-06-04 | 2011-12-08 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | System and method for controlling a power amplifier using a programmable ramp circuit |
| US20120126892A1 (en) * | 2010-09-08 | 2012-05-24 | Stmicroelectronics (Grenoble 2) Sas | Reference voltage generator for biasing an amplifier |
| CN205029811U (en) * | 2015-09-29 | 2016-02-10 | 深圳市万博鑫科技有限公司 | Duplexing intercom of digit |
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| CN106685461B (en) | 2020-04-17 |
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