CN106682315B - Through silicon via analysis method for reliability - Google Patents

Through silicon via analysis method for reliability Download PDF

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CN106682315B
CN106682315B CN201611244489.2A CN201611244489A CN106682315B CN 106682315 B CN106682315 B CN 106682315B CN 201611244489 A CN201611244489 A CN 201611244489A CN 106682315 B CN106682315 B CN 106682315B
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silicon via
heat distribution
excitation
temperature
silicon
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CN106682315A (en
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董刚
何映婷
杨银堂
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Chongqing Institute Of Integrated Circuit Innovation Xi'an University Of Electronic Science And Technology
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Xian University of Electronic Science and Technology
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Abstract

The invention discloses a kind of through silicon via analysis method for reliability, mainly solve that simulation time in the prior art is long, consumption stores big problem.Its technical solution is: 1) extracting the physical parameter of layers of material inside and outside through silicon via；2) the environment temperature T and extrinsic motivated of through silicon via are inputted；1) and 2) 3) using the parameter in, through silicon via heat distribution is calculated；4) temperature of through silicon via different location is obtained to through silicon via heat distribution sampling site using Matlab；5) according to the temperature of through silicon via different location, the mean temperature difference of through silicon via is calculated6) total amount of heat Q in the unit of account time；7) according to the temperature differenceWith gross energy Q, an equivalent thermal capacitance value is obtained；8) condition is converted, new through silicon via heat distribution is obtained, is repeated 3)~7) obtain one group of equivalent thermal capacitance value；7) and 8) 9) using the equivalent thermal capacitance value in, stress simulation is carried out.Present invention reduces simulation times, reduce amount of storage, can be used for the three dimensional integrated circuits design optimization of through silicon via.

Description

Through silicon via analysis method for reliability
Technical field
The invention belongs to microelectronics technology, in particular to a kind of through silicon via analysis method for reliability can be used for three-dimensional The design optimization of integrated circuit.
Background technique
Through silicon via TSV technology is that semiconductor IC industry is marched toward the key technology in 3D epoch.But 3D-TSV technology Not yet full maturity, integrity problem have become the major obstacle of TSV technology development.Most researchers pass through software building silicon The finite element model of through-hole analyzes the reliability of through silicon via, however very multiple the case where through silicon via in practical three dimensional integrated circuits Miscellaneous, using multi- scenarios method model analysis, low efficiency needs storage resource big, especially for large-scale three dimensional integrated circuits Middle through silicon via fail-safe analysis, the multi- scenarios method model degree of convergence is low, can not be achieved substantially, can not accurately instruct three-dimensionally integrated The design optimization of circuit.
“Study on coupling analysis of electromagnetic-thermal-structure for TSV ", Nanjing, 210003, China, this paper disclose a kind of through silicon via thermodynamic analysis of electrothermal forces THM coupling Method, article use finite element model, derive since each basic physical equation, to construct model, there are three The deficiency of aspect: first is that model excessively idealizes, the case where not accounting for through silicon via in practical three dimensional integrated circuits；Second is that directly Long using electrothermal forces THM coupling simulation time, the storage resource needed is big；Third is that the model only analyzes silicon under Gaussian pulse The stress situation of through-hole does not account for the case where generating stress under different extrinsic motivateds around through silicon via.
Summary of the invention
It is an object of the invention in view of the deficiency of the prior art, propose a kind of through silicon via fail-safe analysis side Method, to realize the fail-safe analysis to through silicon via in three dimensional integrated circuits.
Technical thought of the invention is to extract the physical parameter of through silicon via in circuit；It inputs additional used in through silicon via Excitation and environment temperature；By the heat distribution mathematical model in through silicon via, the distribution of temperature is obtained；It is obtained using Matlab sampling site Through silicon via mean temperature difference is calculated in the temperature of different location；Excitation gross energy is calculated according to extrinsic motivated；It is logical by silicon A thermal capacitance value is calculated in the mean temperature difference and excitation gross energy in hole；Then condition is reset, new through silicon via heat distribution is obtained Function repeats the above steps to obtain one group of thermal capacitance value；Obtained all thermal capacitance values are finally loaded into the circuit of Comsol building It in model, is coupled using thermal field, emulation obtains maximum stress value around through silicon via.Implementation step includes the following:
(1) physical parameter of layers of material inside and outside through silicon via used in circuit is extracted；
(2) extrinsic motivated and environment temperature T used in through silicon via are inputted；
(3) heat distribution of through silicon via is calculated；
Justified according to the physical parameter of through silicon via, extrinsic motivated and environment temperature T using the mathematical model of heat distribution Under cylindrical coordinates, after the load excitation unit time, through silicon via is in continuous current excitation JDCUnder heat distribution A (r) or in sinusoidal excitation JAC Under heat distribution B (r):
Wherein, g0Represent the heat production speed of continuous current excitation, rCu1It is the upper surface radius of through silicon via, k is thermal coefficient, J0 (βmIt r) is first kind zero Bessel function, βmIt is J0(βmR) characteristic value=0, J1(βm) it is first kind single order Bezier letter Number, α is heat distribution equation coefficient, α1It is skin depth, B1It is through silicon via r ∈ [- rCu1,r0] region, B2It is through silicon via r ∈ [r0, rCu1] region, θ is that the polar angle coordinate parameters r of A (r) perhaps B (r) is the polar diameter coordinate parameters of A (r) or B (r), TBIt is load Through silicon via upper surface equivalent center point (r after the sinusoidal excitation unit time0, 0, H) at temperature, r0It is one and is less than rCu1Just Number, H is the height of through silicon via, g1Represent the heat production speed of sinusoidal excitation；
(4) temperature in through silicon via at different location is obtained to A (r) or B (r) sampling site using Matlab；
If step-length is h, r=nh, n=1,2,3 ... c are taken1…c2, c1,c2It is two unequal natural numbers and c1< c2, c1Meet (rCu2/ h) -1 < c1< rCu2/ h, c2Meet (rCu1/ h) -1 < c2< rCu1/ h, θ take 0, are calculated in through silicon via not With the temperature A (h) of position, A (2h), A (3h) ... A (c1h)…A(c2H) or B (h), B (2h), B (3h) ... B (c1h)…B (c2h)；
(5) temperature difference after calculating the load excitation unit time:
Wherein, T1It is the through silicon via ensemble average temperature after the load excitation unit time, there are two types of indicate:
In continuous current excitation JDCUnder representation formula are as follows:
In sinusoidal excitation JACUnder representation formula are as follows:
Wherein, H is the height of through silicon via, H1It is that nh falls in [rCu2,rCu1] on effective through silicon via height, rCu2It is silicon Through-hole following table radius surface, θ1It is the angle of through silicon via side surface and bottom surface；
(6) the total amount of heat Q that unit of account time underexcitation generates:
It is obtained according to Joule's law
In continuous current excitation JDCUnder, Q=JDC 2R；
In sinusoidal excitation JACUnder,
Wherein, R is the resistance of through silicon via；
(7) be by R in step (5) through silicon via resistance the temperature differenceIt is public according to thermal capacitance with the gross energy Q in step (6) FormulaAn equivalent thermal capacitance value C is calculatedp0；
(8) resetting condition obtains new heat distribution function A (rj') and B'(r)j, step (3)~(7) are repeated, obtain one group Equivalent thermal capacitance value Cpj, j=1,2,3 ...:
8a) set r 'j=r+bj, j=1,2,3 ..., bjIt is that absolute value is less than rCu2Arbitrary constant, by r 'jReplace r, obtains To continuous current excitation JDCNew heat distribution function A (r ' downj):
8b) set r0j=r0+bj, α1j=α1+dj, j=1,2,3 ..., djIt is that absolute value is less than rCu2Arbitrary constant, by r0j Replace r0, α1jReplace α1, obtain sinusoidal excitation JACNew heat distribution function B'(r down)j:
8c) utilize above-mentioned A (r 'j) and B'(r)j, j takes 1,2,3 respectively ..., repeats step (3)~(7), obtain one group it is equivalent Thermal capacitance value Cp1, Cp2, Cp3,…；
(9) by the C in step (7)p0With the C in step (8)pjIt is loaded into the three dimensional integrated circuits model of Comsol building In, it is coupled using thermal field, emulation obtains the maximum stress value around through silicon via.
Compared with the prior art, the present invention has the following advantages:
First, the present invention provides a kind of through silicon via analysis method for reliability, can help designer compared with prior art Member analyzes three dimensional integrated circuits through silicon via reliability in the case where without misalignment really, saves analysis time and storage money Source realizes three dimensional integrated circuits design optimization, improves the performance of three dimensional integrated circuits.
Second, the through silicon via heat distribution model that the present invention uses, in the case of describing continuous current excitation and two kinds of sinusoidal excitation Heat distribution, compared to the heat distribution model under single excitation, the model use scope is wider more accurate, and considers excitation The position of load, become to taking effect, external magnetic field on through silicon via heat distribution influence and through silicon via asymmetry heat distribution situation, more Add and tallies with the actual situation；
Third, the present invention in the temperature differenceAcquisition, it is contemplated that temperature and positional relationship and through silicon via itself shape pair The influence of the temperature difference only considers temperature and positional relationship compared to the prior art, can obtain the temperature difference in accurate through silicon via, be suitable for Cylinder and taper through silicon via.
Detailed description of the invention
Fig. 1 is implementation flow chart of the invention.
Specific embodiment
Referring to Fig.1, of the invention to be implemented as follows:
Step 1. extracts the physical parameter of layers of material inside and outside through silicon via in circuit.
The physical parameter of each layer inside and outside through silicon via used in circuit is extracted, which includes: the upper table of through silicon via Radius surface rCu1, the following table radius surface r of through silicon viaCu2, the height H of through silicon via, the resistance R of through silicon via copper post and through silicon via The angle theta of side surface and bottom surface1, rCu1Equal to the thickness that through silicon via copper post upper surface radius adds through silicon via upper surface silica Degree, rCu2Equal to the thickness that through silicon via copper post following table radius surface adds through silicon via lower surface silica.
Step 2. inputs environment temperature T and extrinsic motivated used in through silicon via.
It inputs environment temperature T used in through silicon via and external dc motivates JDCOr sinusoidal excitation JAC。
Step 3. calculates through silicon via heat distribution.
The heat distribution of through silicon via can be calculated by the heat distribution model of through silicon via, existing through silicon via heat distribution model There are many kinds of, such as continuous current excitation heat distribution model, sinusoidal excitation heat distribution model, square wave excitation heat distribution model, direct current swashs It encourages and combines heat distribution model with sinusoidal excitation, this example is adopted according to the frequency of use for practicing various excitations in three dimensional integrated circuits Heat distribution model is combined with continuous current excitation and sinusoidal excitation, but is not limited to use this heat distribution model.
3a) heat distribution function:
The continuous current excitation and sinusoidal excitation combination heat distribution model are made of two distribution functions: first is that under cylindrical coordinates, After the load excitation unit time, continuous current excitation JDCUnder heat distribution A (r), second is that under cylindrical coordinates, after the load excitation unit time, Sinusoidal excitation JACUnder heat distribution B (r), calculation formula is as follows:
Wherein, g0Represent the heat production speed of continuous current excitation, rCu1It is the upper surface radius of through silicon via, k is thermal coefficient, J0 (βmIt r) is first kind zero Bessel function, βmIt is J0(βmR) characteristic value=0, J1(βm) it is first kind single order Bezier letter Number, α is heat distribution equation coefficient, α1It is skin depth, B1It is through silicon via r ∈ [- rCu,r0] region, B2It is through silicon via r ∈ [r0, rCu] region, θ is that the polar angle coordinate parameters r of A (r) perhaps B (r) is the polar diameter coordinate parameters of A (r) or B (r), g1It represents just The heat production speed of string excitation, TBIt is to load through silicon via upper surface equivalent center point (r after the sinusoidal excitation unit time0, 0, H) at Temperature, r0It is one and is less than rCu1Positive number, H is the height of through silicon via, g1The heat production speed of sinusoidal excitation is represented,
g0=JDC 2R
g1=JAC 2R
Wherein, the resistance of R through silicon via copper post.
3b) through silicon via heat distribution is calculated using heat distribution function:
According to the type that input extrinsic motivated type judgement in step (2) is using heat distribution function:
If the extrinsic motivated of input is continuous current excitation JDC, then by layers of material inside and outside the through silicon via of step (1) extraction Physical parameter value and the parameter value of step (2) input bring continuous current excitation J intoDCUnder heat distribution function A (r) in, silicon is calculated Through-hole heat distribution；
If the extrinsic motivated of input is sinusoidal excitation JAC, then by layers of material inside and outside the through silicon via of step (1) extraction Physical parameter value and the parameter value of step (2) input bring sinusoidal excitation J intoDCUnder heat distribution function B (r) in, silicon is calculated Through-hole heat distribution.
Step 4. uses Matlab software sampling site, obtains the temperature of through silicon via different location.
It 4a) will be in A (r) or B (r) write-in Matlab software；
Set step-length 4b) as h, θ is the polar angle coordinate parameters of A (r) or B (r), and taking θ is 0, takes the pole of A (r) or B (r) Diameter coordinate parameters r=nh, n=1,2,3 ... c1…c2, wherein c1,c2It is two unequal natural numbers, and c1< c2, (rCu2/ H) -1 < c1< rCu2/ h, (rCu1/ h) -1 < c2< rCu1/h；
Taking n is 1, brings r=h and θ=0 into A (r) A (h) that perhaps B (r) is calculated or B (h) value is that silicon is logical Temperature on hole at (h, 0, H) point；
Taking n is 2, and bringing r=2h and θ=0 into A (r), perhaps A (2h) is calculated in B (r) or B (2h) value is that silicon is logical Temperature on hole at (2h, 0, H) point；
Taking n is 3, and bringing r=3h and θ=0 into A (r), perhaps A (3h) is calculated in B (r) or B (3h) value is that silicon is logical Temperature on hole at (3h, 0, H) point；
…
Taking n is c1, by r=c1H and θ=0 bring A (r) or B (r) into, and A (c is calculated1Or B (c h)1H) value is (c in through silicon via1H, 0, H) temperature at point；
…
Taking n is c2, by r=c2H and θ=0 bring A (r) or B (r) into, and A (c is calculated2Or B (c h)2H) value is (c in through silicon via2H, 0, H) temperature at point；
Obtain above-mentioned A (h), A (2h), A (3h) ... A (c1h)…A(c2H) or B (h), B (2h), B (3h) ... B (c1h)…B (c2H) it after these values, that is, completes to the temperature computation in through silicon via at different location.
The mean temperature difference of step 5. calculating through silicon via
According to differential thermal calculation formula, the temperature difference in the unit time is calculated in through silicon via；
Temperature difference formula are as follows:
Wherein, T is environment temperature used in input through silicon via, T in step (2)1It is after load motivates the unit time Through silicon via ensemble average temperature, by the temperature A (h), A (2h), A at different location in through silicon via in step (4) (3h)…A(c1h)…A(c2H) or B (h), B (2h), B (3h) ... B (c1h)…B(c2H) it is obtained using calculated with weighted average method It arrives, there are two types of calculation formula:
In continuous current excitation JDCUnder representation formula are as follows:
In sinusoidal excitation JACUnder representation formula are as follows:
Wherein, H is the height of through silicon via, rCu1It is through silicon via upper surface radius, rCu2It is through silicon via following table radius surface, θ1It is The angle of through silicon via side surface and bottom surface, H1It is that nh falls in section [rCu2,rCu1] on effective through silicon via height；H1By as follows Formula calculates:
Step 6. calculates total amount of heat Q in the through silicon via unit time.
According to Joule's law, total amount of heat Q in the through silicon via unit time is calculated；
In continuous current excitation JDCUnder, Q=JDC 2R；
In sinusoidal excitation JACUnder,
Wherein, JDCIt is continuous current excitation used in the through silicon via of step (2) input, JACIt is the through silicon via of step (2) input Used sinusoidal excitation, R are the resistance for the through silicon via copper post that step (1) is extracted
Step 7. is according to the mean temperature difference of through silicon viaWith gross energy Q in the unit time, an equivalent thermal capacitance value is obtained.
According to thermal capacitance formulaBy the mean temperature difference of the through silicon via in step (5)With it is total in step (6) Energy Q brings thermal capacitance formula into, and an equivalent thermal capacitance value C is calculatedp0；
Step 8. converts condition, obtains new through silicon via heat distribution, repeats step (3)~(7) and obtains one group of equivalent thermal capacitance Value；
8a) set r 'j=r+bj, j=1,2,3 ..., bjIt is that absolute value is less than rCu2Arbitrary constant, by r 'jReplace r, obtains To continuous current excitation JDCNew heat distribution function A (r ' downj):
8b) set r0j=r0+bj, α1j=α1+dj, j=1,2,3 ..., djIt is that absolute value is less than rCu2Arbitrary constant, by r0j Replace r0, α1jReplace α1, obtain sinusoidal excitation JACNew heat distribution function B'(r down)j:
8c) utilize above-mentioned A (r 'j) and B'(r)j, j takes 1,2,3 respectively ..., repeats step (3)~(7), obtains one group of thermal capacitance Value Cp1, Cp2, Cp3,…。
Step 9. stress simulation
9a) according to three-dimensional integrated circuit structure and physical size, Comsol software building circuit model is used；
9b) by the C in step (7)p0With the C in step (8)pjIt is loaded into the circuit model of Comsol building；
It 9c) is coupled using thermal field, emulation obtains the maximum stress value around through silicon via.
The stress value range around through silicon via is provided according to the manufacturer of manufacture circuit, checks that emulation obtains around through silicon via Whether maximum stress value exceeds this stress value range, if emulation obtains the maximum stress value around through silicon via in this stress It is worth range, then through silicon via is reliable in circuit, whereas if emulation obtains the maximum stress value around through silicon via not at this Stress value range is then unreliable.
Foregoing description is only example of the present invention, does not constitute any limitation of the invention, it is clear that for this It, all may be in the feelings without departing substantially from the principle of the invention, structure after understanding the content of present invention and principle for the professional in field Under condition, various modifications and variations in form and details are carried out.But these modifications and variations based on inventive concept still exist Within protection scope of the present invention.
Mathematic sign according to the present invention is symbol commonly used in the art.

Claims (6)

1. a kind of through silicon via analysis method for reliability, includes the following steps:
(1) physical parameter of layers of material inside and outside through silicon via used in circuit is extracted；
(2) extrinsic motivated and environment temperature T used in through silicon via are inputted；
(3) heat distribution of through silicon via is calculated；
Cylinder seat is obtained using the mathematical model of heat distribution according to the physical parameter of through silicon via, extrinsic motivated and environment temperature T Under mark, after the load excitation unit time, through silicon via motivates J in DC currentDCUnder heat distribution A (r) or sinusoidal current swash Encourage JACUnder heat distribution B (r):
Wherein, g0Represent the heat production speed of DC current excitation, rCu1It is the upper surface radius of through silicon via, k is thermal coefficient, J0 (βmIt r) is first kind zero Bessel function, βmIt is J0(βmR) characteristic value=0, J1(βm) it is first kind single order Bezier letter Number, α is heat distribution equation coefficient, α1It is skin depth, B1It is through silicon via r ∈ [- rCu,r0] region, B2It is through silicon via r ∈ [r0, rCu] region, θ is that the polar angle coordinate parameters r of A (r) perhaps B (r) is the polar diameter coordinate parameters of A (r) or B (r), TBIt is load Through silicon via upper surface equivalent center point (r after the sinusoidal excitation unit time0, 0, H) at temperature, r0It is one and is less than rCu1Just Number, H is the height of through silicon via, g1Represent the heat production speed of sinusoidal current excitation；
(4) temperature in through silicon via at different location is obtained to A (r) or B (r) sampling site using Matlab；
If step-length is h, r=nh, n=1,2 are taken, 3, c1···c2, c1,c2It is two unequal natural numbers and c1< c2, c1Meet (rCu2/ h) -1 < c1< rCu2/ h, c2Meet (rCu1/ h) -1 < c2< rCu1/ h, θ take 0, are calculated in through silicon via The temperature A (h) of different location, A (2h), A (3h) A (c1h)···A(c2H) or B (h), B (2h), B (3h)···B(c1h)···B(c2h)；
(5) temperature difference after calculating the load excitation unit time:
Wherein, T1It is the through silicon via ensemble average temperature after the load excitation unit time, there are two types of indicate:
In continuous current excitation JDCUnder representation formula are as follows:
In sinusoidal excitation JACUnder representation formula are as follows:
Wherein, H is the height of through silicon via, H1It is that nh falls in [rCu2,rCu1] on effective through silicon via height, rCu2It is under through silicon via Surface radius, θ1It is the angle of through silicon via side surface and bottom surface；
(6) the total amount of heat Q that unit of account time underexcitation generates:
It is obtained according to Joule's law
J is motivated in DC currentDCUnder, Q=JDC 2Rt, t=1；
J is motivated in sinusoidal currentACUnder,
Wherein, R is the resistance of through silicon via；
(7) be by R in step (5) through silicon via resistance temperature difference ▽ T and step (6) in gross energy Q, according to thermal capacitance formulaAn equivalent thermal capacitance value C is calculatedp0；
(8) resetting condition obtains new heat distribution function A (r'j) and B'(r, j), repeat step (3)~(7), obtain one group it is equivalent Thermal capacitance value Cpj, j=1,2,3:
8a) set r'j=r+bj, j=1,2,3, bjIt is that absolute value is less than rCu2Arbitrary constant, by r'jReplace r, obtains Continuous current excitation JDCNew heat distribution function A (r' downj):
8b) set r0j=r0+bj, α1j=α1+dj, j=1,2,3, djIt is that absolute value is less than rCu2Arbitrary constant, by r0j Replace r0, α1jReplace α1, obtain sinusoidal excitation JACNew heat distribution function B'(r, j down):
8c) utilize above-mentioned A (r'j) and B'(r, j), j takes 1,2,3 respectively, repeats step (3)~(7), obtains one group etc. Imitate thermal capacitance value Cp1, Cp2, Cp3,···；
(9) by the C in step (7)p0With the C in step (8)pjIt is loaded into the three dimensional integrated circuits model of Comsol building, makes It is coupled with thermal field, emulation obtains the maximum stress value around through silicon via.
2. according to the method described in claim 1, wherein, in step (1) extracting each layer inside and outside through silicon via used in circuit Physical parameter includes the upper surface radius r of through silicon viaCu1, the following table radius surface r of through silicon viaCu2, the height H of through silicon via, through silicon via The angle theta of the resistance R of copper post and the side surface of through silicon via and bottom surface1, rCu1It is added equal to through silicon via copper post upper surface radius The thickness of through silicon via upper surface silica, rCu2Through silicon via lower surface titanium dioxide is added equal to through silicon via copper post following table radius surface The thickness of silicon.
3. according to the method described in claim 1, wherein, table in through silicon via after the load sinusoidal excitation unit time in step (3) Face equivalent center point (r0, 0, H) at temperature TB, it is calculated as follows:
4. according to the method described in claim 1, wherein, the heat production speed g of continuous current excitation in step (3)0, count as follows It calculates:
g0=JDC 2R。
5. according to the method described in claim 1, wherein, the heat production speed g of sinusoidal excitation in step (3)1, count as follows It calculates:
g1=JAC 2R。
6. according to the method described in claim 1, wherein, in step (5), section [rCu2,rCu1] on effective through silicon via height H1, it is calculated as follows:
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