CN106681941A - Data write-in and data-out method of memory and device - Google Patents
Data write-in and data-out method of memory and device Download PDFInfo
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- CN106681941A CN106681941A CN201510750646.6A CN201510750646A CN106681941A CN 106681941 A CN106681941 A CN 106681941A CN 201510750646 A CN201510750646 A CN 201510750646A CN 106681941 A CN106681941 A CN 106681941A
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- data
- target address
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- compression
- memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
Abstract
The invention discloses a data write-in and data-out method of a memory and a device. The data write-in and data-out method of the memory includes steps of encrypting a data D to be written when the to-be-written data D and the target address data A of the to-be-written data D are received, and acquiring the encrypted data T; respectively compressing the encrypted data T and the target address data A, acquiring the compressed encrypted data T1 and the target address data A1; acquiring verification data S according to the compressed encrypted data T1 and the target address data A1; writing the encrypted data T and the verification data S to the memory as digits. Application of the method can further improve the safety of the memory.
Description
Technical field
The present invention relates to memory data processing technology field, and in particular to a kind of data write of memory,
Reading method and device.
Background technology
At present, the storage of smart card internal bus data and transmitting procedure are easily interfered or attack.In order to
The anti-interference or anti-attack ability of smart card is improved, generally in the data to the memory write of smart card
Increase verification data, and then can be checked by the verification data corresponding data storage and transmission be
It is no to make a mistake.
However, in above-mentioned anti-interference attack method, being only capable of checking write to storage by the verification data
Whether the data in device itself make a mistake, and cannot check whether read-out data are user input
The data of destination address, cause the security of the memory relatively low.
The content of the invention
Present invention solves the technical problem that being the security for how further improving memory.
To solve above-mentioned technical problem, the embodiment of the present invention provides a kind of method for writing data of memory,
Methods described includes：
When the target address data A of data D to be written and data D to be written is received,
Data D to be written are encrypted, encryption data T is obtained；
Respectively process is compressed to encryption data T and the target address data A, is compressed
Encryption data T1 afterwards and target address data A1, and according to encryption data T1 after compression and target ground
Location data A1 obtain verification data S；
Encryption data T and verification data S are write to the memory as code word.
Alternatively, it is described respectively place to be compressed to encryption data T and the target address data A
Reason, encryption data T1 and target address data A1 after being compressed, and according to the T1 and mesh after compression
Mark address A1 data obtain verification data S, including：
First compression function is called to be compressed process to encryption data T according to default bit length,
Encryption data T1 after being compressed；
The second compression function is called to be compressed place to the target address data A according to the default bit length
Reason, the target address data A1 after being compressed；
First computing is performed to encryption data T1 after the compression and target address data A1, school is obtained
Test data S.
Alternatively, the default bit length and the checking feature of the memory, data D to be written
Bit length, the bit length of the target address data A and first compression function and the second compression function phase
Close.
Alternatively, first computing is XOR.
The embodiment of the present invention additionally provides a kind of data read method of memory, and methods described includes：
Reception is continued the target address data A of D of fetching data；
The code word of corresponding position in the memory is read according to the target address data A；
The code word is split as into encryption data T and verification data S according to default bit length；
Respectively process is compressed to encryption data T and the target address data A, is compressed
Encryption data T1 afterwards and target address data A1；
According to encryption data T1 after the compression, target address data A1 and verification data S, to described
Encryption data T is verified, and determines the output of the memory according to check results.
Alternatively, it is described respectively place to be compressed to encryption data T and the target address data A
Reason, encryption data T1 and target address data A1 after being compressed, including：
Call the first compression function that process is compressed to encryption data T according to default bit length, obtain
Encryption data T1 after compression；
The second compression function is called to be compressed place to the target address data A according to the default bit length
Reason, the target address data A1 after being compressed.
Alternatively, encryption data T1 according to after the compression, target address data A1 and verification
Data S, verify to encryption data T, and determine the defeated of the memory according to check results
Go out, including：
First computing is performed to encryption data T1 after the compression and verification data S；
Judge whether the result after first computing is equal with the target address data A1 after the compression；
When the result after first computing is equal with the target address data A1 after the compression, judge
Encryption data T is correct data, is exported after being decrypted to encryption data T.
Alternatively, encryption data T1 according to after the compression, target address data A1 and verification
Data T after the encryption are verified by data S, and determine the memory according to check results
Output, also include：
When the target address data A1 after the result after first computing with the compression is unequal, sentence
Fixed encryption data T is wrong data, exports corresponding cue, to call corresponding protection plan
Slightly.
Alternatively, first computing is XOR.
Alternatively, the default bit length fetches data D's with the checking feature of the memory, described continuing
Bit length, the bit length of the target address data A and first compression function and the second compression function are related.
The embodiment of the present invention additionally provides a kind of data transfer apparatus of memory, and described device includes：
Ciphering unit, is suitable to when the target that receive data D to be written and data D to be written
During address date A, data D to be written are encrypted, obtain encryption data T；
First processing units, are suitable to respectively carry out encryption data T and the target address data A
Compression process, encryption data T1 and target address data A1 after being compressed, and according to compression after
Encryption data T1 and target address data A1 obtain verification data S；
Writing unit, is suitable to encryption data T and verification data S be write to described as code word and deposits
Reservoir.
Alternatively, the first processing units include：
First processes subelement, is suitable to call first compression function according to default bit length to the encryption
Data T are compressed process, encryption data T1 after being compressed；
Second processing subelement, is suitable to call the second compression function according to the default bit length to the target
Address date A is compressed process, the target address data A1 after being compressed；
First computing subelement, is suitable to encryption data T1 after the compression and target address data A1
The first computing is performed, verification data S is obtained.
Alternatively, the default bit length and the checking feature of the memory, data D to be written
Bit length, the bit length of the target address data A and first compression function and the second compression function phase
Close.
Alternatively, the first computing subelement is suitable to encryption data T1 after the compression and target ground
Location data A1 perform XOR, obtain verification data S.
The embodiment of the present invention additionally provides a kind of data readout setup of memory, and described device includes：
Receiving unit, is suitable to receive the target address data A of D of fetching data that continues；
Reading unit, is suitable to read corresponding position in the memory according to the target address data A
Code word；
Split cells, is suitable to that the code word is split as into encryption data T and verification data according to default bit length
S；
Second processing unit, is suitable to respectively carry out encryption data T and the target address data A
Compression is processed, encryption data T1 and target address data A1 after being compressed；
3rd processing unit, is suitable to according to encryption data T1 after the compression, target address data A1
And verification data S, data T after the encryption are verified, and according to check results determine
The output of memory.
Alternatively, the second processing unit includes：
3rd processes subelement, is suitable to call the first compression function according to default bit length to encryption data T
Process is compressed, encryption data T1 after being compressed；
Fourth process subelement, is suitable to call the second compression function according to the default bit length to the target
Address date A is compressed process, the target address data A1 after being compressed.
Alternatively, the 3rd processing unit includes：
Second computing subelement, is suitable to perform encryption data T1 after the compression and verification data S the
One computing；
Judgment sub-unit, the destination address for being suitable to judge after the result after first computing and the compression
Whether data A1 are equal；
Decryption subelement, the destination address number being suitable to after result after first computing and the compression
According to A1 it is equal when, judge that encryption data T, by verification, is decrypted to encryption data T
After export.
Alternatively, the 3rd processing unit also includes：
Prompting subelement, the destination address number being suitable to after result after first computing and the compression
According to A1 it is unequal when, judge that encryption data T is not validated, export corresponding cue, with
Call corresponding prevention policies.
Alternatively, the second computing subelement is suitable to encryption data T1 and check number after the compression
XOR is performed according to S.
Alternatively, the default bit length fetches data D's with the checking feature of the memory, described continuing
Bit length, the bit length of the target address data A and first compression function and the second compression function are related.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that：
When data are write in memory, by entering to encryption data T and the target address data A
Row compression is processed, and then can obtain verification data S according to the data after compression.Due to the verification data
Middle S is closed with encryption data T-phase, also related to target address data A, therefore can be from memory
When reading data, either encryption data T is interfered in itself or attacks, or the encryption number
According to the corresponding encryption datas of the non-target address data A of T, can pass through the checking of verification data S
And data exception is found, such that it is able to the security for further improving memory.
Description of the drawings
Fig. 1 is a kind of method for writing data flow chart of memory in the embodiment of the present invention；
Fig. 2 is a kind of data transfer apparatus structural representation of memory in the embodiment of the present invention；
Fig. 3 is a kind of data read method flow chart of memory in the embodiment of the present invention；
Fig. 4 is a kind of data readout setup structural representation of memory in the embodiment of the present invention.
Specific embodiment
At present, when data are write in memory, generally according only to the data genaration check number for being write
According to, and then when data are read from memory, verify that the memory is according to the verification data
It is no to be interfered or attack.However, in the above-mentioned methods, by the verification data, it is only capable of in write
When data in memory make a mistake in itself, detect that the memory is interfered or attacks, and nothing
During the data of the destination address that method is input into read-out data non-user, detect that the memory is subject to
Interference is attacked, and causes the security of the memory relatively low.
For the problems referred to above, a kind of wiring method of memory is embodiments provided, using described
Method, when data are write in memory, by encryption data T and the target address data A
Process is compressed, and then verification data S can be obtained according to the data after compression.Due to the check number
Not only close with encryption data T-phase according to middle S, it is also related to target address data A, therefore can be from depositing
When reading data in reservoir, either encryption data T is interfered in itself or attacks, or described
The corresponding encryption datas of the non-target address data A of encryption data T, can pass through verification data S
Checking and find data exception, further improve the security of memory.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent from, with reference to
Accompanying drawing is described in detail to the specific embodiment of the present invention.
As shown in figure 1, embodiments providing a kind of method for writing data of memory, the side
Method may include steps of：
Step 11, when the destination address number for receiving data D to be written and data D to be written
During according to A, data D to be written are encrypted, obtain encryption data T.
In being embodied as, when writing data D in memory, can be using symmetric encipherment algorithm to institute
State data D to be written to be encrypted, it would however also be possible to employ rivest, shamir, adelman is to described to be written
Data D be encrypted.Wherein, the symmetric encipherment algorithm can include DES algorithms, RC2
Algorithm, RC4 algorithms, RC5 algorithms and Blowfish algorithms etc..The rivest, shamir, adelman can be wrapped
Include RSA Algorithm, ECC algorithm and Knapsack algorithms etc..It is concrete no matter which kind of AES pair to be adopted
Data D to be written are encrypted, and are not construed as limiting the invention, and at this
Within bright protection domain.
Data D to be written are encrypted using AES, after obtaining encryption data T,
Then execution step 12.
Step 12, is compressed process to encryption data T and the target address data A respectively,
Encryption data T1 and target address data A1 after being compressed, and according to encryption data T1 after compression
And target address data A1 obtains verification data S.
In being embodied as, after obtaining encryption data T, the first compression function can be called according to default position
Length is compressed process to encryption data T, encryption data T1 after being compressed.Receive described
During the target address data A of data D to be written, call the second compression function according to default bit length to institute
State target address data A and be compressed process, the target address data A1 after being compressed.Then, root
The first computing is performed according to encryption data T1 after the compression and target address data A1, check number is obtained
According to S.
Wherein, first compression function and the second compression function can be with identical, it is also possible to different, for example,
First compression function and the second compression function can be CRC (CRC) algorithm.When
So, first compression function and the second compression function can also be other algorithms, specifically not be restricted,
But no matter the first compression function and the concrete why algorithm of the second compression function, in protection scope of the present invention
Within.
In being embodied as, first computing can be XOR, or other computings.
Specifically, with the bit length of encryption data T as m bits, the position of the target address data A
A length of n-bit, the default bit length is r bits, and first computing is as a example by XOR, to call institute
The first compression function is stated by encryption data T1 of the encryption data T boil down to r bits of m bits, institute is called
The second compression function is stated by the target address data A1 of n-bit target address data A boil down to r bits.
XOR is performed to encryption data T1 after the compression and target address data A1, check number is obtained
According to S.
It should be noted that the default bit length is identical with the bit length of verification data S, specifically can basis
The checking feature of the memory, the data D bit length to be written, the target address data A positions
Long and selected the first compression function and the second compression function is configured.It is understood that described
Default bit length is longer, and the error detecing capability of the memory is also stronger, and corresponding cost is also bigger.Example
Such as, when first compression function and the second compression function are CRC algorithm, if m≤11, r=4,
For when mistake occurs in any 2 bit in encryption data T, the error detecing capability of the memory is
100%.
Step 13, encryption data T and verification data S are write to the memory as code word.
In being embodied as, after obtaining verification data S, by encryption data T and the verification data
S carries out being spliced to form code word, and the code word is stored in into the memory.
In order that those skilled in the art more fully understand and realize the present invention, below to above-mentioned memory
The corresponding device of method for writing data is described in detail.
As shown in Fig. 2 embodiments providing a kind of writing station of memory.Said write is filled
Putting to include：Ciphering unit 21, first processing units 22 and writing unit 23.Wherein：
The ciphering unit 21 is suitable to work as and receives data D and data D to be written to be written
Target address data A when, data D to be written are encrypted, obtain encryption data
T.The first processing units 22 are suitable to respectively to encryption data T and the target address data A
Process is compressed, encryption data T1 and target address data A1 after being compressed, and according to compression
Encryption data T1 and target address data A1 afterwards obtains verification data S.Said write unit 23 is suitable to
Encryption data T and verification data S are write to the memory as code word.
In being embodied as, the first processing units 22 include：First process subelement 220, second
Process the computing subelement 222 of subelement 221 and first.Wherein, the first process subelement 220 is fitted
In calling first compression function to be compressed process to encryption data T according to default bit length, obtain
Encryption data T1 after must compressing.The second processing subelement 221 be suitable to call the second compression function by
Process is compressed to the target address data according to the default bit length, the destination address after being compressed
Data A1.The first computing subelement 222 is suitable to encryption data T1 and target after the compression
Address date A1 performs the first computing, obtains verification data S.
It is the default bit length and the checking feature of the memory, described to be written in being embodied as
The bit length of data D, the bit length of the target address data A and first compression function and the second compression
Functional dependence.
In being embodied as, the first computing subelement 222 is suitable to the encryption data after the compression
T1 and target address data A1 performs XOR, obtains verification data S.
As shown in figure 3, the embodiment of the present invention additionally provides a kind of data read method of memory, it is described
Method comprises the steps：
Step 31, reception is continued the target address data A of D of fetching data.
Step 32, according to the target address data A code word of corresponding position in the memory is read.
Step 33, encryption data T and verification data S are split as according to default bit length by the code word.
In specific implementation step 31-33, according to the target address data A, phase is searched in memory
The code word answered.After reading the code word, because the default bit length is the bit length of the verification data, because
The code word for being read can be split as encryption data T and verification data S by this according to the default bit length.
For example, when the default bit length is r bits, and the bit length of the code word is m+r bits, read described
After code word, using the rear r bits of the code word as verification data S, remaining m bits are the number after encryption
According to T.
Wherein, the default bit length and the checking feature of the memory, the position of D of fetching data of continuing
The bit length and first compression function of long, described target address data A and the second compression function are related.
Step 34, is compressed process to encryption data T and the target address data A respectively,
Encryption data T1 and target address data A1 after being compressed.
In being embodied as, after obtaining encryption data T, the first compression function can be called according to default position
Length is compressed process to encryption data T, encryption data T1 after being compressed.Receive described
During target address data A, call the second compression function according to default bit length to the target address data A
Process is compressed, the target address data A1 after being compressed.
Wherein, first compression function and the second compression function can be with identical, it is also possible to different, for example,
First compression function and the second compression function can be CRC algorithm, or other algorithms.Institute
It can be XOR to state the first computing, or other computings.
Specifically, with the bit length of encryption data T as m bits, the position of the target address data A
A length of n-bit, the default bit length is r bits, and first computing is as a example by XOR, to call institute
The first compression function is stated by encryption data T1 of the encryption data T boil down to r bits of m bits, institute is called
The second compression function is stated by the target address data A1 of n-bit target address data A boil down to r bits.
Step 35, according to encryption data T1 after the compression, target address data A1 and verification data
S, verifies to encryption data T, and determines the output of the memory according to check results.
In being embodied as, the first can be performed to encryption data T1 after the compression and verification data S
One computing, then by judging the result of the first computing and the compression after target address data A1 whether phases
Deng to verify to encryption data T.Wherein, first computing can be XOR.
When the result of the first computing is equal with the target address data A1 after the compression, the encryption number
It is correct data according to T.So-called encryption data T be correct data, i.e., described encryption data T itself
Be not interfered or attack, and the encryption data be the memory in the target address data A
Corresponding data.When encryption data T is correct data, encryption data T is solved
Close, after being decrypted data D, export data D after the decryption.
When the target address data A1 after result and the compression of the first computing is unequal, the encryption
Data T are the data of mistake.So-called encryption data T be mistake data, i.e., described encryption data T sheet
Body is interfered or attacks, or state in the non-memory of encryption data with the target address data A
Corresponding data, or encryption data T be interfered in itself or attack and in the non-memory with
The corresponding data of the target address data A.When the data that encryption data T is mistake, can be with
Corresponding cue is exported, such as produces corresponding alarm signal, to notify that memory is received described in user
To interference or attack, facilitate user to call corresponding prevention policies, such as, export default data.
As shown in the above, using the method for writing data of memory described in the embodiment of the present invention,
When writing data in memory, by being compressed to encryption data T and the target address data A
Process, and then verification data S can be obtained according to the data after compression.Due to S in the verification data
Not only close with encryption data T-phase, it is also related to target address data A, therefore can be from memory
When reading data, either encryption data T is interfered in itself or attacks, or the encryption number
According to the corresponding encryption datas of the non-target address data A of T, can pass through the checking of verification data S
And data exception is found, such that it is able to the security for further improving memory.
In order that those skilled in the art more fully understand and realize the present invention, below to above-mentioned memory
The corresponding device of data read method is described in detail.
As shown in figure 4, embodiments providing a kind of data readout setup of memory.The dress
Putting to include：Receiving unit 41, reading unit 42, split cells 43, second processing unit 44 with
And the 3rd processing unit 45.Wherein：
The receiving unit 41 is suitable to receive the target address data A of D of fetching data that continues.It is described to read list
Unit 42 is suitable to read the code word of corresponding position in the memory according to the target address data A.Institute
State split cells 43 to be suitable to that the code word is split as into encryption data T and verification data S according to default bit length.
The second processing unit 44 is suitable to respectively carry out encryption data T and the target address data A
Compression is processed, encryption data T1 and target address data A1 after being compressed.Described 3rd processes single
Unit 45 is suitable to according to encryption data T1 after the compression, target address data A1 and verification data S,
Data T after the encryption are verified, and determines the output of the memory according to check results.
Further, the second processing unit 44 can include：3rd processes subelement 441 and the 4th
Process subelement 442.Wherein, the described 3rd process subelement 441, be suitable to call the first compression function by
Process is compressed to encryption data T according to default bit length, encryption data T1 after being compressed.The
Four process subelement 442, are suitable to call the second compression function according to the default bit length to the destination address
Data are compressed process, the target address data A1 after being compressed.
In being embodied as, the 3rd processing unit 45 can include：Second computing subelement, judgement
Subelement and decryption subelement (not shown).The second computing subelement, is suitable to after the compression
Encryption data T1 performs the first computing with verification data S.The judgment sub-unit, is suitable to judge described
Whether the result after one computing is equal with the target address data A1 after the compression.Decryption is single
Unit, is suitable to when the result after first computing is equal with the target address data A1 after the compression,
Judge that encryption data T, by verification, is exported after being decrypted to encryption data T.
Wherein, first computing can be XOR.The school of the default bit length and the memory
Test ability, bit length, the bit length of the target address data A and described first of D of fetching data that continue
Compression function and the second compression function are related.
Further, the 3rd processing unit 45 can also include：Prompting subelement (not shown).
The prompting subelement is suitable to the target address data after result after first computing and the compression
When A1 is unequal, judge that encryption data T is not validated, export corresponding cue, to adjust
Use corresponding prevention policies.
As shown in the above, when data are write in memory, by encryption data T and described
Target address data A is compressed process, and then can obtain verification data S according to the data after compression.
It is also related to target address data A because S is not only closed with encryption data T-phase in the verification data,
Therefore can when data are read from memory, either encryption data T be interfered in itself or
Attack, or the corresponding encryption datas of the non-target address data A of encryption data T, can be with
Verified by verification data S.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment
Suddenly can be by program to instruct the hardware of correlation to complete, the program can be stored in a computer can
In reading storage medium, storage medium can include：ROM, RAM, EEPROM, FLASH, disk
Or CD etc..
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of method for writing data of memory, it is characterised in that include：
When the target address data A of data D to be written and data D to be written is received,
Data D to be written are encrypted, encryption data T is obtained；
Respectively process is compressed to encryption data T and the target address data A, is compressed
Encryption data T1 afterwards and target address data A1, and according to encryption data T1 after compression and target ground
Location data A1 obtain verification data S；
Encryption data T and verification data S are write to the memory as code word.
2. the method for writing data of memory as claimed in claim 1, it is characterised in that described respectively to institute
State encryption data T and the target address data A is compressed process, the encryption data after being compressed
T1 and target address data A1, and check number is obtained according to the T1 after compression and destination address A1 data
According to S, including：
First compression function is called to be compressed process to encryption data T according to default bit length,
Encryption data T1 after being compressed；
The second compression function is called to be compressed place to the target address data A according to the default bit length
Reason, the target address data A1 after being compressed；
First computing is performed to encryption data T1 after the compression and target address data A1, school is obtained
Test data S.
3. the method for writing data of memory as claimed in claim 2, it is characterised in that the default bit length
Checking feature, the bit length of data D to be written with the memory, the target address data
The bit length of A and first compression function and the second compression function correlation.
4. the method for writing data of memory as claimed in claim 2, it is characterised in that first computing
For XOR.
5. a kind of data read method of memory, it is characterised in that include：
Reception is continued the target address data A of D of fetching data；
The code word of corresponding position in the memory is read according to the target address data A；
The code word is split as into encryption data T and verification data S according to default bit length；
Respectively process is compressed to encryption data T and the target address data A, is compressed
Encryption data T1 afterwards and target address data A1；
According to encryption data T1 after the compression, target address data A1 and verification data S, to described
Encryption data T is verified, and determines the output of the memory according to check results.
6. the data read method of memory as claimed in claim 5, it is characterised in that described respectively to institute
State encryption data T and the target address data A is compressed process, the encryption data after being compressed
T1 and target address data A1, including：
Call the first compression function that process is compressed to encryption data T according to default bit length, obtain
Encryption data T1 after compression；
The second compression function is called to be compressed place to the target address data A according to the default bit length
Reason, the target address data A1 after being compressed.
7. the data read method of memory as claimed in claim 6, it is characterised in that described in the basis
Encryption data T1, target address data A1 and verification data S after compression, to encryption data T
Verified, and determined the output of the memory according to check results, including：
First computing is performed to encryption data T1 after the compression and verification data S；
Judge whether the result after first computing is equal with the target address data A1 after the compression；
When the result after first computing is equal with the target address data A1 after the compression, judge
Encryption data T is correct data, is exported after being decrypted to encryption data T.
8. the data read method of memory as claimed in claim 7, it is characterised in that described in the basis
Encryption data T1, target address data A1 and verification data S after compression, to the data after the encryption
T is verified, and determines the output of the memory according to check results, is also included：
When the target address data A1 after the result after first computing with the compression is unequal, sentence
Fixed encryption data T is wrong data, exports corresponding cue, to call corresponding protection plan
Slightly.
9. the data read method of memory as claimed in claim 7, it is characterised in that first computing
For XOR.
10. the data read method of memory as claimed in claim 6, it is characterised in that the default position
It is long with the checking feature of the memory, bit length, the target address data of D of fetching data that continue
The bit length of A and first compression function and the second compression function correlation.
11. a kind of data transfer apparatus of memory, it is characterised in that include：
Ciphering unit, is suitable to when the target that receive data D to be written and data D to be written
During address date A, data D to be written are encrypted, obtain encryption data T；
First processing units, are suitable to respectively carry out encryption data T and the target address data A
Compression process, encryption data T1 and target address data A1 after being compressed, and according to compression after
Encryption data T1 and target address data A1 obtain verification data S；
Writing unit, is suitable to encryption data T and verification data S be write to described as code word and deposits
Reservoir.
The data transfer apparatus of 12. memories as claimed in claim 11, it is characterised in that at described first
Reason unit includes：
First processes subelement, is suitable to call first compression function according to default bit length to the encryption
Data T are compressed process, encryption data T1 after being compressed；
Second processing subelement, is suitable to call the second compression function according to the default bit length to the target
Address date A is compressed process, the target address data A1 after being compressed；
First computing subelement, is suitable to encryption data T1 after the compression and target address data A1
The first computing is performed, verification data S is obtained.
The data transfer apparatus of 13. memories as claimed in claim 12, it is characterised in that the default position
Length and the checking feature of the memory, the bit length of data D to be written, the destination address number
Bit length and first compression function and the second compression function according to A is related.
The data transfer apparatus of 14. memories as claimed in claim 12, it is characterised in that first fortune
Operator unit is suitable to perform XOR to encryption data T1 after the compression and target address data A1,
Obtain verification data S.
15. a kind of data readout setups of memory, it is characterised in that include：
Receiving unit, is suitable to receive the target address data A of D of fetching data that continues；
Reading unit, is suitable to read corresponding position in the memory according to the target address data A
Code word；
Split cells, is suitable to that the code word is split as into encryption data T and verification data according to default bit length
S；
Second processing unit, is suitable to respectively carry out encryption data T and the target address data A
Compression is processed, encryption data T1 and target address data A1 after being compressed；
3rd processing unit, is suitable to according to encryption data T1 after the compression, target address data A1
And verification data S, data T after the encryption are verified, and according to check results determine
The output of memory.
The data readout setup of 16. memories as claimed in claim 15, it is characterised in that at described second
Reason unit includes：
3rd processes subelement, is suitable to call the first compression function according to default bit length to encryption data T
Process is compressed, encryption data T1 after being compressed；
Fourth process subelement, is suitable to call the second compression function according to the default bit length to the target
Address date A is compressed process, the target address data A1 after being compressed.
The data readout setup of 17. memories as claimed in claim 16, it is characterised in that at the described 3rd
Reason unit includes：
Second computing subelement, is suitable to perform encryption data T1 after the compression and verification data S the
One computing；
Judgment sub-unit, the destination address for being suitable to judge after the result after first computing and the compression
Whether data A1 are equal；
Decryption subelement, the destination address number being suitable to after result after first computing and the compression
According to A1 it is equal when, judge that encryption data T, by verification, is decrypted to encryption data T
After export.
The data readout setup of 18. memories as claimed in claim 17, it is characterised in that at the described 3rd
Reason unit also includes：
Prompting subelement, the destination address number being suitable to after result after first computing and the compression
According to A1 it is unequal when, judge that encryption data T is not validated, export corresponding cue, with
Call corresponding prevention policies.
The data readout setup of 19. memories as claimed in claim 17, it is characterised in that second fortune
Operator unit is suitable to perform XOR to encryption data T1 after the compression and verification data S.
The data readout setup of 20. memories as claimed in claim 16, it is characterised in that the default position
It is long with the checking feature of the memory, bit length, the target address data of D of fetching data that continue
The bit length of A and first compression function and the second compression function correlation.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510750646.6A CN106681941A (en) | 2015-11-07 | 2015-11-07 | Data write-in and data-out method of memory and device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510750646.6A CN106681941A (en) | 2015-11-07 | 2015-11-07 | Data write-in and data-out method of memory and device |
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| CN201510750646.6A Pending CN106681941A (en) | 2015-11-07 | 2015-11-07 | Data write-in and data-out method of memory and device |
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