CN106653718A - Silicon wafer back metallization structure for eutectic bonding and processing technology - Google Patents
Silicon wafer back metallization structure for eutectic bonding and processing technology Download PDFInfo
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- CN106653718A CN106653718A CN201510740926.9A CN201510740926A CN106653718A CN 106653718 A CN106653718 A CN 106653718A CN 201510740926 A CN201510740926 A CN 201510740926A CN 106653718 A CN106653718 A CN 106653718A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
- H01L2224/2745—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/28105—Layer connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. layer connectors on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/2954—Coating
- H01L2224/29575—Plural coating layers
- H01L2224/2958—Plural coating layers being stacked
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
The invention belongs to the technical field of semiconductor, and specifically relates to a silicon wafer back metallization structure for eutectic bonding and a processing technology. The surface of a back substrate silicon wafer is plated with a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer in sequence from the near to the distant relative to the silicon wafer, wherein the first metal layer is made of titanium, vanadium or chromium, the second metal layer is made of nickel, the third metal layer is made of silver, the fourth metal layer is made of tin-copper or tin-antimony alloy, and the fifth metal layer is made of silver. According the silicon wafer back metallization structure for eutectic bonding and the processing technology of the invention, the cost is reduced under the condition of no toxicity, phenomena such as bad eutectic performance and pseudo soldering are avoided during packaging, and over temperature is avoided during wave soldering. The silicon wafer back metallization structure for eutectic bonding and processing technology have higher reliability, large coverage and a wide range of applications.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of silicon chip back side metallization for eutectic weldering
Structure and processing technology.
Background technology
Eutectic weldering is also known as low-melting alloy welding.The fundamental characteristics of eutectic alloy is：Two kinds of different metals can
Alloy is formed under far below respective melting temperature in constant weight ratio.It is the most frequently used in microelectronic component
Eutectic weldering be that silicon is soldered to gold-plated base or lead frame up, i.e., " gold-silicon eutectic weldering ".At present
Golden arsenic eutectic technology, it is relatively costly and poisonous.Existing three layers of low temperature tin eutectic, easily goes out in keeping
Existing tin layers oxidation, and eutectic is bad during later stage encapsulation load, rosin joint, residual less, wave-soldering when excess temperature make core
The problems such as piece comes off.
The content of the invention
It is an object of the invention to provide a kind of silicon chip back side metallization structure and processing technology for eutectic weldering,
While not having toxicity, reduces cost is not in the phenomenons such as the bad, rosin joint of eutectic in encapsulation, together
When in wave-soldering be also not in excess temperature problem, increase reliability, coverage rate is big, widely applicable.
For achieving the above object, the technical solution adopted in the present invention is：The structure overleaf silicon substrate
Surface by away from silicon chip from the close-by examples to those far off order be coated with successively the first metal layer, second metal layer, the 3rd metal level,
4th metal level and fifth metal layer, the material of the first metal layer is any one in titanium, vanadium or chromium, second
The material of metal level is nickel, and the material of the 3rd metal level is silver, and the material of the 4th metal level is tin copper or tin antimony
Alloy, the material of fifth metal layer is silver.
Preferably, the thickness of the first metal layer is
Preferably, the thickness of the second metal layer is
Preferably, the thickness of the 3rd metal level is
Preferably, the thickness of the 4th metal level is
Preferably, the thickness of the fifth metal layer is
Preferably, when the material of the 4th metal level is gun-metal, the weight of tin in the gun-metal
Percentage is 55～65%, and the percentage by weight of copper is 35～45%；The material of the 4th metal level is tin pewter
When, the percentage by weight of tin is 90～94% in the tin pewter, and the percentage by weight of antimony is 6～10%.
A kind of processing technology of the silicon chip back side metallization structure for eutectic weldering, the first metal layer, the second gold medal
Category layer, the 3rd metal level, the 4th metal level and fifth metal layer carry out plated film by way of evaporation, its
The speed of the evaporation of middle the first metal layer isThe speed of the evaporation of second metal layer is
The speed of the evaporation of the 3rd metal level isThe speed of the evaporation of the 4th metal level is
The speed of the evaporation of fifth metal layer is
After above-mentioned technical proposal, the present invention has the positive effect that：
Silicon chip back side metallization structure and processing technology for eutectic weldering in the present invention, using five layers of plated film
Mode, compared to existing golden arsenic eutectic technology, reduce its cost and reduce toxic action, compare
In existing three layers of low temperature tin eutectic technology, easily there is tin layers problem of oxidation when efficiently solving keeping, this
The eutectic structure of invention is not in the phenomenons such as the bad, rosin joint of eutectic in encapsulation, while the 3rd of the present invention the
The design of metal level and the 4th metal level efficiently solves the wave-soldering phenomenon produced during low temperature eutectic, it is ensured that
Be not in excess temperature problem in wave-soldering, increased the reliability of eutectic structure, coverage rate is big, applicable surface
Extensively.
Description of the drawings
Fig. 1 is the schematic diagram of the silicon chip back side metallization structure of the eutectic weldering of the present invention.
Wherein：1st, silicon chip, 2, the first metal layer, 3, second metal layer, the 4, the 3rd metal level, 5,
Four metal levels, 6, fifth metal layer.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and detailed description.
1. metallization structure
As shown in figure 1, for the present invention eutectic weldering silicon chip back side metallization structure, including material be titanium,
The first metal layer 2, material of any one in vanadium or chromium is silver-colored the 3rd for the second metal layer 3, material of nickel
Metal level 4, material is silver-colored fifth metal layer for the 4th metal level 5 and material of gun-metal or tin pewter
6.The first metal layer 2, second metal layer 3, the 3rd metal level 4, the 4th metal level 5 and fifth metal layer 6
Overleaf the surface of silicon substrate 1 is by away from silicon chip 1, from the close-by examples to those far off order is deposited with successively.
2. processing technology step is：
(1) gun-metal or tin pewter are prepared, the percentage by weight of tin is 55～65% in gun-metal,
The percentage by weight of copper is 35～45%；The percentage by weight of tin is 90～94% in tin pewter, the weight of antimony
Percentage is 6～10%；
(2) pad pasting process is carried out to the front of silicon chip 1, then edge is carried out to repair film inspection；
(3) reduction processing is carried out to the backing substrate of silicon chip 1, after process, pad pasting is removed to front；
(4) silicon chip 1 is cleaned；
(5) silicon chip 1 is put in vapourizing furnace after cleaning；
(6) process is evaporated to the back side：The thickness of the first metal layer 2 isThe speed of evaporation
Rate isThe thickness of second metal layer 3 isThe speed of evaporation is
The thickness of the 3rd metal level 4 isThe speed of evaporation is4th metal level 5
Thickness beThe speed of evaporation isThe thickness of fifth metal layer 6 isThe speed of evaporation is
(7) come out of the stove detection.
Embodiment 1
1. metallization structure
The present embodiment eutectic weldering silicon chip back side metallization structure, including material for titanium the first metal layer 2,
Material is the 4th gold medal that the 3rd metal level 4, material that the second metal layer 3, material of nickel is silver is gun-metal
Category layer 5 and material are the fifth metal layer 6 of silver.
2. processing technology step is：
(1) gun-metal is prepared, the percentage by weight of tin is 60% in gun-metal, the percentage by weight of copper
For 40%；
(2) pad pasting process is carried out to the front of silicon chip 1, then edge is carried out to repair film inspection；
(3) reduction processing is carried out to the backing substrate of silicon chip 1, after process, pad pasting is removed to front；
(4) silicon chip 1 is cleaned；
(5) silicon chip 1 is put in vapourizing furnace after cleaning；
(6) process is evaporated to the back side：The thickness of the first metal layer 2 isThe speed of evaporation isThe thickness of second metal layer 3 isThe speed of evaporation is3rd metal level 4
Thickness isThe speed of evaporation isThe thickness of the 4th metal level 5 isEvaporation
Speed isThe thickness of fifth metal layer 6 isThe speed of evaporation is
(7) come out of the stove detection.
Embodiment 2
1. metallization structure
The present embodiment eutectic weldering silicon chip back side metallization structure, including material for vanadium the first metal layer 2,
Material is that gun-metal or tin antimony are closed for the 3rd metal level 4, material that the second metal layer 3, material of nickel is silver
4th metal level 5 and material of gold is the fifth metal layer 6 of silver.
2. processing technology step is：
(1) tin pewter is prepared, the percentage by weight of tin is 92% in tin pewter, the percentage by weight of antimony
For 8%；
(2) pad pasting process is carried out to the front of silicon chip 1, then edge is carried out to repair film inspection；
(3) reduction processing is carried out to the backing substrate of silicon chip 1, after process, pad pasting is removed to front；
(4) silicon chip 1 is cleaned；
(5) silicon chip 1 is put in vapourizing furnace after cleaning；
(6) process is evaporated to the back side：The thickness of the first metal layer 2 isThe speed of evaporation isThe thickness of second metal layer 3 isThe speed of evaporation isThe thickness of the 3rd metal level 4
Spend and beThe speed of evaporation isThe thickness of the 4th metal level 5 isThe speed of evaporation
Rate isThe thickness of fifth metal layer 6 isThe speed of evaporation is
(7) come out of the stove detection.
Embodiment 3
1. metallization structure
The present embodiment eutectic weldering silicon chip back side metallization structure, including material for chromium the first metal layer 2,
Material is the 4th gold medal that the 3rd metal level 4, material that the second metal layer 3, material of nickel is silver is gun-metal
Category layer 5 and material are the fifth metal layer 6 of silver.
2. processing technology step is：
(1) gun-metal is prepared, the percentage by weight of tin is 65% in gun-metal, the percentage by weight of copper
For 35%；
(2) pad pasting process is carried out to the front of silicon chip 1, then edge is carried out to repair film inspection；
(3) reduction processing is carried out to the backing substrate of silicon chip 1, after process, pad pasting is removed to front；
(4) silicon chip 1 is cleaned；
(5) silicon chip 1 is put in vapourizing furnace after cleaning；
(6) process is evaporated to the back side：The thickness of the first metal layer 2 isThe speed of evaporation isThe thickness of second metal layer 3 isThe speed of evaporation is3rd metal level 4
Thickness isThe speed of evaporation isThe thickness of the 4th metal level 5 isEvaporation
Speed isThe thickness of fifth metal layer 6 isThe speed of evaporation is
(7) come out of the stove detection.
Embodiment 4
1. metallization structure
The present embodiment eutectic weldering silicon chip back side metallization structure, including material for chromium the first metal layer 2,
Material is the 4th gold medal that the 3rd metal level 4, material that the second metal layer 3, material of nickel is silver is gun-metal
Category layer 5 and material are the fifth metal layer 6 of silver.
2. processing technology step is：
(1) tin pewter is prepared, the percentage by weight of tin is 90% in tin pewter, the percentage by weight of antimony
For 10%；
(2) pad pasting process is carried out to the front of silicon chip 1, then edge is carried out to repair film inspection；
(3) reduction processing is carried out to the backing substrate of silicon chip 1, after process, pad pasting is removed to front；
(4) silicon chip 1 is cleaned；
(5) silicon chip 1 is put in vapourizing furnace after cleaning；
(6) process is evaporated to the back side：The thickness of the first metal layer 2 isThe speed of evaporation isThe thickness of second metal layer 3 isThe speed of evaporation is3rd metal level 4
Thickness isThe speed of evaporation isThe thickness of the 4th metal level 5 isEvaporation
Speed isThe thickness of fifth metal layer 6 isThe speed of evaporation is
(7) come out of the stove detection.
It will be apparent to those skilled in the art that technical scheme that can be as described above and design, make it
Its various corresponding change and deformation, and all these changes and deformation should all belong to the present invention and want
Within the protection domain asked.
Claims (8)
1. it is a kind of for eutectic weldering silicon chip back side metallization structure, it is characterised in that：The structure is overleaf
The surface of silicon substrate (1) press away from silicon chip (1) from the close-by examples to those far off order be coated with successively the first metal layer (2),
Second metal layer (3), the 3rd metal level (4), the 4th metal level (5) and fifth metal layer (6), first
The material of metal level (2) is any one in titanium, vanadium or chromium, and the material of second metal layer (3) is nickel,
The material of the 3rd metal level (4) is silver, and the material of the 4th metal level (5) is tin copper or tin pewter, the
The material of five metal levels (6) is silver.
2. it is according to claim 1 for eutectic weldering silicon chip back side metallization structure, it is characterised in that：
The thickness of the first metal layer (2) is
3. it is according to claim 2 for eutectic weldering silicon chip back side metallization structure, it is characterised in that：
The thickness of second metal layer (3) is
4. it is according to claim 3 for eutectic weldering silicon chip back side metallization structure, it is characterised in that：
The thickness of the 3rd metal level (4) is
5. it is according to claim 4 for eutectic weldering silicon chip back side metallization structure, it is characterised in that：
The thickness of the 4th metal level (5) is
6. it is according to claim 5 for eutectic weldering silicon chip back side metallization structure, it is characterised in that：
The thickness of fifth metal layer (6) is
7. it is according to claim 6 for eutectic weldering silicon chip back side metallization structure, it is characterised in that：
When the material of the 4th metal level (5) is gun-metal, the percentage by weight of tin is in the gun-metal
55～65%, the percentage by weight of copper is 35～45%；When the material of the 4th metal level (5) is tin pewter,
The percentage by weight of tin is 90～94% in the tin pewter, and the percentage by weight of antimony is 6～10%.
8. the processing technology of the silicon chip back side metallization structure of eutectic weldering is used for described in a kind of claim 7, its
It is characterised by：The first metal layer (2), second metal layer (3), the 3rd metal level (4), the 4th metal level
And fifth metal layer (6) carries out plated film by way of evaporation, (5) wherein the first metal layer (2)
The speed of evaporation isThe speed of the evaporation of second metal layer (3) is3rd metal
The speed of evaporation of layer (4) isThe speed of the evaporation of the 4th metal level (5) is
The speed of the evaporation of fifth metal layer (6) is
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| CN201510740926.9A CN106653718B (en) | 2015-11-04 | 2015-11-04 | Silicon chip back side metallization structure and processing technology for eutectic weldering |
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| CN201510740926.9A CN106653718B (en) | 2015-11-04 | 2015-11-04 | Silicon chip back side metallization structure and processing technology for eutectic weldering |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110783292A (en) * | 2020-01-02 | 2020-02-11 | 南京市产品质量监督检验院 | Silicon wafer back metallization structure and manufacturing process thereof |
| CN114742819A (en) * | 2022-05-10 | 2022-07-12 | 上海晶岳电子有限公司 | Silicon wafer film pasting quality inspection management method and system in MOS tube back gold process |
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| CN102956515A (en) * | 2012-09-29 | 2013-03-06 | 北京时代民芯科技有限公司 | Silver-silicon eutectic soldering method of chips |
| CN203456442U (en) * | 2013-08-16 | 2014-02-26 | 江阴新顺微电子有限公司 | Low-cost high-applicability semiconductor chip back face metallization structure for eutectic package |
| CN103963375A (en) * | 2013-01-30 | 2014-08-06 | 苏州同冠微电子有限公司 | Silicon wafer back side metallized eutectic structure and manufacturing process thereof |
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2015
- 2015-11-04 CN CN201510740926.9A patent/CN106653718B/en active Active
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| CN102956515A (en) * | 2012-09-29 | 2013-03-06 | 北京时代民芯科技有限公司 | Silver-silicon eutectic soldering method of chips |
| CN103963375A (en) * | 2013-01-30 | 2014-08-06 | 苏州同冠微电子有限公司 | Silicon wafer back side metallized eutectic structure and manufacturing process thereof |
| CN203456442U (en) * | 2013-08-16 | 2014-02-26 | 江阴新顺微电子有限公司 | Low-cost high-applicability semiconductor chip back face metallization structure for eutectic package |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110783292A (en) * | 2020-01-02 | 2020-02-11 | 南京市产品质量监督检验院 | Silicon wafer back metallization structure and manufacturing process thereof |
| WO2021136222A1 (en) * | 2020-01-02 | 2021-07-08 | 南京市产品质量监督检验院 | Silicon wafer back metallization structure and manufacturing process therefor |
| CN113299621A (en) * | 2020-01-02 | 2021-08-24 | 南京市产品质量监督检验院 | Lightly doped n-type silicon wafer back metallization structure and manufacturing process thereof |
| CN114742819A (en) * | 2022-05-10 | 2022-07-12 | 上海晶岳电子有限公司 | Silicon wafer film pasting quality inspection management method and system in MOS tube back gold process |
| CN114742819B (en) * | 2022-05-10 | 2022-12-09 | 上海晶岳电子有限公司 | Silicon wafer film pasting quality inspection management method and system in MOS tube back gold process |
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| CN106653718B (en) | 2019-02-26 |
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