CN106653597B - A method of avoiding gate polycrystalline silicon etching pitting defects - Google Patents
A method of avoiding gate polycrystalline silicon etching pitting defects Download PDFInfo
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- CN106653597B CN106653597B CN201710078923.2A CN201710078923A CN106653597B CN 106653597 B CN106653597 B CN 106653597B CN 201710078923 A CN201710078923 A CN 201710078923A CN 106653597 B CN106653597 B CN 106653597B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 82
- 238000005530 etching Methods 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000007547 defect Effects 0.000 title claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims 1
- 239000011248 coating agent Substances 0.000 abstract description 7
- 238000000576 coating method Methods 0.000 abstract description 7
- 238000001259 photo etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of methods for avoiding gate polycrystalline silicon etching pitting defects, include: first step: forming the first hard exposure mask component layers on the polysilicon layer, wherein the first hard exposure mask component layers are a component parts of the hard exposure mask for etches polycrystalline silicon layer, and the first hard exposure mask component layers have first thickness；Second step: the second hard exposure mask component layers are formed on the first layer, wherein the second hard exposure mask component layers are the one other components of the hard exposure mask for etches polycrystalline silicon layer, and second hard exposure mask component layers have second thickness, wherein second thickness is arranged according to first thickness.In the method according to the present invention for avoiding gate polycrystalline silicon etching pitting defects, it, can be without being effectively prevented from gate polycrystalline silicon etching pitting defects in the case where carrying out technological operation change by the thickness according to the oxide skin(coating) in the hard exposure mask on polysilicon layer come the thickness of the second layer in the hard exposure mask on dynamic regulation polysilicon layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to which one kind avoids gate polycrystalline silicon etching
The method of pitting defects.
Background technique
In 0.15 technique, after etching polysilicon, sometimes pitting defects can be found on polysilicon after etching.Tool
Say to body, polycrystalline silicon etching method generally comprises according to prior art: photoetching agent pattern forming step, hard mask pattern are formed
Step and poly-silicon pattern forming step.
Fig. 1 schematically shows showing for the photoetching agent pattern forming step of polycrystalline silicon etching method according to prior art
It is intended to.As shown in Figure 1, sequentially forming oxide skin(coating) 21, SION layer 22 (oxide skin(coating) 21 and SION layer 22 on polysilicon layer 10
Constitute hard exposure mask) and photoresist layer 30, and form the pattern of photoresist.Fig. 2 schematically shows according to prior art
The schematic diagram of the hard mask pattern forming step of polycrystalline silicon etching method.Hereafter, as shown in Fig. 2, utilizing the photoetching for forming pattern
Glue-line 30 forms the pattern of SION layer 22 and oxide skin(coating) 21.Fig. 3 schematically shows polysilicon according to prior art
The schematic diagram of the poly-silicon pattern forming step of lithographic method.As shown in figure 3, utilizing the 22 pairs of polysilicon of SION layer for forming pattern
Layer 10 performs etching, to form poly-silicon pattern.
But as described above, in some cases, pitting defects, this defect can be found on polysilicon after etching
It will lead to product failure, reduce yield rate, cause to waste.Specifically, Fig. 4 schematically shows polycrystalline according to prior art
The schematic diagram for the etching polysilicon dent 40 that silicon etching method is formed.
It is therefore desirable to be capable of providing a kind of method that gate polycrystalline silicon etching pitting defects can be effectively avoided.
Summary of the invention
The technical problem to be solved by the present invention is to for drawbacks described above exists in the prior art, providing one kind can be effective
The method that ground avoids gate polycrystalline silicon etching pitting defects.
In order to achieve the above technical purposes, according to the present invention, it provides one kind and avoids gate polycrystalline silicon etching pitting defects
Method, comprising:
First step: the first hard exposure mask component layers are formed on the polysilicon layer, wherein the first hard exposure mask component layers are to be used for
One component part of the hard exposure mask of etches polycrystalline silicon layer, and the first hard exposure mask component layers have first thickness；
Second step: forming the second hard exposure mask component layers on the first layer, wherein the second hard exposure mask component layers are to use
In the one other component of the hard exposure mask of etches polycrystalline silicon layer, and the second hard exposure mask component layers have second thickness, wherein
According to first thickness, second thickness is set.
Preferably, in the method for avoiding gate polycrystalline silicon etching pitting defects, the first hard exposure mask component layers are
Silicon oxide layer, the second hard exposure mask component layers are SION layers.
Preferably, in the method for avoiding gate polycrystalline silicon etching pitting defects, in the second step, so that the
The sum of one thickness and the thickness of second thickness are equal to predetermined value.
Preferably, in the method for avoiding gate polycrystalline silicon etching pitting defects, in the second step, first
In the case that the first thickness of hard exposure mask component layers is less than 20A, 350A is set by the second thickness of the second hard exposure mask component layers.
Preferably, in the method for avoiding gate polycrystalline silicon etching pitting defects, in the second step, first
In the case that the first thickness of hard exposure mask component layers is greater than 20A and is less than 30A, the second thickness of the second hard exposure mask component layers is set
It is set to 340A.
Preferably, in the method for avoiding gate polycrystalline silicon etching pitting defects, in the second step, first
In the case that the first thickness of hard exposure mask component layers is greater than 30A and is less than 40A, the second thickness of the second hard exposure mask component layers is set
It is set to 330A.
Preferably, in the method for avoiding gate polycrystalline silicon etching pitting defects, in the second step, first
In the case that the first thickness of hard exposure mask component layers is greater than 40A and is less than 50A, the second thickness of the second hard exposure mask component layers is set
It is set to 320A.
Preferably, in the method for avoiding gate polycrystalline silicon etching pitting defects, in the second step, first
In the case that the first thickness of hard exposure mask component layers is greater than 50A and is less than 60A, the second thickness of the second hard exposure mask component layers is set
It is set to 310A.
Preferably, in the method for avoiding gate polycrystalline silicon etching pitting defects, in the second step, first
In the case that the first thickness of hard exposure mask component layers is greater than 60A and is less than 70A, the second thickness of the second hard exposure mask component layers is set
It is set to 300A.
Preferably, in the method for avoiding gate polycrystalline silicon etching pitting defects, in the second step, first
In the case that the first thickness of hard exposure mask component layers is greater than 70A and is less than 80A, the second thickness of the second hard exposure mask component layers is set
It is set to 290A.
In the method according to the present invention for avoiding gate polycrystalline silicon etching pitting defects, by according on polysilicon layer
The thickness of oxide skin(coating) in hard exposure mask carrys out the thickness of the second layer in the hard exposure mask on dynamic regulation polysilicon layer, can be effective
Ground avoids gate polycrystalline silicon etching pitting defects.Moreover, because SION material has lower selectivity, institute relative to silica
In the method according to the preferred embodiment of the invention for avoiding gate polycrystalline silicon etching pitting defects without carrying out changing for technological operation
Become.So the present invention can be without being effectively prevented from gate polycrystalline silicon etching dent in the case where carrying out technological operation change
Defect.
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantage and feature is more easily to understand, in which:
Fig. 1 schematically shows showing for the photoetching agent pattern forming step of polycrystalline silicon etching method according to prior art
It is intended to.
Fig. 2 schematically shows showing for the hard mask pattern forming step of polycrystalline silicon etching method according to prior art
It is intended to.
Fig. 3 schematically shows showing for the poly-silicon pattern forming step of polycrystalline silicon etching method according to prior art
It is intended to.
Fig. 4 schematically shows showing for the etching polysilicon dent of the formation of polycrystalline silicon etching method according to prior art
It is intended to.
Fig. 5 schematically shows the side according to the preferred embodiment of the invention for avoiding gate polycrystalline silicon etching pitting defects
The flow chart of method.
It should be noted that attached drawing is not intended to limit the present invention for illustrating the present invention.Note that indicating that the attached drawing of structure can
It can be not necessarily drawn to scale.Also, in attached drawing, same or similar element indicates same or similar label.
Specific embodiment
In order to keep the contents of the present invention more clear and understandable, combined with specific embodiments below with attached drawing in of the invention
Appearance is described in detail.
It was found by the inventors of the present invention that the basic reason of pitting defects occur on polysilicon after etching is polysilicon layer
On hard exposure mask in first layer it is relatively too thin, so that polysilicon layer cannot be protected during entire etching polysilicon, thus
Lead to polysilicon pitting defects.
Based on above-mentioned analysis propose the present invention, wherein according to the thickness of the oxide skin(coating) in the hard exposure mask on polysilicon layer come
The thickness of the second layer in hard exposure mask on dynamic regulation polysilicon layer, to avoid gate polycrystalline silicon etching pitting defects.
Particularly preferred embodiment of the invention is described below in conjunction with flow chart.
Fig. 5 schematically shows the side according to the preferred embodiment of the invention for avoiding gate polycrystalline silicon etching pitting defects
The flow chart of method.
Specifically, as shown in figure 5, the gate polycrystalline silicon etching pitting defects according to the preferred embodiment of the invention of avoiding
Method includes:
First step S1: forming the first hard exposure mask component layers on the polysilicon layer, wherein the first hard exposure mask component layers are to use
In a component part of the hard exposure mask of etches polycrystalline silicon layer, and the first hard exposure mask component layers have first thickness；
Second step S2: the second hard exposure mask component layers are formed on the first layer, wherein the second hard exposure mask component layers are
The one other component of hard exposure mask for etches polycrystalline silicon layer, and the second hard exposure mask component layers have second thickness,
It is middle that second thickness is arranged according to first thickness.
Specifically, for example, the first hard exposure mask component layers are silicon oxide layers.And for example, the second hard exposure mask component layers are
SION layers.
Preferably, it is arranged in this way to the property of can choose: makes a reservation for so that the sum of thickness of first thickness and second thickness is equal to
Numerical value.
In a particular embodiment, it is preferable that make following setting to such as property of can choose:
In the case where the first thickness of the first hard exposure mask component layers is less than 20A, by the second of the second hard exposure mask component layers
Thickness is set as 350A.
In the case where the first thickness of the first hard exposure mask component layers is greater than 20A and is less than 30A, by the second hard exposure mask component
The second thickness of layer is set as 340A.
In the case where the first thickness of the first hard exposure mask component layers is greater than 30A and is less than 40A, by the second hard exposure mask component
The second thickness of layer is set as 330A.
In the case where the first thickness of the first hard exposure mask component layers is greater than 40A and is less than 50A, by the second hard exposure mask component
The second thickness of layer is set as 320A.
In the case where the first thickness of the first hard exposure mask component layers is greater than 50A and is less than 60A, by the second hard exposure mask component
The second thickness of layer is set as 310A.
In the case where the first thickness of the first hard exposure mask component layers is greater than 60A and is less than 70A, by the second hard exposure mask component
The second thickness of layer is set as 300A.
In the case where the first thickness of the first hard exposure mask component layers is greater than 70A and is less than 80A, by the second hard exposure mask component
The second thickness of layer is set as 290A.
For example, as concrete application, the gate polycrystalline silicon etching pitting defects according to the preferred embodiment of the invention that avoid
Method can be used for manufacturing various semiconductor devices, such as PMOS transistor device and/or NMOS transistor device, memory
Deng.
In the method according to the preferred embodiment of the invention for avoiding gate polycrystalline silicon etching pitting defects, by according to more
The thickness of the oxide skin(coating) in hard exposure mask on crystal silicon layer carrys out the thickness of the second layer in the hard exposure mask on dynamic regulation polysilicon layer
Degree, can be effectively prevented from gate polycrystalline silicon etching pitting defects.Moreover, because SION material is relative to silica with lower
Selectivity, so the method according to the preferred embodiment of the invention for avoiding gate polycrystalline silicon etching pitting defects is without carrying out work
The change of skill operation.So the present invention can be without being effectively prevented from gate polycrystalline in the case where carrying out technological operation change
Silicon etching pitting defects.
In addition, it should be noted that, unless stated otherwise or point out, the otherwise term " first " in specification, "
Two ", the descriptions such as " third " are used only for distinguishing various components, element, the step etc. in specification, each without being intended to indicate that
Component, element, the logical relation between step or ordinal relation etc..
It is understood that although the present invention has been disclosed in the preferred embodiments as above, above-described embodiment not to
Limit the present invention.For any person skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications all are made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of variation.Therefore, anything that does not depart from the technical scheme of the invention are right according to the technical essence of the invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments still fall within the range of technical solution of the present invention protection
It is interior.
And it should also be understood that the present invention is not limited thereto and locate the specific method described, compound, material, system
Technology, usage and application are made, they can change.It should also be understood that term described herein be used merely to describe it is specific
Embodiment, rather than be used to limit the scope of the invention.Must be noted that herein and appended claims used in
Singular "one", "an" and "the" include complex reference, unless context explicitly indicates that contrary.Therefore, example
Such as, the citation to one or more elements is meaned to the citation of " element ", and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
The citation of multiple steps or device, and may include secondary step and second unit.It should be managed with broadest meaning
All conjunctions that solution uses.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as the function of also quoting from the structure
Equivalent.It can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
Moreover, the realization of the method and/or system of the embodiment of the present invention may include manual, automatic or selected by executing in combination
Task.Moreover, according to the method for the present invention and/or the real instrument and equipment of the embodiment of system, it is logical using operating system
It crosses hardware, software, or its combination and realizes several selected tasks.
Claims (9)
1. a kind of method for avoiding gate polycrystalline silicon etching pitting defects, characterized by comprising:
First step: the first hard exposure mask component layers are formed on the polysilicon layer, wherein the first hard exposure mask component layers are for etching
One component part of the hard exposure mask of polysilicon layer, and the first hard exposure mask component layers have first thickness；
Second step: the second hard exposure mask component layers are formed in the described first hard exposure mask component layers, wherein the second hard exposure mask component
Layer is the one other component of the hard exposure mask for etches polycrystalline silicon layer, and the second hard exposure mask component layers have the second thickness
Degree, wherein second thickness is arranged according to first thickness, so that the sum of thickness of first thickness and second thickness is equal to predetermined number
Value.
2. the method according to claim 1 for avoiding gate polycrystalline silicon etching pitting defects, which is characterized in that first covers firmly
Membrane component layer is silicon oxide layer, and the second hard exposure mask component layers are SION layers.
3. the method according to claim 1 or 2 for avoiding gate polycrystalline silicon etching pitting defects, which is characterized in that
In two steps, in the case where the first thickness of the first hard exposure mask component layers is less than 20 angstroms, by the of the second hard exposure mask component layers
Two thickness are set as 350 angstroms.
4. the method according to claim 1 or 2 for avoiding gate polycrystalline silicon etching pitting defects, which is characterized in that
In two steps, it is greater than 20 angstroms in the first thickness of the first hard exposure mask component layers and in the case where less than 30 angstroms, by the second hard exposure mask
The second thickness of component layers is set as 340 angstroms.
5. the method according to claim 1 or 2 for avoiding gate polycrystalline silicon etching pitting defects, which is characterized in that
In two steps, it is greater than 30 angstroms in the first thickness of the first hard exposure mask component layers and in the case where less than 40 angstroms, by the second hard exposure mask
The second thickness of component layers is set as 330 angstroms.
6. the method according to claim 1 or 2 for avoiding gate polycrystalline silicon etching pitting defects, which is characterized in that
In two steps, it is greater than 40 angstroms in the first thickness of the first hard exposure mask component layers and in the case where less than 50 angstroms, by the second hard exposure mask
The second thickness of component layers is set as 320 angstroms.
7. the method according to claim 1 or 2 for avoiding gate polycrystalline silicon etching pitting defects, which is characterized in that
In two steps, it is greater than 50 angstroms in the first thickness of the first hard exposure mask component layers and in the case where less than 60 angstroms, by the second hard exposure mask
The second thickness of component layers is set as 310 angstroms.
8. the method according to claim 1 or 2 for avoiding gate polycrystalline silicon etching pitting defects, which is characterized in that
In two steps, it is greater than 60 angstroms in the first thickness of the first hard exposure mask component layers and in the case where less than 70 angstroms, by the second hard exposure mask
The second thickness of component layers is set as 300 angstroms.
9. the method according to claim 1 or 2 for avoiding gate polycrystalline silicon etching pitting defects, which is characterized in that
In two steps, it is greater than 70 angstroms in the first thickness of the first hard exposure mask component layers and in the case where less than 80 angstroms, by the second hard exposure mask
The second thickness of component layers is set as 290 angstroms.
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| CN201710078923.2A CN106653597B (en) | 2017-02-14 | 2017-02-14 | A method of avoiding gate polycrystalline silicon etching pitting defects |
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| CN201710078923.2A CN106653597B (en) | 2017-02-14 | 2017-02-14 | A method of avoiding gate polycrystalline silicon etching pitting defects |
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| CN106653597B true CN106653597B (en) | 2019-09-17 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6232002B1 (en) * | 1998-11-06 | 2001-05-15 | Advanced Micro Devices, Inc. | Bilayer anti-reflective coating and etch hard mask |
| CN1336573A (en) * | 2000-08-02 | 2002-02-20 | 联华电子股份有限公司 | Photoetching process |
| CN1877796A (en) * | 2005-06-07 | 2006-12-13 | 台湾积体电路制造股份有限公司 | Deep structure forming method |
| CN1959958A (en) * | 2005-10-31 | 2007-05-09 | 中芯国际集成电路制造(上海)有限公司 | Method and structure for doping grid pole of polysilicon in use for MDS transistor of strain silicon |
| CN101740370A (en) * | 2008-11-26 | 2010-06-16 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Silicon gate etching method and method for improving matching of linewidth chamber of silicon gate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030045118A1 (en) * | 2001-09-05 | 2003-03-06 | United Microelectronics Corp. | Method for controlling the critical dimension of the polysilicon gate by etching the hard mask |
-
2017
- 2017-02-14 CN CN201710078923.2A patent/CN106653597B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6232002B1 (en) * | 1998-11-06 | 2001-05-15 | Advanced Micro Devices, Inc. | Bilayer anti-reflective coating and etch hard mask |
| CN1336573A (en) * | 2000-08-02 | 2002-02-20 | 联华电子股份有限公司 | Photoetching process |
| CN1877796A (en) * | 2005-06-07 | 2006-12-13 | 台湾积体电路制造股份有限公司 | Deep structure forming method |
| CN1959958A (en) * | 2005-10-31 | 2007-05-09 | 中芯国际集成电路制造(上海)有限公司 | Method and structure for doping grid pole of polysilicon in use for MDS transistor of strain silicon |
| CN101740370A (en) * | 2008-11-26 | 2010-06-16 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Silicon gate etching method and method for improving matching of linewidth chamber of silicon gate |
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