CN106653088A - Pseudo differential type semiconductor read-only memory array based on dynamic resistance unit - Google Patents
Pseudo differential type semiconductor read-only memory array based on dynamic resistance unit Download PDFInfo
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- CN106653088A CN106653088A CN201610883758.3A CN201610883758A CN106653088A CN 106653088 A CN106653088 A CN 106653088A CN 201610883758 A CN201610883758 A CN 201610883758A CN 106653088 A CN106653088 A CN 106653088A
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- bit line
- unit
- electric resistor
- dynamic electric
- read
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000011156 evaluation Methods 0.000 claims description 10
- 238000003491 array Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims 1
- 230000001629 suppression Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- Read Only Memory (AREA)
Abstract
The invention discloses a pseudo-differential semiconductor read-only memory array based on a dynamic resistance unit, which comprises a memory array unit, a pre-charging unit and a differential sense amplifier, and is characterized by also comprising a dynamic resistance unit; the drain electrode of each memory cell in the memory array unit is connected with a differential bit line, the grid electrode of each memory cell is connected with a word line, and the source electrode of each memory cell is grounded; the upper end of the differential bit line is output to the differential sense amplifier through the dynamic resistance unit under the control of a bit selection signal, and the lower end of the differential bit line is connected with the pre-charging unit. The invention has the advantages of reducing the access time of the memory and improving the common mode noise suppression capability of the memory.
Description
Technical field
The present invention relates to semiconductor memory design technical field, more particularly to a kind of semiconductor ROM storage battle array
Row.
Background technology
Semiconductor ROM is typically made up of address decoder, storage array and sense amplifier, wherein storing battle array
Row include the multiple memory cells being arranged in rows with column array.Each memory cell includes a transistor, and one is given
The grid of each transistor is connected to wordline in row, and the drain terminal of each transistor in a given row is connected to into bit line.In order to read
The state of each memory cell is taken, typically comes the voltage on each word line precharge to some voltage, and reading bit line
The data for judging storage are " 1 " or " 0 ".By the data for detecting the voltage of bit line to sense storage, it usually needs waiting is certain
Stabilization time could interpretation storage data.With the increase of memory cell, the parasitic capacitance on bit line needs more steady
Fix time, become the access speed bottleneck of memory.
The content of the invention
(1) technical problem to be solved
In view of this, it is an object of the present invention to provide a kind of artifact fraction semiconductor based on dynamic electric resistor unit
Read storage array, can quickly read data storage, by using difference form bit line, there is provided dynamic electric resistor, and reduce bit line
Upper voltage swing, so as to reduce to the parasitic capacitance charging interval, solves the bottleneck in read-only storage access speed.
(2) technical scheme
In order to achieve the above object, a kind of artifact fraction semiconductor based on dynamic electric resistor unit of present invention offer is read-only deposits
Storage array, including cells of memory arrays, precharge unit, difference sense amplifier, it is characterised in that also including dynamic electric resistor list
Unit；Each memory cell is made up of a transistor in cells of memory arrays, and transistor drain is connected with differential bit line, grid with
Wordline is connected, source ground；Jing dynamic electric resistor units under the control of signal are selected to export sensitive to difference in place in differential bit line upper end
Amplifier, differential bit line lower end connection precharge unit.
Wherein, differential bit line can be divided into homophase bit line or anti-phase bit line；It is connected with homophase bit line, then the data for storing are to patrol
Collect level " 0 "；If being connected with anti-phase bit line, what is stored is logic level " 1 ".
Wherein, precharge unit is used for one charging path of offer between bit line and power supply (VDD) between precharge phase,
The positive end of oppisite phase of differential bit line is all pre-charged to into VDD, bit line disconnects with the connection of precharge unit during evaluation.
Wherein, dynamic electric resistor unit between precharge phase by the connecting node of memory cell and difference sense amplifier unit
VDD is charged to, dynamic electric resistor unit disconnects during evaluation, does not affect between memory cell and difference sense amplifier unit
Signal transmission.
(3) beneficial effect
The positive effect being had based on the read-only storage array of artifact fraction semiconductor of dynamic electric resistor unit that the present invention is provided
It is really：
(1) using dynamic electric resistor unit, accelerate the discharge and recharge of memory cell, be conducive to reducing the store access time.
(2) by adopting differential bit line, strengthen the suppression to common-mode noise, and difference form output voltage is provided, have
Operating circuit and simplified circuit beneficial to offer memory.
Description of the drawings
Fig. 1 is the read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit of one embodiment of the present of invention
Schematic diagram；
Fig. 2 is the read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit of one embodiment of the present of invention
Reading data sequential chart；
Fig. 3 is the read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit of one embodiment of the present of invention
Precharge equivalent circuit diagram；
Fig. 4 is the read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit of one embodiment of the present of invention
Evaluation during the selected equivalent circuit diagram of " 0 " unit；
Fig. 5 is the read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit of one embodiment of the present of invention
Evaluation during the selected equivalent circuit diagram of " 1 " unit.
Specific embodiment
To make the object, technical solutions and advantages of the present invention more clear bright from below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in further detail.
Fig. 1 is the read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit of one embodiment of the present of invention
Schematic diagram, be made up of cells of memory arrays, precharge unit, dynamic electric resistor unit and difference sense amplifier.Memory cell
It is made up of a MOS transistor, (WL here includes WL to be connected to wordline WL with the memory cell grid of a line0-WLn, every time
There was only a wordline when reading data for high level, other bit lines are low level).Cell source is connected to the ground, and storage is single
If unit's drain electrode is with homophase bit line BL in differential bit line, and (BL here includes BL0～BLn) be connected, that is, what is stored is logic level
" 0 ", as shown in storage unit 0；If conversely, with anti-phase bit line in differential bit lineIt is connected then store is logic level " 1 ", such as
Shown in memory cell 1.
In order to reduce the charging interval of electric capacity on bit line, the present invention introduces cascode transistors, the meaning in differential bit line
It is the transistor cascaded on a transistor, such as the M6 and M7 in Fig. 1 belongs to this kind of transistor.Realize keeping poor
In the case of difference between current is constant in lane place line, reduce the voltage change amplitude of oscillation on bit line.If memory cell 0 is selected, then same-phase
Line BLn-1Voltage is pulled low, and anti-phase bit lineVoltage does not occur decline, and is to maintain constant.Bit line BLn-1WithUpper signal is not real difference form, therefore claims the type memory to be artifact fraction read-only storage.Artifact fraction
Read-only storage array advantage has at 3 points.First, the data in memory are by transistor drain in memory cell and homophase bit line BL
Or with anti-phase bit lineIt is connected and determines.As long as by judging that the voltage difference of differential bit line is just or negative, you can obtain what is stored
Data are logic level " 1 " or " 0 ".It is equal so as to ensure each row transistor quantity of storage array.For row address decoding
For device, the load of each row address decoder is identical, is conducive to simplifying circuit design；Secondly, the read-only storage of artifact fraction
Array adopts differential bit line, improves the rejection ability to common-mode noise；Finally, the read-only storage array offer difference of pseudo-differential is defeated
Go out, strengthen the output signal amplitude of oscillation, be conducive to next stage circuit to design.
Fig. 2 is the read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit of one embodiment of the present of invention
Reading data sequential chart.
Fig. 3 is the read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit of one embodiment of the present of invention
Precharge equivalent circuit diagram.Wherein wordline WL (WL0-WLn).Between precharge phase, clock signal (CLK), clock control signal
(CLKS), position selects signal (BS) and wordline (WL) to be low level, because CLK and CLKS are low level, now M0, M1, M2,
M3, M10, M11, M12 and M13 are in conducting state, can be equivalent to small resistor.Select signal (BS) and row selects signal (WL) in position
Low level is, so M4, M5, M6 and M7 now disconnect, big resistance can be equivalent to, it can be seen that the difference between precharge phase
The input of bit line and difference sense amplifier is charged to high level, this can improve evaluation during electric current on bit line
Change and the sensitivity of raising difference sense amplifier, so as to improve reaction speed.
During evaluation, clock signal (CLK), clock control signal (CLKS) is high level, and corresponding metal-oxide-semiconductor is closed
It is disconnected, select the low and high level of signal and wordline to select corresponding memory cell by position.
Fig. 4 is the read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit of one embodiment of the present of invention
Evaluation during the selected equivalent circuit diagram of " 0 " unit.Now clock signal (CLK), clock control signal (CLKS), position choosing
Signal (BS) is high level, and M0, M1, M2, M3, M10, M11, M12 and M13 are in off state.It is such as Fig. 4 statements
Corresponding wordline (the WL of " 0 " unitn) WL for high level0～WLn-1Be low level, represent that " 0 " unit is selected, now with together
Phase line BLnConnected metal-oxide-semiconductor conducting, is equivalent to a little resistance, by BLnPlace position is moved to, so as to homophase bit line BLn's
Current potential is less than reverse bit lineCurrent potential, be output as low level.
Fig. 5 is the read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit of one embodiment of the present of invention
Evaluation during the selected equivalent circuit diagram of " 1 " unit.Now clock signal (CLK), clock control signal (CLKS), position choosing
Signal (BS) is high level, and M0, M1, M2, M3, M10, M11, M12 and M13 are in off state.As shown in figure 5, working as word
Line (WLn-1) it is high level WL0～WLn-2And WLnWhen being low level, represent that " 1 " unit is selected, now with reverse bit lineConnected metal-oxide-semiconductor is opened, and moves reverse bit line to ground potential, so as to the current potential of homophase bit line is higher than the electricity of reverse bit line
Position, is output as 1.
Particular embodiments described above, has been carried out further in detail to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail bright, it should be understood that the foregoing is only the specific embodiment of the present invention, be not limited to the present invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc. should be included in the protection of the present invention
Within the scope of.
Claims (4)
1. a kind of read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit, including cells of memory arrays, preliminary filling
Electric unit, difference sense amplifier, it is characterised in that also including dynamic electric resistor unit；Each storage is single in cells of memory arrays
Unit is made up of a transistor, and transistor drain is connected with differential bit line, and grid is connected with wordline, source ground；Differential bit line
Upper end selects in place Jing dynamic electric resistor units under the control of signal to export and gives difference sense amplifier, differential bit line lower end connection preliminary filling
Electric unit.
2. a kind of read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit according to claim 1, its
It is characterised by, differential bit line can be divided into homophase bit line or anti-phase bit line；It is connected with homophase bit line, then the logic level for storing is
“0”；If being connected with anti-phase bit line, the logic level for storing is " 1 ".
3. a kind of read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit according to claim 1, its
It is characterised by, precharge unit is given between bit line and power supply (VDD) between precharge phase and provides a charging path, by differential bit
The positive end of oppisite phase of line is all pre-charged to VDD, and bit line disconnects with the connection of precharge unit during evaluation.
4. a kind of read-only storage array of artifact fraction semiconductor based on dynamic electric resistor unit according to claim 1, its
It is characterised by, dynamic electric resistor unit charges the connecting node of memory cell and difference sense amplifier unit between precharge phase
To VDD, dynamic electric resistor unit disconnects during evaluation, does not affect the signal between memory cell and difference sense amplifier unit
Transmission.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610883758.3A CN106653088A (en) | 2016-10-10 | 2016-10-10 | Pseudo differential type semiconductor read-only memory array based on dynamic resistance unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610883758.3A CN106653088A (en) | 2016-10-10 | 2016-10-10 | Pseudo differential type semiconductor read-only memory array based on dynamic resistance unit |
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| CN106653088A true CN106653088A (en) | 2017-05-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610883758.3A Pending CN106653088A (en) | 2016-10-10 | 2016-10-10 | Pseudo differential type semiconductor read-only memory array based on dynamic resistance unit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1199229A (en) * | 1997-03-31 | 1998-11-18 | 精工爱普生株式会社 | Low power memory including selective precharge circuit |
| CN101681671A (en) * | 2007-05-18 | 2010-03-24 | 高通股份有限公司 | Method and apparatus for reducing leakage current in memory arrays |
| CN102637449A (en) * | 2012-04-13 | 2012-08-15 | 中国科学院微电子研究所 | Pseudo differential storage array |
-
2016
- 2016-10-10 CN CN201610883758.3A patent/CN106653088A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1199229A (en) * | 1997-03-31 | 1998-11-18 | 精工爱普生株式会社 | Low power memory including selective precharge circuit |
| CN101681671A (en) * | 2007-05-18 | 2010-03-24 | 高通股份有限公司 | Method and apparatus for reducing leakage current in memory arrays |
| CN102637449A (en) * | 2012-04-13 | 2012-08-15 | 中国科学院微电子研究所 | Pseudo differential storage array |
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