CN106653088A - Pseudo differential type semiconductor read-only memory array based on dynamic resistance unit - Google Patents

Abstract

The invention discloses a pseudo-differential semiconductor read-only memory array based on a dynamic resistance unit, which includes a memory array unit, a pre-charging unit, and a differential sensitive amplifier, and is characterized in that it also includes a dynamic resistance unit; The cell drain is connected to the differential bit line, the gate of each memory cell is connected to the word line, and the source is grounded; the upper end of the differential bit line is output to the differential sense amplifier through the dynamic resistance unit under the control of the bit selection signal, and the lower end of the differential bit line is connected to pre-charged unit. The invention has the advantages of reducing the access time of the memory and improving the common mode noise suppression ability of the memory.

Description

A Pseudo-differential Semiconductor Read-Only Memory Array Based on Dynamic Resistance Unit

technical field

The invention relates to the technical field of semiconductor memory design, in particular to a semiconductor read-only memory storage array.

Background technique

A semiconductor read-only memory is generally composed of an address decoder, a memory array and a sense amplifier, wherein the memory array includes a plurality of memory cells arranged in a row and column array. Each memory cell includes a transistor with the gate of each transistor in a given row connected to a word line and the drain of each transistor in a given column connected to a bit line. In order to read the state of each memory cell, each word line is generally precharged to a certain voltage, and the voltage on the bit line is read to determine whether the stored data is "1" or "0". The stored data is sensed by detecting the voltage of the bit line, and it usually needs to wait for a certain stabilization time to interpret the stored data. With the increase of memory cells, the parasitic capacitance on the bit line requires more stabilization time, which becomes the bottleneck of the access speed of the memory.

Contents of the invention

(1) Technical problems to be solved

In view of this, the object of the present invention is to provide a pseudo-differential semiconductor read-only memory array based on a dynamic resistance unit, which can quickly read stored data, and provide dynamic resistance by using a differential bit line, and reduce the voltage on the bit line. Voltage swing, thereby reducing the charging time of the parasitic capacitance, and solving the bottleneck of the access speed of the read-only memory.

(2) Technical solutions

In order to achieve the above object, the present invention provides a pseudo-differential semiconductor read-only memory array based on a dynamic resistance unit, comprising a storage array unit, a precharge unit, and a differential sense amplifier, and is characterized in that it also includes a dynamic resistance unit; the storage array unit Each memory cell in the system is composed of a transistor, the drain of the transistor is connected to the differential bit line, the gate is connected to the word line, and the source is grounded; the upper end of the differential bit line is output to the differential sense amplifier through the dynamic resistance unit under the control of the bit selection signal , the lower end of the differential bit line is connected to the pre-charging unit.

Among them, the differential bit line can be divided into the same phase line or the reverse phase line; if it is connected to the same phase line, the stored data is logic level "0"; if it is connected to the reverse phase line, the stored data is the logic level "1".

Among them, the pre-charging unit is used to provide a charging path between the bit line and the power supply (VDD) during the pre-charging period, and pre-charge the positive and negative terminals of the differential bit line to VDD. During the evaluation period, the bit line and the pre-charging unit is disconnected.

Wherein, the dynamic resistance unit charges the connection node between the storage unit and the differential sense amplifier unit to VDD during the precharging period, and the dynamic resistance unit is disconnected during the evaluation period, which does not affect the signal transmission between the storage unit and the differential sense amplifier unit.

(3) Beneficial effects

The positive effects of the pseudo-differential semiconductor read-only memory array based on the dynamic resistance unit provided by the present invention are:

(1) The dynamic resistance unit is adopted to accelerate the charge and discharge of the storage unit, which is beneficial to reduce the access time of the memory.

(2) By adopting the differential bit line, the suppression of the common mode noise is enhanced, and the output voltage in the differential form is provided, which is beneficial to provide the working circuit of the memory and simplify the circuit.

Description of drawings

Fig. 1 is the schematic diagram of the pseudo-differential type semiconductor read-only memory array based on the dynamic resistance unit of an embodiment of the present invention;

Fig. 2 is the timing diagram of the reading data of the pseudo-differential type semiconductor read-only memory array based on the dynamic resistance unit of an embodiment of the present invention;

Fig. 3 is the precharge equivalent circuit diagram of the pseudo-differential type semiconductor read-only memory array based on the dynamic resistance unit of an embodiment of the present invention;

Fig. 4 is the equivalent circuit diagram of "0" unit being selected during the evaluation period of the pseudo-differential type semiconductor read-only memory array based on the dynamic resistance unit according to an embodiment of the present invention;

FIG. 5 is an equivalent circuit diagram of a "1" cell being selected during evaluation of a dynamic resistance cell-based pseudo-differential semiconductor read-only memory array according to an embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

1 is a schematic diagram of a pseudo-differential semiconductor read-only memory array based on a dynamic resistance unit according to an embodiment of the present invention, which is composed of a memory array unit, a precharge unit, a dynamic resistance unit and a differential sense amplifier. The storage unit is composed of a MOS transistor, and the gates of the storage units in the same row are connected to the word line WL (where WL includes WL ₀ -WL _n , only one word line is high level when reading data each time, and the other bit lines is low level). The source of the memory cell is connected to the ground, and if the drain of the memory cell is connected to the same phase line BL in the differential bit line (the BL here includes BL ₀ ~ BL _n ), that is, the logic level "0" is stored, such as the memory cell 0 shown; on the contrary, if the reverse phase line in the differential bit line If connected, the logic level "1" is stored, as shown in memory cell 1.

In order to reduce the charging time of the capacitor on the bit line, the present invention introduces a cascode transistor on the differential bit line, which means cascaded transistors on one transistor, such as M6 and M7 in FIG. 1 belong to this type of transistor. It realizes reducing the voltage variation swing on the bit line while keeping the current difference on the differential bit line constant. If memory cell 0 is selected, the voltage of the same phase line BL _n-1 is pulled low, and the voltage of the opposite phase line The voltage does not drop, but stays the same. bit line BL _n-1 and The upper signal is not a true differential form, so this type of memory is called a pseudo-differential read-only memory. There are three advantages of the pseudo-differential read-only memory array. First, the data in the memory is connected by the drain of the transistor in the memory unit to the same phase line BL or to the opposite phase line connected decision. Just by judging whether the voltage difference of the differential bit line is positive or negative, it can be obtained whether the stored data is logic level "1" or "0". Therefore, the number of transistors in each row of the memory array is guaranteed to be equal. For row address decoders, the load of each row address decoder is the same, which is beneficial to simplify circuit design; secondly, the pseudo-differential read-only memory array uses differential bit lines to improve the ability to suppress common-mode noise; finally , the pseudo-differential read-only memory array provides differential output, enhances the output signal swing, and is beneficial to the next-level circuit design.

FIG. 2 is a timing diagram of reading data of a pseudo-differential semiconductor read-only memory array based on a dynamic resistance unit according to an embodiment of the present invention.

FIG. 3 is a precharge equivalent circuit diagram of a pseudo-differential semiconductor read-only memory array based on a dynamic resistance unit according to an embodiment of the present invention. Wherein the word line WL (WL ₀ -WL _n ). During pre-charging, the clock signal (CLK), clock control signal (CLKS), bit select signal (BS) and word line (WL) are all at low level, since both CLK and CLKS are at low level, at this time M0, M1 , M2 , M3 , M10 , M11 , M12 and M13 are all in a conduction state and can be equivalent to small resistors. The bit selection signal (BS) and the row selection signal (WL) are both low level, so M4, M5, M6 and M7 are disconnected at this time, which can be equivalent to a large resistance. It can be seen that the differential bit line and the The inputs of the differential sense amplifier are both charged high, which increases the current change on the bit line during evaluation and increases the sensitivity of the differential sense amplifier, thereby increasing the reaction speed.

During the evaluation period, the clock signal (CLK) and the clock control signal (CLKS) are high level, the corresponding MOS transistor is turned off, and the corresponding memory cell is selected by the high and low levels of the bit selection signal and the word line.

FIG. 4 is an equivalent circuit diagram in which a "0" cell is selected during evaluation of a dynamic resistance cell-based pseudo-differential semiconductor read-only memory array according to an embodiment of the present invention. At this time, the clock signal (CLK), the clock control signal (CLKS), and the bit selection signal (BS) are all at high level, and M0, M1, M2, M3, M10, M11, M12 and M13 are all in the off state. As shown in Figure 4, the word line (WL _n ) corresponding to the "0" unit is at high level and WL ₀ ~ WL _n-1 are all at low level, indicating that the "0" unit is selected. The MOS transistor connected to BL _n is turned on, which is equivalent to a small resistance, pulling BL _n to the ground position, so that the potential of the same phase line BL _n is lower than that of the reverse bit line The potential of the output is low.

FIG. 5 is an equivalent circuit diagram of a "1" cell being selected during evaluation of a dynamic resistance cell-based pseudo-differential semiconductor read-only memory array according to an embodiment of the present invention. At this time, the clock signal (CLK), the clock control signal (CLKS), and the bit selection signal (BS) are all at high level, and M0, M1, M2, M3, M10, M11, M12 and M13 are all in the off state. As shown in Figure 5, when the word line (WL _n-1 ) is at a high level, WL ₀ ~ WL _n-2 and WL _n are both at a low level, which means that the "1" cell is selected. The connected MOS transistor is turned on, and the reverse bit line is pulled to the ground potential, so that the potential of the same phase line is higher than the potential of the reverse bit line, and the output is 1.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (4)

1. A pseudo-differential type semiconductor read-only memory array based on dynamic resistance unit, comprising storage array unit, precharge unit, differential sense amplifier, is characterized in that, also comprises dynamic resistance unit; In the storage array unit, each storage unit is composed of It consists of a transistor, the drain of the transistor is connected to the differential bit line, the gate is connected to the word line, and the source is grounded; the upper end of the differential bit line is output to the differential sense amplifier through the dynamic resistance unit under the control of the bit selection signal, and the lower end of the differential bit line is connected to pre-charged unit. 2. a kind of pseudo-differential semiconductor read-only memory array based on dynamic resistance unit according to claim 1, is characterized in that, differential bit line can be divided into same phase line or antiphase line; Be connected with same phase line, Then the stored logic level is "0"; if it is connected to the reverse phase line, the stored logic level is "1". 3. A kind of pseudo-differential type semiconductor read-only memory array based on dynamic resistance unit according to claim 1, it is characterized in that, precharge unit provides a charging path between bit line and power supply (VDD) during precharge , precharge both positive and negative terminals of the differential bit line to VDD, and the connection between the bit line and the precharged cell is disconnected during the evaluation. 4. A kind of pseudo-differential type semiconductor read-only memory array based on dynamic resistance unit according to claim 1, it is characterized in that, dynamic resistance unit charges the connection node of storage unit and differential sense amplifier unit to VDD during precharging , the dynamic resistance unit is disconnected during the evaluation, which does not affect the signal transmission between the storage unit and the differential sense amplifier unit.