CN106652930A - Display panel, data driving circuit thereof, and display device - Google Patents
Display panel, data driving circuit thereof, and display device Download PDFInfo
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- CN106652930A CN106652930A CN201610910235.3A CN201610910235A CN106652930A CN 106652930 A CN106652930 A CN 106652930A CN 201610910235 A CN201610910235 A CN 201610910235A CN 106652930 A CN106652930 A CN 106652930A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- Crystallography & Structural Chemistry (AREA)
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract
An embodiment of the invention discloses a display panel, a data driving circuit thereof, and a display device. The data driving circuit comprises at least one switching circuit. The switching circuit comprises two switching devices. A first switching device transmits a data signal which is received from a data lead wire to a data wire. A second switching device transmits the data signal which is received from the data lead wire to the data wire. When the data signal is in a forward data state, a first control wire starts the first switching device and simultaneously a second control wire starts the second switching device. When the data signal is in a reverse data state, the first control wire starts the first switching device and simultaneously the second control wire stops the second switching device. According to the display panel, the data driving circuit and the display device, the data driving circuit ensures no positive frame charging capability loss of a display panel through driving by a large-size switching circuit, and furthermore ensures negative frame charging capability of the display panel through a small-size switching circuit, thereby realizing an effect of reducing power consumption of the display panel.
Description
Technical field
The present embodiments relate to Display Technique, more particularly to a kind of display floater and its data drive circuit, Yi Jixian
Showing device.
Background technology
Liquid crystal display is the main product of present field of liquid crystal display, the brightness of liquid crystal display, contrast, color and
The display effects such as visible angle are mainly determined that 80% cost of liquid crystal display is also concentrated mainly on liquid crystal by display panels
In display floater, therefore display panels are the principal elements for determining liquid crystal display quality and cost.Display panels
The cost that data drive circuit can be adopted reduces driving chip reduces the purpose of panel cost, data drive circuit control one
Single data lead drives the polarity of at least two data lines, the data-signal of data lead transmission to replace and overturn,
Drive so as to realize showing.
The schematic diagram of the data drive circuit of the display floater for providing for prior art as shown in Figure 1A, the data-driven electricity
Road 10 is 2:6CMOS multiplexer circuits, the data drive circuit 10 respectively with six SECO line CKHR1, CKHG1,
CKHB1, XCKHR1, XCKHG1 and XCKHB1, two data lead S1 and S2 and a plurality of data lines (here only illustrate D1～
D6) electrically connect, the data drive circuit 10 includes multiple switching switch (demux switches) 11.The optional display floater of here is row
Inverted pattern, then Figure 1B is the driver' s timing figure of Figure 1A, after the scan line (not shown) of line n is opened in m frames, six
SECO line drives multiple demux switches 11 first backward data wire D1～D6 transmission data signals, wherein data lead S1 pair
Corresponding pixel carries out positive charged, and data lead S2 carries out negatively charged to corresponding pixel, after the (n+1)th row is opened, repeats
Same action.Data drive circuit 10 repeats same action in m+1 frames, but data lead S1 is filled to corresponding pixel
Negative electricity, data lead S2 carries out positive charged to corresponding pixel.It follows that per data in the refresh process for completing a frame
The corresponding demux of lead switchs 11 (by taking FHD products as an example) and has switched 1920 times.
Discharge and recharge to intrinsic electric capacity and parasitic capacitance when AC power dissipation derives from panel refresh in known display floater,
Therefore data drive circuit can account for the 70% of whole display floater power consumption, and the power consumption of data drive circuit is opened by demux
The size of pass and discharge and recharge number of times are determined.With the lifting of display floater resolution ratio and the increase of panel refresh frequency and right
The not enough worry of pixel charging capability, the size and discharge and recharge number of times of data drive circuit all increase therewith, cause display floater
Power consumption it is increasing.
The content of the invention
The embodiment of the present invention provides a kind of display floater and its data drive circuit and display device, to reduce showing
The power consumption of panel.
In a first aspect, embodiments providing a kind of data drive circuit of display floater, the data drive circuit
Including：At least one switching circuit；
The switching circuit includes two switch, wherein,
The output end of first switch is electrically connected with a data line, input is electrically connected with a data lead, with
And control end is electrically connected with first control line, under the control of first control line, first switch is opened
Or close, and open when by the data signal transmission received from the data lead to the data wire；
The output end of second switch is electrically connected with the data wire, input is electrically connected with the data lead, with
And control end is electrically connected with Article 2 control line, under the control of the Article 2 control line, second switch is opened
Or close, and open when by the data signal transmission received from the data lead to the data wire；
The data-signal has forward data state and negative sense data mode, when the data-signal is forward data shape
During state, first switch is opened second described in the Article 2 control line traffic control simultaneously described in the first control line traffic control
Individual switch is opened, and when the data-signal is negative sense data mode, is cut for first described in the first control line traffic control
Parallel operation is opened second switch described in the Article 2 control line traffic control simultaneously and is closed.
Second aspect, the embodiment of the present invention additionally provides a kind of display floater, and the display floater is including driving chip and such as
The upper data drive circuit.
The third aspect, the embodiment of the present invention additionally provides a kind of display device, and the display device includes as above aobvious
Show panel.
In the embodiment of the present invention, when data-signal is forward data state, first in each switching circuit switching
Device and second switch are opened simultaneously, it is ensured that large-sized switching circuit is driven；When data-signal is negative sense data
During state, first switch in each switching circuit is opened second switch simultaneously and is closed, using small size switching electricity
Road is driven.Obviously the present invention drives the positive frame charging ability for ensureing display floater not to be damaged by large scale switching circuit
Consumption, drives the negative frame charging ability for ensureing display floater to also reduce the chi of switching circuit simultaneously by small size switching circuit
It is very little, reach the effect for reducing the power consumption of data drive circuit and then reducing display floater power consumption.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description does one and simply introduces, it should be apparent that, drawings in the following description are these
Some bright embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can be with root
Other accompanying drawings are obtained according to these accompanying drawings.
The schematic diagram of the data drive circuit of the display floater that Figure 1A is provided for prior art；
Figure 1B is the driver' s timing figure of Figure 1A；
Fig. 2A is the schematic diagram of the data drive circuit of the display floater that one embodiment of the invention is provided；
Fig. 2 B are the driver' s timing figures of Fig. 2A；
Fig. 3 A are the schematic diagrames of the data drive circuit of the display floater that another embodiment of the present invention is provided；
Fig. 3 B are the driver' s timing figures of Fig. 3 A；
Fig. 4 A are the schematic diagrames of the data drive circuit of the display floater that further embodiment of the present invention is provided；
Fig. 4 B are the driver' s timing figures of Fig. 4 A；
Fig. 5 A are the schematic diagrames of the data drive circuit of the display floater that another embodiment of the invention is provided；
Fig. 5 B are the driver' s timing figures of Fig. 5 A；
Fig. 6 is the schematic diagram of display floater provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, hereinafter with reference to the embodiment of the present invention in it is attached
Figure, by embodiment technical scheme is clearly and completely described, it is clear that described embodiment is the present invention one
Section Example, rather than the embodiment of whole.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out the every other embodiment obtained under the premise of creative work, belong to the scope of protection of the invention.
The size and discharge and recharge number of times that the power consumption of given data drive circuit is switched by demux is determined, it is clear that reduce demux
The size and discharge and recharge number of times of switch can reduce the purpose of power consumption.But the size for reducing demux switches can cause to show
Show that panel charging ability is not enough.Specifically, it is as shown in the table, when the signal of data lead is the data-signal of -5V, demux
The size of switch reduces the negative frame charging ability for not affecting data drive circuit；When the signal of data lead is the data letter of+5V
Number when, demux switch size reduce affect data drive circuit positive frame charging ability.However, the gate source voltage Vgs of NMOS
(voltage i.e. between grid G and source S) is less, causes data drive circuit poor in positive frame charging ability, it is clear that restriction data
The factor of drive circuit size reduction is the positive frame charging ability of data drive circuit.
The present invention provides a kind of data drive circuit of display floater, and the data drive circuit of the display floater includes：Extremely
A few switching circuit；Switching circuit includes two switch, wherein, the output end of first switch is electric with a data line
Connect, input is electrically connected with a data lead and control end is electrically connected with first control line, in first control line
Control under, first switch is opened or closed, and open when by the data signal transmission received from data lead to number
According to line；The output end of second switch is electrically connected with data wire, input is electrically connected with data lead and control end and the
The electrical connection of two control lines, under the control of Article 2 control line, second switch is opened or closed, and will be from when opening
The data signal transmission that data lead is received is to data wire；Data-signal has forward data state and negative sense data mode, when
When data-signal is forward data state, first control first switch of line traffic control opens the line traffic control of Article 2 control simultaneously
Second switch is opened, and when data-signal is negative sense data mode, first control first switch of line traffic control is opened
Second switch of line traffic control of Article 2 control simultaneously is closed.
Here is carried out showing for data drive circuit of the present invention by taking the data drive circuit of the display floater shown in Fig. 2A as an example
Example description, it will be recognized to those skilled in the art that the data drive circuit of the present invention includes but is not limited to Fig. 2A institutes registration
According to drive circuit.As shown in Figure 2 A, the data drive circuit includes that (here is only to be labeled with 111 at least one switching circuit 111
A switching circuit as a example by be described), the switching circuit 111 is electrically connected respectively with data lead S1 and data wire D1.
Each switch of first control line electrical connection is first switch in the present invention, and what Article 2 control line was electrically connected respectively cuts
Parallel operation is second switch, accordingly in fig. 2 correspond to switching circuit 111 first control line be CKH1, Article 2
Control line is CKH2, and first switch is T1, and second switch is T2.
Specifically, when data lead S1 output data-signal be forward data state when, in the switching circuit 111 with
First switch (T1) of first control line CKH1 electrical connection and electrically connect with Article 2 control line CKH2 second cut
Parallel operation (T2) is while opening, that is, ensure that large-sized switching circuit 111 is driven；When the data letter of data lead S1 output
Number for negative sense data mode when, first switch electrically connected with first control line CKH1 in the switching circuit 111
(T1) open second switch for electrically connecting with Article 2 control line CKH2 simultaneously and close (T2), i.e., using small size switching electricity
Road 111 is driven.Obviously the present invention drives the positive frame charging ability for ensureing display floater not receive by large scale switching circuit
Loss, drives the negative frame charging ability for ensureing display floater to also reduce the chi of switching circuit simultaneously by small size switching circuit
It is very little, reach the effect for reducing the power consumption of data drive circuit and then reducing display floater power consumption.
Here is illustrated by following multiple specific examples to the display floater that the present invention is provided, those skilled in the art
It is appreciated that the data drive circuit of display floater includes but is not limited to the example below, the data of any one display floater are driven
The structure of dynamic circuit each falls within protection scope of the present invention.Known NMOS causes data drive circuit poor in positive frame charging ability,
Therefore present invention is particularly suitable for cmos data drive circuit and NMOS data drive circuits, but those skilled in the art can be with
Understand, the present invention is obviously also applied for PMOS data drive circuits, in the following embodiments with cmos data drive circuit and
Illustrate based on NMOS data drive circuits.
The schematic diagram of the data drive circuit of the display floater for providing for one embodiment of the invention as shown in Figure 2 A.As schemed
Shown, the data drive circuit of the display floater includes multiple switching circuit groups 110, each switching circuit group 110 include to
Few six switching circuits 111；One switching circuit group 110 includes, respectively with the first data lead S1, the first SECO line CKH1
With the first data wire D1 electrical connection the first switch T1, respectively with the first data lead S1, the second SECO line CKH2 and
Second switch T2 of the first data wire D1 electrical connections, the first data lead S1 is used to transmit the first data-signal；Respectively with
3rd switch T3 of two data leads S2, the 3rd SECO line CKH3 and the second data wire D2 electrical connection, respectively with second
4th switch T4 of data lead S2, the 4th SECO line CKH4 and the second data wire D2 electrical connection, the second data lead
S2 is used to transmit the second data-signal；Respectively with the first data lead S1, the 5th SECO line CKH5 and the 3rd data wire D3
5th switch T5 of electrical connection, it is electric with the first data lead S1, the 6th SECO line CKH6 and the 3rd data wire D3 respectively
6th switch T6 of connection；It is electrically connected with the second data lead S2, the first SECO line CKH1 and the 4th data wire D4 respectively
The 7th switch T7 for connecing, electrically connects respectively with the second data lead S2, the 7th SECO line CKH7 and the 4th data wire D4
The 8th switch T8；Electrically connect with the first data lead S1, the 3rd SECO line CKH3 and the 5th data wire D5 respectively
9th switch T9, for electrically connecting with the first data lead S1, the 8th SECO line CKH8 and the 5th data wire D5 respectively
Ten switch T10；The tenth for electrically connecting with the second data lead S2, the 5th SECO line CKH5 and the 6th data wire D6 respectively
One switch T11, the tenth for electrically connecting with the second data lead S2, the 9th SECO line CKH9 and the 6th data wire D6 respectively
Two switch T12.
In the present embodiment optional first data wire D1, the second data wire D2, the 3rd data wire D3, the 4th data wire D4,
5th data wire D5 and the 6th data wire D6 correspondence drive sub-pixel be tactic red, green, blue, red, green, blue dice picture
Element.It will be understood by those skilled in the art that the sub-pixel colors order arrangement of display floater can also be red, green, blue, white, red,
It is green, blue, white, the sub-pixel of display floater is not limited in the present invention.
In the present embodiment a data lead drives three data lines, therefore this enforcement in each switching circuit group 110
The data drive circuit that example is provided is 2:6CMOS data drive circuits, it will be understood by those skilled in the art that in other embodiment
In also optional data drive circuit be 1:N cmos data drive circuits, will not be described here.In the present embodiment optional first
Switch T1, the 3rd switch T3, the 5th switch T5, the 7th switch T7, the 9th switch T9 and the 11st switch T11
By a nmos pass transistor composition；Second switch T2, the 4th switch T4, the 6th switch T6, the 8th switch T8,
Ten switch T10 and the 12nd switch T12 are constituted by a PMOS transistor.It will be apparent that each in the present embodiment
First switch of switching circuit 111 is respectively T1, T3, T5, T7, T9 and T11, respectively cuts as shown in Figure 2 A in the present embodiment
Second switch for changing circuit 111 is respectively T2, T4, T6, T8, T10 and T12.It will be understood by those skilled in the art that first
The type of switch T1～the 12nd switch T12 includes but is not limited to above example, and in other embodiments also optional first
Switch T1～the 12nd switch T12 is NMOS or is PMOS3, will not be described here.
The display floater optional in the present embodiment is row upset drive pattern, and specifically, display floater shows former frame
During image, the first data-signal is forward data state, and the second data-signal is negative sense data mode；Display floater shows latter
During two field picture, the first data-signal is negative sense data mode, and the second data-signal is forward data state.Those skilled in the art
It is appreciated that the drive pattern of display floater including but not limited to arranges upset, the display floater that the present invention is provided is applied also for a little
The drive patterns such as upset, row upset and frame upset, will not be described here.
Vgs based on NMOS is less to cause data drive circuit poor in positive frame charging ability, therefore the number of the present embodiment
It is according to the driving principle of drive circuit：Display floater before display a two field picture when, signal polarity for positive polarity the first data
Two switch of each switching circuit 111 corresponding to lead S1 are opened simultaneously, it is ensured that large-sized switching circuit 111 is entered
Row drives；And first of each switching circuit 111 of the signal polarity corresponding to the second data lead S2 of negative polarity cuts
Parallel operation is opened, and is driven using small size switching circuit 111.
Display floater after the display a two field picture when, signal polarity for negative polarity the first data lead S1 corresponding to it is every
First switch of individual switching circuit 111 is opened, and is driven using small size switching circuit 111；Signal polarity is positive pole
Property the second data lead S2 corresponding to two switch of each switching circuit 111 open simultaneously, it is ensured that it is large-sized
Switching circuit 111 is driven.Therefore in the present embodiment, data drive circuit is driven by large scale switching circuit 111 and is ensured
The positive frame charging ability of display floater is not lost；And the negative of guarantee display floater is driven by small size switching circuit 111
Frame charging ability also reduces the size of switching circuit to reduce the power consumption of data drive circuit and then reduce showing simultaneously
The effect of panel power consumption.
It will be apparent that so that m two field pictures and m+1 two field pictures show as an example, as shown in Figure 2 B the present embodiment is provided
The driver' s timing of data drive circuit is：M two field pictures are shown, when the first data-signal is forward data state and the second data
When signal is negative sense data mode, the first SECO line CKH1 controls the first switch T1 and opens, the second SECO line
CKH2 controls the second switch T2 and opens, so that the first data signal transmission to the first data wire D1, i.e., switched by large scale
Circuit 111 drives the positive frame charging ability for ensureing display floater not to be lost；Meanwhile, the first SECO line CKH1 controls the 7th
Switch T7 is opened, and the 7th SECO line CKH7 controls the 8th switch T8 and closes, so that the second data signal transmission is to the
Four data wire D4, i.e., drive to reduce the effect of display floater power consumption by small size switching circuit 111.Known first cuts
Parallel operation T1 and the 7th switch T7 are NMOS, and the second switch T2 and the 8th switch T8 are PMOS, so the first sequential
Control line CKH1 exports high level signal, the second SECO line CKH2 output low level signals, the 7th SECO line CKH7
Output high level signal.
3rd SECO line CKH3 controls the 3rd switch T3 and opens, and the 4th SECO line CKH4 controls the 4th switch
Device T4 is closed, so that the second data signal transmission drives to reach to the second data wire D2 by small size switching circuit 111
Reduce the effect of display floater power consumption；Meanwhile, the 3rd SECO line CKH3 controls the 9th switch T9 and opens, the 8th sequential control
Line CKH8 processed controls the tenth switch T10 and opens, so that the first data signal transmission is to the 5th data wire D5, i.e., by large scale
Switching circuit 111 drives the positive frame charging ability for ensureing display floater not to be lost.The switchings of known 3rd switch T3 and the 9th
Device T9 is NMOS, and the 4th switch T4 and the tenth switch T10 are PMOS, so the 3rd SECO line CKH3 outputs are high
Level signal, the 4th SECO line CKH4 output high level signals, the 8th SECO line CKH8 output low level signals.
5th SECO line CKH5 controls the 5th switch T5 and opens, and the 6th SECO line CKH6 controls the 6th switch
Device T6 is opened, so that the first data signal transmission to the 3rd data wire D3, i.e., driven by large scale switching circuit 111 and ensure aobvious
The positive frame charging ability for showing panel is not lost；Meanwhile, the 5th SECO line CKH5 controls the 11st switch T11 and opens,
9th SECO line CKH9 controls the 12nd switch T12 and closes, so that the second data signal transmission is to the 6th data wire D6,
Drive to reduce the effect of display floater power consumption by small size switching circuit 111.Known 5th switch T5 and
11 switch T11 are NMOS, and the 6th switch T6 and the 12nd switch T12 are PMOS, so the 5th SECO
Line CKH5 exports high level signal, the 6th SECO line CKH6 output low level signals, the 9th SECO line CKH9 outputs
High level signal.
As shown in Figure 2 B, m+1 two field pictures are shown, when the first data-signal is negative sense data mode and the second data-signal
For forward data state when, the first SECO line CKH1 control the first switch T1 open, the second SECO line CKH2 control
The second switch T2 closings are made, so that the first data signal transmission is to the first data wire D1, i.e., by small size switching circuit 111
Drive to reduce the effect of display floater power consumption；Meanwhile, the first SECO line CKH1 controls the 7th switch T7 and opens,
7th SECO line CKH7 controls the 8th switch T8 and opens, so that the second data signal transmission to the 4th data wire D4, i.e.,
The positive frame charging ability for ensureing display floater is driven not to be lost by large scale switching circuit 111.Known first switch T1
NMOS is with the 7th switch T7, the second switch T2 and the 8th switch T8 are PMOS, so the first SECO line
CKH1 exports high level signal, and the second SECO line CKH2 output high level signals, the 7th SECO line CKH7 outputs are low
Level signal.
3rd SECO line CKH3 controls the 3rd switch T3 and opens, and the 4th SECO line CKH4 controls the 4th switch
Device T4 is opened, so that the second data signal transmission to the second data wire D2, i.e., driven by large scale switching circuit 111 and ensure aobvious
The positive frame charging ability for showing panel is not lost；Meanwhile, the 3rd SECO line CKH3 controls the 9th switch T9 and opens, and the 8th
SECO line CKH8 controls the tenth switch T10 and closes, so that the first data signal transmission passes through to the 5th data wire D5
Small size switching circuit 111 drives to reduce the effect of display floater power consumption.The switchings of known 3rd switch T3 and the 9th
Device T9 is NMOS, and the 4th switch T4 and the tenth switch T10 are PMOS, so the 3rd SECO line CKH3 outputs are high
Level signal, the 4th SECO line CKH4 output low level signals, the 8th SECO line CKH8 output high level signals.
5th SECO line CKH5 controls the 5th switch T5 and opens, and the 6th SECO line CKH6 controls the 6th switch
Device T6 is closed, so that the first data signal transmission to the 3rd data wire D3, i.e., drive to reach by small size switching circuit 111
Reduce the effect of display floater power consumption；Meanwhile, the 5th SECO line CKH5 controls the 11st switch T11 and opens, when the 9th
Sequence control line CKH9 controls the 12nd switch T12 and opens, so that the second data signal transmission passes through to the 6th data wire D6
Large scale switching circuit 111 drives the positive frame charging ability for ensureing display floater not to be lost.Known 5th switch T5 and
11 switch T11 are NMOS, and the 6th switch T6 and the 12nd switch T12 are PMOS, so the 5th SECO
Line CKH5 exports high level signal, the 6th SECO line CKH6 output high level signals, the 9th SECO line CKH9 outputs
Low level signal.
The schematic diagram of the data drive circuit of the display floater for providing for another embodiment of the present invention as shown in Figure 3A.With
The difference of data drive circuit shown in Fig. 2A is that in the data drive circuit of the display floater that the present embodiment is provided, first cuts
Parallel operation T1, the second switch T2, the 3rd switch T3, the 4th switch T4, the 5th switch T5, the 6th switch T6, the 7th
Switch T7, the 8th switch T8, the 9th switch T9, the tenth switch T10, the switchings of the 11st switch T11 and the 12nd
Device T12 is constituted by a nmos pass transistor.It will be apparent that first switching of each switching circuit 111 in the present embodiment
Device is respectively T1, T3, T5, T7, T9 and T11, in the present embodiment second switch of each switching circuit 111 as shown in Figure 3A
Respectively T2, T4, T6, T8, T10 and T12.
The driver' s timing of the obvious data drive circuit is as shown in Figure 3 B.M two field pictures are shown, when the first data-signal is
When forward data state and the second data-signal are negative sense data mode, the first SECO line CKH1 output high level signals,
Second SECO line CKH2 exports high level signal, the 7th SECO line CKH7 output low level signals.3rd sequential control
Line CKH3 processed exports high level signal, and the 4th SECO line CKH4 output low level signals, the 8th SECO line CKH8 is defeated
Go out high level signal.5th SECO line CKH5 exports high level signal, the 6th SECO line CKH6 output high level letters
Number, the 9th SECO line CKH9 output low level signals.Drive from there through large scale switching circuit 111 and ensure display floater
Positive frame charging ability be not lost, and drive to reduce display floater power consumption by small size switching circuit 111
Effect.
M+1 two field pictures are shown, when the first data-signal is that negative sense data mode and the second data-signal are forward data
During state, the first SECO line CKH1 output high level signals, the second SECO line CKH2 output low level signals, the 7th
SECO line CKH7 exports high level signal.3rd SECO line CKH3 exports high level signal, the 4th SECO line
CKH4 exports high level signal, the 8th SECO line CKH8 output low level signals.5th SECO line CKH5 outputs are high
Level signal, the 6th SECO line CKH6 output low level signals, the 9th SECO line CKH9 output high level signals.By
This drives the positive frame charging ability for ensureing display floater not to be lost by large scale switching circuit 111, and by small size
Switching circuit 111 drives to reduce the effect of display floater power consumption.
The schematic diagram of the data drive circuit of the display floater for providing for further embodiment of the present invention as shown in Figure 4 A.Such as
Shown in figure, the data drive circuit of the display floater includes multiple switching circuit groups 110, and each switching circuit group 110 includes
At least four switching circuits 111；One switching circuit group 110 includes, respectively with the first data lead S1, the first SECO line
First switch T1 of CKH1 and the first data wire D1 electrical connections, respectively with the first data lead S1, the second SECO line
Second switch T2 of CKH2 and the first data wire D1 electrical connections, the first data lead S1 is used to transmit the first data-signal；Point
The 3rd switch T3 not electrically connected with the second data lead S2, the 3rd SECO line CKH3 and the second data wire D2, respectively
The 4th switch T4 electrically connected with the second data lead S2, the 4th SECO line CKH4 and the second data wire D2, the second number
It is used to transmit the second data-signal according to lead S2；Respectively with the first data lead S1, the numbers of the 3rd SECO line CKH3 and the 3rd
According to the 5th switch T5 that line D3 is electrically connected, respectively with the first data lead S1, the 5th SECO line CKH5 and the 3rd data
6th switch T6 of line D3 electrical connections；Respectively with the second data lead S2, the first SECO line CKH1 and the 4th data wire
7th switch T7 of D4 electrical connections, respectively with the second data lead S2, the 6th SECO line CKH6 and the 4th data wire D4
8th switch T8 of electrical connection.
Optional first data wire D1, the second data wire D2, the 3rd data wire D3 and the 4th data wire D4 in the present embodiment
The sub-pixel that correspondence drives is tactic red, green, blue and white sub-pixels.It will be understood by those skilled in the art that showing
The sub-pixel colors order arrangement of panel can also be red, green, blue, and red, green, blue does not limit in the present invention display floater
Sub-pixel.For example, also optional first data wire, the second data wire, the 3rd data wire and the 4th in other embodiments of the present invention
The sub-pixel that data wire correspondence drives is tactic red, green, blue and yellow sub-pixel.
In the present embodiment a data lead drives two data lines, therefore this enforcement in each switching circuit group 110
The data drive circuit that example is provided is 2:4CMOS data drive circuits, it will be understood by those skilled in the art that in other embodiment
In also optional data drive circuit be 1:N cmos data drive circuits, will not be described here.In the present embodiment optional first
Switch T1, the 3rd switch T3, the 5th switch T5 and the 7th switch T7 are constituted by a nmos pass transistor；Second cuts
Parallel operation T2, the 4th switch T4, the 6th switch T6 and the 8th switch T8 are constituted by a PMOS transistor.Obviously
, in the present embodiment first switch of each switching circuit 111 is respectively T1, T3, T5 and T7, in the present embodiment as schemed
Second switch of each switching circuit 111 shown in 4A is respectively T2, T4, T6 and T8.It will be understood by those skilled in the art that the
The type of one switch T1～the 8th switch T8 includes but is not limited to above example, also optional first cuts in other embodiments
Parallel operation T1～the 8th switch T8 is NMOS or is PMOS3, will not be described here.
The display floater optional in the present embodiment is row upset drive pattern, and specifically, display floater shows former frame
During image, the first data-signal is forward data state, and the second data-signal is negative sense data mode；Display floater shows latter
During two field picture, the first data-signal is negative sense data mode, and the second data-signal is forward data state.Those skilled in the art
It is appreciated that the drive pattern of display floater including but not limited to arranges upset, the display floater that the present invention is provided is applied also for a little
The drive patterns such as upset, row upset and frame upset, will not be described here.
Vgs based on NMOS is less to cause data drive circuit poor in positive frame charging ability, therefore the number of the present embodiment
It is according to the driving principle of drive circuit：Display floater before display a two field picture when, signal polarity for positive polarity the first data
Two switch of each switching circuit 111 corresponding to lead S1 are opened simultaneously, it is ensured that large-sized switching circuit 111 is entered
Row drives；And first of each switching circuit 111 of the signal polarity corresponding to the second data lead S2 of negative polarity cuts
Parallel operation is opened, and is driven using small size switching circuit 111.
Display floater after the display a two field picture when, signal polarity for negative polarity the first data lead S1 corresponding to it is every
First switch of individual switching circuit 111 is opened, and is driven using small size switching circuit 111；Signal polarity is positive pole
Property the second data lead S2 corresponding to two switch of each switching circuit 111 open simultaneously, it is ensured that it is large-sized
Switching circuit 111 is driven.Therefore in the present embodiment, data drive circuit is driven by large scale switching circuit 111 and is ensured
The positive frame charging ability of display floater is not lost；And the negative of guarantee display floater is driven by small size switching circuit 111
Frame charging ability also reduces the size of switching circuit to reduce the power consumption of data drive circuit and then reduce showing simultaneously
The effect of panel power consumption.
It will be apparent that so that m two field pictures and m+1 two field pictures show as an example, as shown in Figure 4 B the present embodiment is provided
The driver' s timing of data drive circuit is：M two field pictures are shown, when the first data-signal is forward data state and the second data
When signal is negative sense data mode, the first SECO line CKH1 controls the first switch T1 and opens, the second SECO line
CKH2 controls the second switch T2 and opens, so that the first data signal transmission to the first data wire D1, i.e., switched by large scale
Circuit 111 drives the positive frame charging ability for ensureing display floater not to be lost；Meanwhile, the first SECO line CKH1 controls the 7th
Switch T7 is opened, and the 6th SECO line CKH6 controls the 8th switch T8 and closes, so that the second data signal transmission is to the
Four data wire D4, i.e., drive to reduce the effect of display floater power consumption by small size switching circuit 111.Known first cuts
Parallel operation T1 and the 7th switch T7 are NMOS, and the second switch T2 and the 8th switch T8 are PMOS, so the first sequential
Control line CKH1 exports high level signal, the second SECO line CKH2 output low level signals, the 6th SECO line CKH6
Output high level signal.
3rd SECO line CKH3 controls the 3rd switch T3 and opens, and the 4th SECO line CKH4 controls the 4th switch
Device T4 is closed, so that the second data signal transmission drives to reach to the second data wire D2 by small size switching circuit 111
Reduce the effect of display floater power consumption；Meanwhile, the 3rd SECO line CKH3 controls the 5th switch T5 and opens, the 5th sequential control
Line CKH5 processed controls the 6th switch T6 and opens, so that the first data signal transmission is to the 3rd data wire D3, i.e., by large scale
Switching circuit 111 drives the positive frame charging ability for ensureing display floater not to be lost.The switchings of known 3rd switch T3 and the 5th
Device T5 is NMOS, and the 4th switch T4 and the 6th switch T6 are PMOS, so the 3rd SECO line CKH3 outputs are high
Level signal, the 4th SECO line CKH4 output high level signals, the 5th SECO line CKH5 output low level signals.
As shown in Figure 4 B, m+1 two field pictures are shown, when the first data-signal is negative sense data mode and the second data-signal
For forward data state when, the first SECO line CKH1 control the first switch T1 open, the second SECO line CKH2 control
The second switch T2 closings are made, so that the first data signal transmission is to the first data wire D1, i.e., by small size switching circuit 111
Drive to reduce the effect of display floater power consumption；Meanwhile, the first SECO line CKH1 controls the 7th switch T7 and opens,
6th SECO line CKH6 controls the 8th switch T8 and opens, so that the second data signal transmission to the 4th data wire D4, i.e.,
The positive frame charging ability for ensureing display floater is driven not to be lost by large scale switching circuit 111.Known first switch T1
NMOS is with the 7th switch T7, the second switch T2 and the 8th switch T8 are PMOS, so the first SECO line
CKH1 exports high level signal, and the second SECO line CKH2 output high level signals, the 6th SECO line CKH6 outputs are low
Level signal.
3rd SECO line CKH3 controls the 3rd switch T3 and opens, and the 4th SECO line CKH4 controls the 4th switch
Device T4 is opened, so that the second data signal transmission to the second data wire D2, i.e., driven by large scale switching circuit 111 and ensure aobvious
The positive frame charging ability for showing panel is not lost；Meanwhile, the 3rd SECO line CKH3 controls the 5th switch T5 and opens, and the 5th
SECO line CKH5 controls the 6th switch T6 and closes, so that the first data signal transmission passes through to the 3rd data wire D3
Small size switching circuit 111 drives to reduce the effect of display floater power consumption.The switchings of known 3rd switch T3 and the 5th
Device T5 is NMOS, and the 4th switch T4 and the 6th switch T6 are PMOS, so the 3rd SECO line CKH3 outputs are high
Level signal, the 4th SECO line CKH4 output low level signals, the 5th SECO line CKH5 output high level signals.
The schematic diagram of the data drive circuit of the display floater for providing for another embodiment of the invention as shown in Figure 5A.With
The difference of data drive circuit shown in Fig. 4 A is that in the data drive circuit of the display floater that the present embodiment is provided, first cuts
Parallel operation T1, the second switch T2, the 3rd switch T3, the 4th switch T4, the 5th switch T5, the 6th switch T6, the 7th
Switch T7 and the 8th switch T8 are constituted by a nmos pass transistor.It will be apparent that in the present embodiment each switching is electric
First switch on road 111 is respectively T1, T3, T5 and T7, in the present embodiment the of each switching circuit 111 as shown in Figure 2 A
Two switch are respectively T2, T4, T6 and T8.
The driver' s timing of the obvious data drive circuit is as shown in Figure 5 B.M two field pictures are shown, when the first data-signal is
When forward data state and the second data-signal are negative sense data mode, the first SECO line CKH1 output high level signals,
Second SECO line CKH2 exports high level signal, the 6th SECO line CKH6 output low level signals.3rd sequential control
Line CKH3 processed exports high level signal, and the 4th SECO line CKH4 output low level signals, the 5th SECO line CKH5 is defeated
Go out high level signal.The positive frame charging ability for ensureing display floater is driven not to be lost from there through large scale switching circuit 111,
And drive to reduce the effect of display floater power consumption by small size switching circuit 111.
M+1 two field pictures are shown, when the first data-signal is that negative sense data mode and the second data-signal are forward data
During state, the first SECO line CKH1 output high level signals, the second SECO line CKH2 output low level signals, the 6th
SECO line CKH6 exports high level signal.3rd SECO line CKH3 exports high level signal, the 4th SECO line
CKH4 exports high level signal, the 5th SECO line CKH5 output low level signals.From there through large scale switching circuit 111
Drive the positive frame charging ability for ensureing display floater not to be lost, and drive to reach drop by small size switching circuit 111
The effect of low display floater power consumption.
On the basis of above-mentioned any embodiment, the embodiment of the present invention also provides a kind of display floater, the display floater bag
Include the data drive circuit described in driving chip and as above any embodiment.The number of specific driving chip and data drive circuit
Electrically connect according to lead, first control line and Article 2 control line, for applying data-signal to data lead, to first control
Line processed applies the first timing control signal, and applies second timing control signal to Article 2 control line, wherein, data
Signal has forward data state and negative sense data mode.
When driving chip applies the data-signal of forward data state to data lead, driving chip is to first control line
Apply the timing control signal of first switch opening of control while driving chip applies control second to Article 2 control line
The data signal transmission that the timing control signal that individual switch is opened, first switch and second switch will be received simultaneously
To the data wire of electrical connection；When driving chip applies the data-signal of negative sense data mode to data lead, driving chip is to the
One control line applies the timing control signal that first switch of control is opened, the data-signal that first switch will be received
Transmit to the data wire of electrical connection.
Here carries out the accompanying drawing example of display floater by taking data drive circuit shown in Fig. 2A as an example, the display as shown in Figure 6
Panel includes driving chip 200 and data drive circuit 100 as shown in Figure 2 A.The specific control data of driving chip 200 is driven
The process of dynamic circuit 100 is described in detail in the above-described embodiments, be will not be described here.
The display floater that the present embodiment is provided, in data drive circuit, when data-signal is forward data state, each
First switch and second switch in switching circuit is opened simultaneously, it is ensured that large-sized switching circuit is driven
It is dynamic；When data-signal is negative sense data mode, first in each switching circuit switch opens second switching simultaneously
Device is closed, and is driven using small size switching circuit.Obviously the display floater is driven by large scale switching circuit and ensures aobvious
The positive frame charging ability for showing panel is not lost, and the negative frame charging ability for ensureing display floater is driven by small size switching circuit
The size of switching circuit is also reduced simultaneously, it is clear that, compared with prior art, data drive circuit is reduced at least
25% power consumption, having reached reduces the effect of display floater power consumption.
The embodiment of the present invention also provides a kind of display device, and the display device includes display floater as above.At this
The optional display device is the display devices such as smart mobile phone in embodiment.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention is carried out by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
More other Equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (18)
1. a kind of data drive circuit of display floater, it is characterised in that include：At least one switching circuit；
The switching circuit includes two switch, wherein,
The output end of first switch is electrically connected with a data line, input is electrically connected and controlled with a data lead
End processed electrically connects with first control line, and under the control of first control line, first switch is beaten and opened or closed
Close, and open when by the data signal transmission received from the data lead to the data wire；
The output end of second switch is electrically connected with the data wire, input is electrically connected and controlled with the data lead
End processed electrically connects with Article 2 control line, and under the control of the Article 2 control line, second switch is beaten and opened or closed
Close, and open when by the data signal transmission received from the data lead to the data wire；
The data-signal has forward data state and negative sense data mode, when the data-signal is forward data state
When, first switch described in the first control line traffic control is opened second described in the Article 2 control line traffic control simultaneously
Switch is opened, when the data-signal is negative sense data mode, first switching described in the first control line traffic control
Device is opened second switch described in the Article 2 control line traffic control simultaneously and is closed.
2. data drive circuit according to claim 1, it is characterised in that the data drive circuit includes multiple switchings
Circuit group, each described switching circuit group includes switching circuit described at least six；
Switching circuit group includes described in one,
The first switch for electrically connecting with the first data lead, the first SECO line and the first data wire respectively, respectively with institute
State the second switch of the first data lead, the second SECO line and first data wire electrical connection, first data
Lead is used to transmit the first data-signal；
The 3rd switch for electrically connecting with the second data lead, the 3rd SECO line and the second data wire respectively, respectively with institute
State the 4th switch of the second data lead, the 4th SECO line and second data wire electrical connection, second data
Lead is used to transmit the second data-signal；
The 5th switch for electrically connecting with first data lead, the 5th SECO line and the 3rd data wire respectively, respectively
The 6th switch electrically connected with first data lead, the 6th SECO line and the 3rd data wire；
The 7th switch for electrically connecting with second data lead, the first SECO line and the 4th data wire respectively,
The 8th switch for electrically connecting with second data lead, the 7th SECO line and the 4th data wire respectively；
The 9th switch for electrically connecting with first data lead, the 3rd SECO line and the 5th data wire respectively,
The tenth switch for electrically connecting with first data lead, the 8th SECO line and the 5th data wire respectively；
The 11st switching for electrically connecting with second data lead, the 5th SECO line and the 6th data wire respectively
Device, the 12nd switch for electrically connecting with second data lead, the 9th SECO line and the 6th data wire respectively.
3. data drive circuit according to claim 2, it is characterised in that
When the display floater shows previous frame image, first data-signal is forward data state, second data
Signal is negative sense data mode；
When the display floater shows latter two field picture, first data-signal be negative sense data mode, second data
Signal is forward data state.
4. data drive circuit according to claim 3, it is characterised in that first switch, the 3rd switching
Device, the 5th switch, the 7th switch, the 9th switch and the 11st switch are by a NMOS
Transistor is constituted；
Second switch, the 4th switch, the 6th switch, the 8th switch, the tenth switching
Device and the 12nd switch are constituted by a PMOS transistor.
5. data drive circuit according to claim 3, it is characterised in that first switch, second switching
Device, the 3rd switch, the 4th switch, the 5th switch, the 6th switch, the 7th switching
Device, the 8th switch, the 9th switch, the tenth switch, the 11st switch and the described 12nd
Switch is constituted by a nmos pass transistor.
6. the data drive circuit according to claim 4 or 5, it is characterised in that when first data-signal is forward direction
When data mode and second data-signal are negative sense data mode,
First switch described in the first SECO line traffic control is opened, and second cuts described in the second SECO line traffic control
Parallel operation is opened, so that first data signal transmission is to first data wire；Meanwhile, the first SECO line traffic control
7th switch is opened, and the 8th switch described in the 7th SECO line traffic control is closed, so that second data
Signal transmission is to the 4th data wire；
3rd switch described in the 3rd SECO line traffic control is opened, and the 4th cuts described in the 4th SECO line traffic control
Parallel operation is closed, so that second data signal transmission is to second data wire；Meanwhile, the 3rd SECO line traffic control
9th switch is opened, and the tenth switch described in the 8th SECO line traffic control is opened, so that first data
Signal transmission is to the 5th data wire；
5th switch described in the 5th SECO line traffic control is opened, and the 6th cuts described in the 6th SECO line traffic control
Parallel operation is opened, so that first data signal transmission is to the 3rd data wire；Meanwhile, the 5th SECO line traffic control
11st switch is opened, and the 12nd switch described in the 9th SECO line traffic control is closed, so that described second
Data signal transmission is to the 6th data wire.
7. the data drive circuit according to claim 4 or 5, it is characterised in that when first data-signal is negative sense
When data mode and second data-signal are forward data state,
First switch described in the first SECO line traffic control is opened, and second cuts described in the second SECO line traffic control
Parallel operation is closed, so that first data signal transmission is to first data wire；Meanwhile, the first SECO line traffic control
7th switch is opened, and the 8th switch described in the 7th SECO line traffic control is opened, so that second data
Signal transmission is to the 4th data wire；
3rd switch described in the 3rd SECO line traffic control is opened, and the 4th cuts described in the 4th SECO line traffic control
Parallel operation is opened, so that second data signal transmission is to second data wire；Meanwhile, the 3rd SECO line traffic control
9th switch is opened, and the tenth switch described in the 8th SECO line traffic control is closed, so that first data
Signal transmission is to the 5th data wire；
5th switch described in the 5th SECO line traffic control is opened, and the 6th cuts described in the 6th SECO line traffic control
Parallel operation is closed, so that first data signal transmission is to the 3rd data wire；Meanwhile, the 5th SECO line traffic control
11st switch is opened, and the 12nd switch described in the 9th SECO line traffic control is opened, so that described second
Data signal transmission is to the 6th data wire.
8. data drive circuit according to claim 2, it is characterised in that first data wire, second data
Line, the 3rd data wire, the 4th data wire, the sub- picture of the 5th data wire driving corresponding with the 6th data wire
Element be tactic red, green, blue, red, green, blue sub-pixels.
9. data drive circuit according to claim 1, it is characterised in that the data drive circuit includes multiple switchings
Circuit group, each described switching circuit group includes switching circuit described at least four；
Switching circuit group includes described in one,
The first switch for electrically connecting with the first data lead, the first SECO line and the first data wire respectively, respectively with institute
State the second switch of the first data lead, the second SECO line and first data wire electrical connection, first data
Lead is used to transmit the first data-signal；
The 3rd switch for electrically connecting with the second data lead, the 3rd SECO line and the second data wire respectively, respectively with institute
State the 4th switch of the second data lead, the 4th SECO line and second data wire electrical connection, second data
Lead is used to transmit the second data-signal；
The 5th switch for electrically connecting with first data lead, the 3rd SECO line and the 3rd data wire respectively,
The 6th switch for electrically connecting with first data lead, the 5th SECO line and the 3rd data wire respectively；
The 7th switch for electrically connecting with second data lead, the first SECO line and the 4th data wire respectively,
The 8th switch for electrically connecting with second data lead, the 6th SECO line and the 4th data wire respectively.
10. data drive circuit according to claim 9, it is characterised in that
When the display floater shows previous frame image, first data-signal is forward data state, second data
Signal is negative sense data mode；
When the display floater shows latter two field picture, first data-signal be negative sense data mode, second data
Signal is forward data state.
11. data drive circuits according to claim 10, it is characterised in that first switch, the described 3rd cut
Parallel operation, the 5th switch and the 7th switch are constituted by a nmos pass transistor；
Second switch, the 4th switch, the 6th switch and the 8th switch are by a PMOS
Transistor is constituted.
12. data drive circuits according to claim 10, it is characterised in that first switch, described second cut
Parallel operation, the 3rd switch, the 4th switch, the 5th switch, the 6th switch, the 7th switching
Device and the 8th switch are constituted by a nmos pass transistor.
13. data drive circuits according to claim 11 or 12, it is characterised in that when first data-signal is for just
When to data mode and second data-signal being negative sense data mode,
First switch described in the first SECO line traffic control is opened, and second cuts described in the second SECO line traffic control
Parallel operation is opened, so that first data signal transmission is to first data wire；Meanwhile, the first SECO line traffic control
7th switch is opened, and the 8th switch described in the 6th SECO line traffic control is closed, so that second data
Signal transmission is to the 4th data wire；
3rd switch described in the 3rd SECO line traffic control is opened, and the 4th cuts described in the 4th SECO line traffic control
Parallel operation is closed, so that second data signal transmission is to second data wire；Meanwhile, the 3rd SECO line traffic control
5th switch is opened, and the 6th switch described in the 5th SECO line traffic control is opened, so that first data
Signal transmission is to the 3rd data wire.
14. data drive circuits according to claim 11 or 12, it is characterised in that when first data-signal is negative
When to data mode and second data-signal being forward data state,
First switch described in the first SECO line traffic control is opened, and second cuts described in the second SECO line traffic control
Parallel operation is closed, so that first data signal transmission is to first data wire；Meanwhile, the first SECO line traffic control
7th switch is opened, and the 8th switch described in the 6th SECO line traffic control is opened, so that second data
Signal transmission is to the 4th data wire；
3rd switch described in the 3rd SECO line traffic control is opened, and the 4th cuts described in the 4th SECO line traffic control
Parallel operation is opened, so that second data signal transmission is to second data wire；Meanwhile, the 3rd SECO line traffic control
5th switch is opened, and the 6th switch described in the 5th SECO line traffic control is closed, so that first data
Signal transmission is to the 3rd data wire.
15. data drive circuits according to claim 9, it is characterised in that first data wire, second data
Line, the sub-pixel of the 3rd data wire driving corresponding with the 4th data wire are tactic red, green, blue and white
Pixel；Or,
First data wire, second data wire, the son of the 3rd data wire driving corresponding with the 4th data wire
Pixel is tactic red, green, blue and yellow sub-pixel.
16. a kind of display floaters, it is characterised in that drive including driving chip and the data as described in any one of claim 1-15
Dynamic circuit.
17. display floaters according to claim 16, it is characterised in that
The data lead of the driving chip and the data drive circuit, first control line and Article 2 control line are electrically connected
Connect, for applying data-signal to the data lead, to first control line the first timing control signal is applied, with
And apply second timing control signal to the Article 2 control line, wherein, the data-signal has forward data state
With negative sense data mode；
When the driving chip applies the data-signal of forward data state to the data lead, the driving chip is to described
First control line apply timing control signal that control first switch open simultaneously the driving chip to described
Article 2 control line applies the timing control signal that control second switch is opened, first switch and described
Second switch is simultaneously by the data signal transmission for receiving to the data wire for electrically connecting；
When the driving chip applies the data-signal of negative sense data mode to the data lead, the driving chip is to described
First control line applies the timing control signal that control first switch is opened, and first switch will be received
The data signal transmission to electrically connect the data wire.
18. a kind of display devices, it is characterised in that include the display floater as described in any one of claim 16-17.
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| CN201610910235.3A CN106652930B (en) | 2016-10-19 | 2016-10-19 | Display panel and its data drive circuit and display device |
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| CN201610910235.3A CN106652930B (en) | 2016-10-19 | 2016-10-19 | Display panel and its data drive circuit and display device |
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| WO2019227649A1 (en) * | 2018-05-31 | 2019-12-05 | 武汉华星光电技术有限公司 | Pixel substrate, liquid crystal display panel, and liquid crystal display device |
| US10777157B2 (en) | 2018-05-31 | 2020-09-15 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel having pixel units with difference storage capacitance |
| TWI788578B (en) * | 2018-06-25 | 2023-01-01 | 矽創電子股份有限公司 | Driving method and circuit using the same |
| CN115064134A (en) * | 2022-07-04 | 2022-09-16 | 福建华佳彩有限公司 | Demux circuit for improving charging rate of panel positive frame and driving method thereof |
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