CN106601644B - The method that a kind of pair of flash cell shrinks verifying - Google Patents
The method that a kind of pair of flash cell shrinks verifying Download PDFInfo
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- CN106601644B CN106601644B CN201611110711.XA CN201611110711A CN106601644B CN 106601644 B CN106601644 B CN 106601644B CN 201611110711 A CN201611110711 A CN 201611110711A CN 106601644 B CN106601644 B CN 106601644B
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- flash cell
- storage array
- verifying
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- new storage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Abstract
The present invention provides a kind of pair of flash cells to shrink verification method, applied in chip layout to the shrink process of flash cell, chip layout includes multiple former storage arrays of multiple former flash cell compositions, it is characterized in that, the following steps are included: the new flash cell of step S1, one shrink process of setting, and new flash cell is replaced into the former flash cell on chip layout, to form multiple new storage arrays；Step S2, it provides one group of predetermined device to be filled the predetermined face product moment formed between each former storage array and corresponding each new storage array, to form a predetermined dimension chip layout；Step S3, corresponding chip is prepared according to predetermined dimension chip layout.The beneficial effect of its technical solution is, flash cell after former flash cell shrink process in former chip layout is verified, the difference in areas formed between former storage array and new storage array is filled, using virtual component to realize the integrated testability to new storage array.
Description
Technical field
The present invention relates to the methods that technical field of manufacturing semiconductors more particularly to a kind of pair of flash cell shrink verifying.
Background technique
With the expansion of flash chip capacity, needs to be placed in more flash cells in unit area, change for this
Change generally requires to carry out dimensional contraction to original flash cell, and new storage battle array is formed using the flash cell after contraction
Column, since new storage array must be verified into crossing, if only flash cell can only be obtained by verifying to storage array
Performance, overall performance data when can not obtain storage array as in chip redesign core if it is new storage array
Although the overall performance of newly-designed storage permutation place chip can be obtained by carrying out flow verifying after piece, when expending a large amount of
Between and cost.
Summary of the invention
The existing above problem is verified for the flash cell in the prior art to different size, one kind is now provided and is intended to reality
Now in being shunk on same chip domain to flash cell, and the storage array that the flash cell after contraction is constituted is carried out
The method that verifying is shunk to flash cell of verifying.
Specific technical solution is as follows:
The method that a kind of pair of flash cell shrinks verifying, applied in chip layout to the shrink process of flash cell, institute
State multiple former storage arrays that chip layout includes multiple former flash cell compositions, wherein
The following steps are included:
Step S1, the new flash cell of a shrink process is set, and the new flash cell is replaced into the chip layout
On the former flash cell, to form multiple new storage arrays；
Step S2, one group of predetermined device is provided to each former storage array and corresponding each new storage array
Between the predetermined face product moment that is formed be filled, to form a predetermined dimension chip layout；
Step S3, corresponding chip is prepared according to the predetermined dimension chip layout.
Preferably, the predetermined device is virtual component.
Preferably, the virtual component is filled in the surrounding of the new storage array respectively.
Preferably, the widthwise edges of each new storage array are provided with source interval；
The virtual component of the new storage array width edge is set between the adjacent source interval.
Preferably, the length edge of each new storage array is provided with the virtual group equal with length sides
Part.
Preferably, source diffusion layer is provided between every neighbouring new storage array.
Preferably, the adjustable setting of the width of the source diffusion layer.
Preferably, word line spacer layer is provided between the adjacent new storage array in every left and right.
Above-mentioned technical proposal has the following advantages that or the utility model has the advantages that the former flash cell shrink process in former chip layout
Flash cell afterwards is verified, and the difference in areas formed between former storage array and new storage array is filled using predetermined device,
To realize the integrated testability to new storage array.
Detailed description of the invention
With reference to appended attached drawing, more fully to describe the embodiment of the present invention.However, appended attached drawing be merely to illustrate and
It illustrates, and is not meant to limit the scope of the invention.
Fig. 1 is the flow chart for the embodiment of the method that a kind of pair of flash cell of the present invention shrinks verifying.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
It include the method that a kind of pair of flash cell shrinks verifying in technical solution of the present invention.
A kind of pair of flash cell shrinks the embodiment of the method for verifying, applied to chip layout middle part to the receipts of flash cell
Contracting processing, chip layout include multiple former storage arrays of multiple former flash cell compositions, wherein as shown in Figure 1, including following
Step:
Step S1, the new flash cell of a shrink process is set, and new flash cell is replaced to the former sudden strain of a muscle on chip layout
Memory cell, to form multiple new storage arrays；
Step S2, one group of predetermined device is provided to be formed between each former storage array and corresponding each new storage array
Predetermined face product moment be filled, to form a predetermined dimension chip layout；
Step S3, corresponding chip is prepared according to predetermined dimension chip layout.
In order to test chip overall performance in existing chip layout, need to test the flash cell that it is arranged
Card, and the test of overall performance is completed, but for the flash cell of different size, storage array is needed to reset, with
Realize verifying to flash cell, but singly do storage array and cannot achieve and whole chip layout is tested, if you need into
Row integrated testability verifying, then need to rebuild chip layout and solve the above problems, but rebuild chip layout cost compared with
Height, by the former flash cell in the new flash cell replacement chip layout of definition, leads to by former chip layout in the present invention
The specification that new flash cell is redefined on former chip layout is crossed, new flash cell is less than former flash cell, that is, realizes to original
The contraction of flash cell meets the new flash cell that user constructs different size on same chip domain；New flash cell
After replacing former flash cell, difference in areas is formed between former storage array and new storage array, in order to realize to whole chip version
The test of storage array in figure, therefore predetermined device virtual component is selected to be filled the difference in areas of formation.
Preferably, the predetermined device is virtual component, it should be noted that the structure of virtual component and flash cell one
It causes, but does not play the role of flash cell, and then realize and the integrated testability of new flash cell and new storage array is tested
Card.
In a kind of preferably embodiment, virtual component is filled in the surrounding of new storage array respectively.
In above-mentioned technical proposal, since new flash cell is less than former flash cell, the new storage array formed with
Former storage array there are difference in areas, due to the flash cell specification one in each new storage array and each former storage array
It causes, therefore new storage array is whole diminution, and the region of diminution can be filled by virtual component.
In a kind of preferably embodiment, the widthwise edges of each new storage array are provided with source interval；
The virtual component of new storage array width edge is set to adjacent source interval.
In a kind of preferably embodiment, the length edge of each new storage array is provided with equal with length sides
Virtual component.
In a kind of preferably embodiment, source diffusion layer is provided between every neighbouring new storage array.
In a kind of preferably embodiment, the adjustable setting of the width of source diffusion layer.
In above-mentioned technical proposal, according to the range that flash cell is reduced, can newly it be deposited by adjusting the adjusting of source diffusion layer
Store up the interval between array.
In a kind of preferably embodiment, word line spacer layer is provided between the adjacent new storage array in every left and right.
In above-mentioned technical proposal, the process of verifying includes to the new flash cell composition after shrink process in chip layout
The performance of new storage array tested.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (7)
1. the method that a kind of pair of flash cell shrinks verifying, applied in chip layout to the shrink process of flash cell, it is described
Chip layout includes multiple former storage arrays of multiple former flash cell compositions, which is characterized in that
The following steps are included:
Step S1, the new flash cell of a shrink process is set, and the new flash cell is replaced on the chip layout
The original flash cell, to form multiple new storage arrays；
Step S2, one group of predetermined device is provided between each former storage array and corresponding each new storage array
The predetermined face product moment of formation is filled, to form a predetermined dimension chip layout；
Wherein, the predetermined device is virtual device；
Step S3, corresponding chip is prepared according to the predetermined dimension chip layout；
Step S4, integrated testability verifying is carried out to above-mentioned corresponding chip.
2. the method according to claim 1 for shrinking verifying to flash cell, which is characterized in that the virtual device difference
It is filled in the surrounding of the new storage array.
3. the method according to claim 1 for shrinking verifying to flash cell, which is characterized in that each new storage battle array
The widthwise edges of column are provided with source interval；
The virtual device of the new storage array widthwise edges is set between the adjacent source interval.
4. the method according to claim 1 for shrinking verifying to flash cell, which is characterized in that each new storage battle array
The length edge of column is provided with the virtual device equal with length sides.
5. the method according to claim 4 for shrinking verifying to flash cell, which is characterized in that often neighbouring is described
Source diffusion layer is provided between new storage array.
6. the method according to claim 5 for shrinking verifying to flash cell, which is characterized in that the source diffusion layer
The adjustable setting of width.
7. the method according to claim 1 for shrinking verifying to flash cell, which is characterized in that adjacent described in every left and right
Word line spacer layer is provided between new storage array.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611110711.XA CN106601644B (en) | 2016-12-06 | 2016-12-06 | The method that a kind of pair of flash cell shrinks verifying |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611110711.XA CN106601644B (en) | 2016-12-06 | 2016-12-06 | The method that a kind of pair of flash cell shrinks verifying |
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| Publication Number | Publication Date |
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| CN106601644A CN106601644A (en) | 2017-04-26 |
| CN106601644B true CN106601644B (en) | 2019-07-02 |
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Citations (6)
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|---|---|---|---|---|
| KR100875006B1 (en) * | 2007-03-20 | 2008-12-19 | 주식회사 하이닉스반도체 | Flash memory device and program voltage control method |
| CN103902789A (en) * | 2014-04-22 | 2014-07-02 | 上海华力微电子有限公司 | Filling method of redundant graphs |
| CN104375377A (en) * | 2013-08-16 | 2015-02-25 | 上海华虹宏力半导体制造有限公司 | Method for compressing size of layout data |
| CN104637825A (en) * | 2013-11-14 | 2015-05-20 | 中芯国际集成电路制造(上海)有限公司 | Structure and method for packaging dimensionally shrunk semiconductor devices |
| CN105093850A (en) * | 2015-08-11 | 2015-11-25 | 上海华力微电子有限公司 | Method for preventing lens of lithography machine from being overheated |
| CN105843976A (en) * | 2015-01-15 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Dummy fill method for modified chip design |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6621741B2 (en) * | 2002-01-30 | 2003-09-16 | Fujitsu Limited | System for programming verification |
-
2016
- 2016-12-06 CN CN201611110711.XA patent/CN106601644B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100875006B1 (en) * | 2007-03-20 | 2008-12-19 | 주식회사 하이닉스반도체 | Flash memory device and program voltage control method |
| CN104375377A (en) * | 2013-08-16 | 2015-02-25 | 上海华虹宏力半导体制造有限公司 | Method for compressing size of layout data |
| CN104637825A (en) * | 2013-11-14 | 2015-05-20 | 中芯国际集成电路制造(上海)有限公司 | Structure and method for packaging dimensionally shrunk semiconductor devices |
| CN103902789A (en) * | 2014-04-22 | 2014-07-02 | 上海华力微电子有限公司 | Filling method of redundant graphs |
| CN105843976A (en) * | 2015-01-15 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Dummy fill method for modified chip design |
| CN105093850A (en) * | 2015-08-11 | 2015-11-25 | 上海华力微电子有限公司 | Method for preventing lens of lithography machine from being overheated |
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| CN106601644A (en) | 2017-04-26 |
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