CN106601292A - Nonvolatile storage device and programming method thereof - Google Patents
Nonvolatile storage device and programming method thereof Download PDFInfo
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- CN106601292A CN106601292A CN201611180860.3A CN201611180860A CN106601292A CN 106601292 A CN106601292 A CN 106601292A CN 201611180860 A CN201611180860 A CN 201611180860A CN 106601292 A CN106601292 A CN 106601292A
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- semiconductor memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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Abstract
The invention provides a nonvolatile storage device and a programming method thereof. The nonvolatile storage device comprises a storage unit array, a programming voltage generator, a bypass voltage generator and a calibration voltage generator, wherein the bypass voltage generator provides a bypass voltage for word lines in selected blocks in the storage unit array, and the voltage amplitudes of the bypass voltage in different word lines are equal. The programming method of the nonvolatile storage device comprises the steps that the same bypass voltage is exerted on the word lines in the storage unit array; a programming voltage is exerted on the word line where a selected storage unit is located; a calibration voltage is set according to the position of the word line where the selected storage unit is located; the corresponding calibration voltage is exerted on the word line where the selected storage unit is located, and calibration is performed. By exerting the same bypass voltage on different word lines, the bypass voltage generator does not need to be composed of multiple sets of voltage regulators and analog switches, therefore, an overall power management scheme is simplified, and the area is reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of nonvolatile semiconductor memory member and its programmed method.
Background technology
Even if electric erasable/programmable non-volatile memory part can also keep the data, internal memory to be when stopping power supply
One representative illustration of electric erasable/programmable non-volatile memory part.Particularly, NAND internal memory has string structure,
Plurality of flash cell series connection, therefore can be easily integrated and can be manufactured with low cost.For this purpose, NAND-type flash memory is
Jing is used as the data link of various types of portable product.
Fig. 1 is existing nonvolatile semiconductor memory member schematic diagram, as shown in figure 1, nonvolatile semiconductor memory member includes storage
Cell array 110, voltage generator and decoding transmission circuit 120, logic control circuit 130 and read/write circuit 140, wherein, deposit
Include multiple wordline 111 in storage unit array 110, each wordline is due to the difference of its position, the programming being necessary to apply different
Voltage and bypass voltage, Fig. 2 (a), Fig. 2 (b) and Fig. 2 (c) are applied in existing nonvolatile semiconductor memory member programmed method
Each V diagram, wherein, Fig. 2 (a) is the program voltage that different wordline apply, and Fig. 2 (b) is the stepping electricity that different wordline apply
Pressure, Fig. 2 (c) is the bypass voltage that different wordline apply, because every wordline of memory cell array needs different programming electricity
Pressure and bypass voltage, in the case where the wordline number of plies is more, it may be necessary to tens groups of voltage adjusters and analog switch, overall electricity
Power management schemes are huge.Even if by wordline subregion, increasing as wordline number of plies increase also results in number of partitions, it is still desirable to
More multigroup voltage adjuster and analog switch, power management scheme is still complicated.
Accordingly, it would be desirable to designing, a kind of different wordline apply identical bypass voltage and programing effect is impregnable non-volatile
Memory device and its programmed method, with the overall power management scheme scale of construction for solving existing nonvolatile semiconductor memory member it is huge and
Complicated problem.
The content of the invention
It is an object of the invention to provide a kind of different wordline apply identical bypass voltage and programing effect is impregnable
Nonvolatile semiconductor memory member and its programmed method, to solve the overall power management scheme body of existing nonvolatile semiconductor memory member
The huge and complicated problem of amount.
To solve above-mentioned technical problem, the present invention provides a kind of nonvolatile semiconductor memory member, the nonvolatile memory
Part includes that memory cell array, a program voltage generator, a bypass voltage generator and a calibration voltage are produced
Device, wherein：
The memory cell array includes some wordline and some memory element, and each wordline connects multiple memory element,
The wordline stacked arrangement；
The program voltage generator connects the memory cell array, provides for the wordline in the memory cell array
Program voltage；
The bypass voltage generator connects the memory cell array, is choosing in block in the memory cell array
Wordline bypass voltage is provided, the voltage amplitude of the bypass voltage of different wordline is equal；
The calibration voltage generator connects the memory cell array, provides for the wordline in the memory cell array
Calibration voltage.
Optionally, in described nonvolatile semiconductor memory member, the nonvolatile semiconductor memory member also includes logic control
Circuit, the logic control circuit controls the program voltage generator, bypass voltage generator and calibration voltage generator
Produce time and the voltage magnitude of voltage.
Optionally, in described nonvolatile semiconductor memory member, the nonvolatile semiconductor memory member also includes read/write circuit,
The read/write circuit is read out in wordline, programming and erasing operation.
Optionally, in described nonvolatile semiconductor memory member, the nonvolatile semiconductor memory member is three dimensional nonvolatile
Device or array in memorizer.
Optionally, in described nonvolatile semiconductor memory member, the nonvolatile semiconductor memory member includes multiple regions.
Optionally, in described nonvolatile semiconductor memory member, the nonvolatile semiconductor memory member monotonicity or irregular
Arrangement.
Optionally, in described nonvolatile semiconductor memory member, the nonvolatile semiconductor memory member is located in NAND chip.
Optionally, in described nonvolatile semiconductor memory member, the nonvolatile semiconductor memory member is located in eMMC chips.
Optionally, in described nonvolatile semiconductor memory member, the nonvolatile semiconductor memory member is located in SSD chips.
The present invention also provides a kind of nonvolatile semiconductor memory member programmed method, the nonvolatile semiconductor memory member programmed method
Including：
Programming instruction is input into memory cell array；
The position setting program voltage of the wordline being located according to the memory element selected in programming instruction；
Bypass voltage generator to all wordline chosen in block in memory cell array apply identical bypass electricity
Pressure；
Program voltage generator to the wordline that selected memory element is located applies corresponding program voltage, to memory element
In wordline be programmed；
The position setting calibration voltage of the wordline being located according to the memory element selected in programming instruction；
Calibration voltage generator to the wordline that selected memory element is located applies corresponding calibration voltage, to memory element
In wordline verified.
Optionally, in described nonvolatile semiconductor memory member programmed method, the nonvolatile semiconductor memory member programming side
Carrying out verification to the wordline in memory element in method includes：
If verification passes through, the nonvolatile semiconductor memory member programming terminates；
If verification failure, applies identical bypass voltage to some wordline again, to selected wordline programming is applied
Voltage, according to the position of selected wordline calibration voltage is set, and to selected wordline calibration voltage is applied, and is verified again.
Optionally, in described nonvolatile semiconductor memory member programmed method, the nonvolatile semiconductor memory member programming side
Method also includes：
The threshold voltage of the wordline that the memory element chosen is located passes through more than calibration voltage, then verification；
The threshold voltage of the wordline that the memory element chosen is located is less than calibration voltage, then verification failure.
Optionally, in described nonvolatile semiconductor memory member programmed method, the size of the threshold voltage is by adjusting
Program voltage is adjusting.
It is storage by bypass voltage generator in the nonvolatile semiconductor memory member and its programmed method that the present invention is provided
The wordline chosen in block in cell array provides bypass voltage, and the voltage amplitude of the bypass voltage of different wordline is equal, makes
Without the need for being made up of multigroup voltage adjuster and analog switch, overall power management scheme simplifies bypass voltage generator and area subtracts
It is little.In nonvolatile semiconductor memory member programmed method, by applying the step such as corresponding calibration voltage and verification, until threshold value is electric
Pressure is further move upwardly until by verification to pros, in the case that realization applies identical bypass voltage in different wordline,
The reliability of program rate and programming is not affected.
Nonvolatile semiconductor memory member proposed by the present invention and its programmed method answering for three dimensional nonvolatile storage array
With a kind of new programmed method is proposed, it is suitable for but is not limited to all kinds of three dimensional nonvolatile memory arrays, the method can be suitable for
But device and array in the three dimensional nonvolatile memorizer in cited existing correlation technique are not limited to, can be single according to storage
The characteristic of element array has different subregion and monotonicity or irregular arrangement, using the device of the present invention be not limited to it is three-dimensional it is non-easily
Lose property memory array itself, can be include the array circuit system and electronic product, including but not limited to NAND chip,
EMMC chips, SSD chips etc..
Different word line layers (or area) use identical bypass voltage, and using the programming stepping of each word line layer (or area) of adaptation
Voltage schemes, the device programming speed of balanced each word line layer (or area), balanced each floor (or area) device is received under non-selected state
The programming interference arrived.
Using technical scheme proposed by the invention, used in programming operation identical bypass voltage, it is to avoid existing
Because increasing design complexity using multigroup bypass voltage in technology, the multigroup program voltage and calibration voltage needed for the present invention,
It is that conventional design layout can be provided, does not dramatically increase design complexity.In a word, the solution of the present invention improves programming behaviour
Make, on the premise of design complexity is not dramatically increased, realize the programming to three dimensional nonvolatile memory array.
Description of the drawings
Fig. 1 is existing nonvolatile semiconductor memory member schematic diagram；
Fig. 2 (a)～Fig. 2 (c) is each V diagram that existing nonvolatile semiconductor memory member applies；
Fig. 3 (a)～Fig. 3 (c) is each V diagram that nonvolatile semiconductor memory member of the present invention applies；
Fig. 4 is nonvolatile semiconductor memory member programmed method flow chart of the present invention；
Fig. 5 is the voltage flow chart applied in nonvolatile semiconductor memory member programmed method of the present invention；
Fig. 6～7 are threshold voltage variation schematic diagrams in nonvolatile semiconductor memory member programmed method of the present invention；
Fig. 8 is threshold voltage variation schematic diagram in nonvolatile semiconductor memory member programmed method of the present invention；
Shown in figure：110- memory cell arrays；111- wordline；120- voltage generators；130- logic control circuits；
140- read/write circuits；51～58- program voltages；59- calibration voltages.
Specific embodiment
Below in conjunction with accompanying drawing 3～8 and specific embodiment to nonvolatile semiconductor memory member proposed by the present invention and its programming side
Method is described in further detail.According to following explanation and claims, advantages and features of the invention will become apparent from.Need explanation
, accompanying drawing in the form of simplifying very much and uses non-accurately ratio, only conveniently, lucidly to aid in illustrating this
The purpose of inventive embodiments.
The core concept of the present invention is to provide a kind of nonvolatile semiconductor memory member and its programmed method, existing to solve
The huge and complicated problem of the overall power management scheme scale of construction of nonvolatile semiconductor memory member.
To realize above-mentioned thought, the invention provides a kind of nonvolatile semiconductor memory member for applying identical bypass voltage, with
And the programmed method of the nonvolatile semiconductor memory member of the identical bypass voltage of applying.
<Embodiment one>
The present embodiment provides a kind of nonvolatile semiconductor memory member, and the nonvolatile semiconductor memory member includes memory element battle array
Row, program voltage generator, a bypass voltage generator and a calibration voltage generator, wherein：The storage
Cell array includes some wordline and some memory element, and each wordline connects multiple memory element, the wordline stacked arrangement；
The program voltage generator connects the memory cell array, and for the wordline in the memory cell array programming electricity is provided
Pressure.
Fig. 3 (a) is the program voltage schematic diagram that nonvolatile semiconductor memory member of the present invention applies, WL7～WL1, with wordline
The increase of position, the amplitude of program voltage is gradually reduced, and the bypass voltage generator connects the memory cell array, is institute
The wordline chosen in block stated in memory cell array provides bypass voltage, different from bypass of the prior art in Fig. 2 (c)
The amplitude of voltage reduces with the increase of the position of wordline, and Fig. 3 (b) is the bypass that nonvolatile semiconductor memory member of the present invention applies
Shown in V diagram, such as Fig. 3 (b), the voltage amplitude of the bypass voltage of different wordline is equal, not with the change of word line position
And change；The calibration voltage generator connects the memory cell array, provides for the wordline in the memory cell array
Calibration voltage, Fig. 3 (c) is the calibration voltage schematic diagram that nonvolatile semiconductor memory member of the present invention applies, from WL7～WL1, with word
The increase of line position, the amplitude of program voltage gradually increases.
Further, the nonvolatile semiconductor memory member also includes logic control circuit, the logic control circuit control
The program voltage generator, bypass voltage generator and calibration voltage generator produce the time of voltage and voltage magnitude.
The nonvolatile semiconductor memory member also includes read/write circuit, and the read/write circuit is read out in wordline, programmed and erased behaviour
Make.The nonvolatile semiconductor memory member can carry out subregion, i.e., including multiple regions, it is also possible to monotonicity or irregular arrangement.
The nonvolatile semiconductor memory member monotonicity arrangement, refers to the physical size of nonvolatile semiconductor memory member in one direction
The change of upper rule, i.e. its physical size of the reduction of systematicness, cause WL7～WL1, with the increase of word line position, i.e. folk prescription
To displacement spatially change, WL7～WL1 physical sizes systematicness reduces, further result in the amplitude of program voltage by
It is decrescence little；The nonvolatile semiconductor memory member is irregularly arranged, and refers to the whole memory cell array of nonvolatile semiconductor memory member,
It is divided into multiple different regions, in each region, the change of physical size rule in one direction of nonvolatile semiconductor memory member
Change, but between zones, the physical size then irregular change of nonvolatile semiconductor memory member, or it is every in memory cell array
The change of the physical size of individual nonvolatile semiconductor memory member is all irregular.
Specifically, the nonvolatile semiconductor memory member is the device or array in three dimensional nonvolatile memorizer.It is described non-
Volatile memory device can be located at NAND chip, in eMMC chips, or SSD chips.
Using technical scheme proposed by the invention, used in programming operation identical bypass voltage, it is to avoid existing
Because increasing design complexity using multigroup bypass voltage in technology, the multigroup program voltage and calibration voltage needed for the present invention,
It is that conventional design layout can be provided, does not dramatically increase design complexity.In a word, the solution of the present invention improves programming behaviour
Make, on the premise of design complexity is not dramatically increased, realize the programming to three dimensional nonvolatile memory array.
<Embodiment two>
The present embodiment provides a kind of nonvolatile semiconductor memory member programmed method, and Fig. 4 is nonvolatile semiconductor memory member of the present invention
Programmed method flow chart, as shown in figure 4, the nonvolatile semiconductor memory member programmed method includes：Memory cell array is input into
Programming instruction；The position setting program voltage of the wordline being located according to the memory element selected in programming instruction；Bypass voltage is produced
Raw device to all wordline chosen in block in memory cell array apply identical bypass voltage；Program voltage generator to
The wordline that selected memory element is located applies corresponding program voltage, and the wordline in memory element is programmed；According to choosing
The word line position setting calibration voltage that fixed memory element is located；Calibration voltage generator to selected memory cell array is located
Wordline apply corresponding calibration voltage, the wordline in memory element is verified；Fig. 5 is nonvolatile memory of the present invention
The voltage flow chart applied in part programmed method, as shown in figure 5, apply program voltage 51 first, in memory cell array
Wordline is programmed, and then applies calibration voltage 59, and the memory element to selecting is verified, the voltage amplitude of program voltage 51～58
Value gradually increases.
Further, verification bag is carried out to the wordline in memory element in the nonvolatile semiconductor memory member programmed method
Include：If verification passes through, the nonvolatile semiconductor memory member programming terminates；If verification failure, again to some wordline
Apply identical bypass voltage, to selected wordline program voltage applied, calibration voltage is set according to the position of selected wordline,
Apply calibration voltage to selected wordline, verify again.
Specifically, the memory element in flash memory is programmed or wiped using the physical phenomenon for being referred to as F-N tunnel-effects,
During erasing operation, ground voltage is applied to the control gate of memory cell transistor, and high voltage (i.e. more than regulation power supply
The voltage of voltage) it is applied to the Semiconductor substrate (or matrix (bulk)) related to the memory element.In these erasing biass
Under the conditions of, highfield is formed between floating grid and matrix, due to the big voltage difference occurred on floating grid and matrix, float
Put the electronics accumulated on grid and matrix is discharged into by F-N tunnel-effects, in other words, wipe the threshold value of the cell transistor of (E)
Voltage Vth is moved in a negative direction.
During the programming operation of memory element, high voltage (i.e. more than the voltage of supply voltage) is applied to Component units
The control gate of transistor, and ground voltage is applied to drain electrode and the matrix of the cell transistor, under these bias conditions,
Electronics is injected on the floating grid of cell transistor by F-N tunnel-effects.In other words, the cell transistor of (P) is programmed
Threshold voltage vt h is moved in the positive direction.
Fig. 6～7 are threshold voltage variation schematic diagrams in nonvolatile semiconductor memory member programmed method of the present invention, and Vth is threshold value
Voltage, Vvr is calibration voltage, and WL1 is the first wordline, and WL2 is the second wordline, and WL3 is the 3rd wordline, and E represents erase status, P
Represent programming state.In order that the wordline for applying identical bypass voltage reaches, and program rate is identical, the high effect of reliability is programmed
Really, the nonvolatile semiconductor memory member programmed method needs to have adjusted the threshold voltage of different wordline, and what adjustment was chosen deposits
The threshold voltage of the wordline that storage unit is located, it is right that the threshold voltage of each wordline after adjustment is carried out with its respective calibration voltage
Than threshold voltage is more than calibration voltage, then verification passes through；Threshold voltage is less than calibration voltage, then verification failure.And with WL7
The increase of～WL1 word line positions, calibration voltage gradually increases, as shown in fig. 7, the calibration voltage Vvr1 of the first wordline WL1 is more than
The calibration voltage Vvr2 of the second wordline WL2, the calibration voltage Vvr2 of the second wordline WL2 are more than the calibration voltage of the 3rd wordline WL3
Vvr3, so by the verification of calibration voltage, can step up the threshold voltage vt h of each wordline, make the threshold of the first wordline WL1
Threshold voltage is more than the threshold voltage of the second wordline WL2, and the threshold voltage of the second wordline WL2 is electric more than the threshold value of the 3rd wordline WL3
Pressure, the i.e. threshold voltage of each wordline to positive direction moves certain value, and with the increase of word line position, mobile value is got over
Greatly, then according to calibration voltage Vvr verifying, whether judging the threshold voltage vt h of the wordline in memory cell array, reach will
Ask.
In nonvolatile semiconductor memory member programmed method, by applying the step such as corresponding calibration voltage and verification, until
Threshold voltage is further move upwardly until that, by verification, realization applies the feelings of identical bypass voltage in different wordline to pros
Under condition, the reliability of program rate and programming is not affected.
Fig. 8 is threshold voltage variation schematic diagram in nonvolatile semiconductor memory member programmed method of the present invention, the increasing of threshold voltage
Plus realized by increasing program voltage, as shown in figure 8, threshold voltage and the proportional relation of program voltage, if increased
Program voltage, threshold voltage can be accordingly increased.The size of the threshold voltage is adjusted by adjusting program voltage.
Further, the nonvolatile semiconductor memory member is the device or array in three dimensional nonvolatile memorizer, can
To carry out subregion, it is also possible to monotonicity or irregular arrangement.The nonvolatile semiconductor memory member is three dimensional nonvolatile memorizer
In device or array.The nonvolatile semiconductor memory member is located in NAND chip.The nonvolatile semiconductor memory member is located at
In eMMC chips.The nonvolatile semiconductor memory member is located in SSD chips.
It is storage by bypass voltage generator in the nonvolatile semiconductor memory member and its programmed method that the present invention is provided
Cell array provides bypass voltage, and the voltage amplitude of the bypass voltage of different wordline is equal, makes the bypass voltage generator need not
It is made up of multigroup voltage adjuster and analog switch, overall power management scheme simplifies and area reduces.In non-volatile memories
In device programming method, by applying identical bypass voltage, applying program voltage, setting calibration voltage, apply corresponding school
The step such as electrical verification pressure and verification, until threshold voltage is further move upwardly until by verification to pros, realizes in different words
In the case of applying identical bypass voltage on line, the reliability of program rate and programming is not affected.
Nonvolatile semiconductor memory member proposed by the present invention and its programmed method answering for three dimensional nonvolatile storage array
With a kind of new programmed method is proposed, it is suitable for but is not limited to all kinds of three dimensional nonvolatile memory arrays, the method can be suitable for
But device and array in the three dimensional nonvolatile memorizer in cited existing correlation technique are not limited to, can be single according to storage
The characteristic of element array has different subregion and monotonicity or irregular arrangement, using the device of the present invention be not limited to it is three-dimensional it is non-easily
Lose property memory array itself, can be include the array circuit system and electronic product, including but not limited to NAND chip,
EMMC chips, SSD chips etc..
Different word line layers (or area) use identical bypass voltage, and using the programming stepping of each word line layer (or area) of adaptation
Voltage schemes, the device programming speed of balanced each word line layer (or area), balanced each floor (or area) device is received under non-selected state
The programming interference arrived.
Using technical scheme proposed by the invention, used in programming operation identical bypass voltage, it is to avoid existing
Because increasing design complexity using multigroup bypass voltage in technology, the multigroup program voltage and calibration voltage needed for the present invention,
It is that conventional design layout can be provided, does not dramatically increase design complexity.In a word, the solution of the present invention improves programming behaviour
Make, on the premise of design complexity is not dramatically increased, realize the programming to three dimensional nonvolatile memory array.
Each embodiment is described by the way of progressive in this specification, and what each embodiment was stressed is and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.Foregoing description is only to the present invention
The description of preferred embodiment, not to any restriction of the scope of the invention, the those of ordinary skill in field of the present invention is according to above-mentioned
Any change, modification that disclosure is done, belong to the protection domain of claims.
Claims (13)
1. a kind of nonvolatile semiconductor memory member, it is characterised in that the nonvolatile semiconductor memory member include memory cell array, one
Individual program voltage generator, a bypass voltage generator and a calibration voltage generator, wherein：
The memory cell array includes some wordline and some memory element, and each wordline connects multiple memory element, described
Wordline stacked arrangement；
The program voltage generator connects the memory cell array, and for the wordline in the memory cell array programming is provided
Voltage；
The bypass voltage generator connects the memory cell array, is choosing in block in the memory cell array
Wordline provides bypass voltage, and the voltage amplitude of the bypass voltage of different wordline is equal；
The calibration voltage generator connects the memory cell array, and for the wordline in the memory cell array verification is provided
Voltage.
2. nonvolatile semiconductor memory member as claimed in claim 1, it is characterised in that the nonvolatile semiconductor memory member also includes
Logic control circuit, the logic control circuit controls the program voltage generator, bypass voltage generator and verification electricity
Pressure generator produces time and the voltage magnitude of voltage.
3. nonvolatile semiconductor memory member as claimed in claim 1, it is characterised in that the nonvolatile semiconductor memory member also includes
Read/write circuit, the read/write circuit is read out in wordline, programming and erasing operation.
4. nonvolatile semiconductor memory member as claimed in claim 1, it is characterised in that the nonvolatile semiconductor memory member is three-dimensional
Device or array in nonvolatile memory.
5. nonvolatile semiconductor memory member as claimed in claim 1, it is characterised in that the nonvolatile semiconductor memory member includes many
Individual region.
6. nonvolatile semiconductor memory member as claimed in claim 1, it is characterised in that the nonvolatile semiconductor memory member monotonicity
Or irregular arrangement.
7. nonvolatile semiconductor memory member as claimed in claim 1, it is characterised in that the nonvolatile semiconductor memory member is located at
In NAND chip.
8. nonvolatile semiconductor memory member as claimed in claim 1, it is characterised in that the nonvolatile semiconductor memory member is located at
In eMMC chips.
9. nonvolatile semiconductor memory member as claimed in claim 1, it is characterised in that the nonvolatile semiconductor memory member is located at
In SSD chips.
10. a kind of nonvolatile semiconductor memory member programmed method, it is characterised in that the nonvolatile semiconductor memory member programmed method bag
Include：
Programming instruction is input into memory cell array；
The position setting program voltage of the wordline being located according to the memory element selected in programming instruction；
Bypass voltage generator to all wordline chosen in block in memory cell array apply identical bypass voltage；
Program voltage generator to the wordline that selected memory element is located applies corresponding program voltage, in memory element
Wordline is programmed；
The position setting calibration voltage of the wordline being located according to the memory element selected in programming instruction；
Calibration voltage generator to the wordline that selected memory element is located applies corresponding calibration voltage, in memory element
Wordline is verified.
11. nonvolatile semiconductor memory member programmed methods as claimed in claim 10, it is characterised in that the non-volatile memories
Carrying out verification to the wordline in memory element in device programming method includes：
If verification passes through, the nonvolatile semiconductor memory member programming terminates；
If verification failure, applies identical bypass voltage to some wordline again, to selected wordline program voltage is applied,
Calibration voltage is set according to the position of selected wordline, to selected wordline calibration voltage is applied, verified again.
12. nonvolatile semiconductor memory member programmed methods as claimed in claim 11, it is characterised in that the non-volatile memories
Device programming method also includes：
The threshold voltage of the wordline that the memory element chosen is located passes through more than calibration voltage, then verification；
The threshold voltage of the wordline that the memory element chosen is located is less than calibration voltage, then verification failure.
13. nonvolatile semiconductor memory member programmed methods as claimed in claim 12, it is characterised in that the threshold voltage it is big
It is little to be adjusted by adjusting program voltage.
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| CN1983448A (en) * | 2005-11-17 | 2007-06-20 | 三星电子株式会社 | Flash memory device and word line enable method thereof |
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| CN102810332A (en) * | 2011-06-03 | 2012-12-05 | 三星电子株式会社 | Non-volatile memory device and method controlling dummy word line voltage according to location of selected word line |
| US20130250690A1 (en) * | 2012-03-26 | 2013-09-26 | Chun-Hung Lai | Selected word line dependent select gate voltage during program |
| CN104916319A (en) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | Semiconductor memory device |
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- 2016-12-20 CN CN201611180860.3A patent/CN106601292A/en active Pending
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|---|---|---|---|---|
| CN1983448A (en) * | 2005-11-17 | 2007-06-20 | 三星电子株式会社 | Flash memory device and word line enable method thereof |
| US20110199833A1 (en) * | 2010-02-17 | 2011-08-18 | Samsung Electronics Co., Ltd. | Non-volatile memory devices, operating methods thereof and memory systems including the same |
| CN102810332A (en) * | 2011-06-03 | 2012-12-05 | 三星电子株式会社 | Non-volatile memory device and method controlling dummy word line voltage according to location of selected word line |
| US20130250690A1 (en) * | 2012-03-26 | 2013-09-26 | Chun-Hung Lai | Selected word line dependent select gate voltage during program |
| CN104916319A (en) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | Semiconductor memory device |
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