CN106599556B - The comprehensive performance evaluation method and apparatus of integrated circuit - Google Patents
The comprehensive performance evaluation method and apparatus of integrated circuit Download PDFInfo
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- CN106599556B CN106599556B CN201611092473.4A CN201611092473A CN106599556B CN 106599556 B CN106599556 B CN 106599556B CN 201611092473 A CN201611092473 A CN 201611092473A CN 106599556 B CN106599556 B CN 106599556B
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Abstract
The present invention relates to a kind of comprehensive performance evaluation method and apparatus of integrated circuit, this method comprises: obtaining the measured value of the relevant parameter of N number of to-be-measured integrated circuit, and obtain elementary item score value and addition Item score value based on measured value；If the elementary item score value of each to-be-measured integrated circuit is both less than reference value, each to-be-measured integrated circuit is ranked up to obtain final ranking results using the evaluation method based on threshold value；Evaluation result based on final ranking results output integrated performance.Evaluation method based on threshold value is the following steps are included: the elementary item score value according to each to-be-measured integrated circuit is sorted in advance；If the difference of the elementary item score value of two to-be-measured integrated circuits of arbitrary neighborhood after pre- sequence is less than preset threshold, elementary item score value and addition Item score value based on two to-be-measured integrated circuits are adjusted to obtain ranking results to pre- ranking results.By having comprehensively considered the elementary item of integrated circuit and the influence of addition Item, keep the evaluation of integrated circuit more practical, reasonable, comprehensive and objective.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to the comprehensive performance evaluation method and dress of a kind of integrated circuit
It sets.
Background technique
Programmable logic array (FPGA) due to its have the characteristics that it is programmable, flexibly easily upgrading, expense is low is widely applied
In fields such as aerospace, communication, radar, audio-video processing.
In the application of FPGA device, in order to select optimal FPGA device, user and testing agency are usually required to not
FPGA device with producer compares evaluation.However, how to carry out reasonable evaluation to FPGA device comprehensively so as to objective
The basic performance and additional properties for assessing FPGA device between different vendor, become one paid close attention in FPGA device industrialized development
A focus.
Summary of the invention
Based on this, it is necessary to provide the method for evaluating performance and device of a kind of comprehensive and practical integrated circuit.
A kind of comprehensive performance evaluation method of integrated circuit, comprising:
The measured value of the relevant parameter of N number of to-be-measured integrated circuit is obtained, and elementary item score value is obtained based on the measured value
With addition Item score value；
If the elementary item score value of each to-be-measured integrated circuit is both less than reference value, using the evaluation method based on threshold value to institute
Each to-be-measured integrated circuit is stated to be ranked up to obtain final ranking results；
Evaluation result based on the final ranking results output integrated performance；
The evaluation method based on threshold value the following steps are included:
It is sorted in advance according to the elementary item score value of each to-be-measured integrated circuit；
If the difference of the elementary item score value of two to-be-measured integrated circuits of arbitrary neighborhood after pre- sequence is less than preset threshold,
Elementary item score value and addition Item score value based on two to-be-measured integrated circuits are adjusted to obtain ranking results to pre- ranking results.
A kind of comprehensive performance evaluation device of integrated circuit, comprising: parameter acquisition module, evaluation module based on threshold value,
Sorting module and evaluation module；
The parameter acquisition module, the measured value of the relevant parameter for obtaining N number of to-be-measured integrated circuit, and based on described
Measured value obtains elementary item score value and addition Item score value；
The sorting module, for when the elementary item score value of each to-be-measured integrated circuit is both less than reference value, described in calling
Each to-be-measured integrated circuit is ranked up to obtain final ranking results based on the evaluation module of threshold value；
The evaluation module, for the evaluation result based on the final ranking results output integrated performance；
The evaluation module based on threshold value includes pre-ranking module and adjustment module；
The pre-ranking module, for being sorted in advance according to the elementary item score value of each to-be-measured integrated circuit；
The adjustment module, the difference of the elementary item score value for two to-be-measured integrated circuits of arbitrary neighborhood after pre- sequence
When value is less than preset threshold, elementary item score value and addition Item score value based on two to-be-measured integrated circuits carry out pre- ranking results
Adjustment obtains ranking results.
The comprehensive performance evaluation method of said integrated circuit is both less than referred in the elementary item score value of each to-be-measured integrated circuit
When value, each to-be-measured integrated circuit is ranked up using the evaluation method based on threshold value, specifically, first by each integrated circuit according to
Elementary item score value is ranked up, when the difference of two adjacent integrated circuits is less than preset threshold, in conjunction with elementary item score value and
Addition Item score value is adjusted pre- ranking results, has comprehensively considered the elementary item of integrated circuit and the influence of addition Item, makes to collect
It is more practical, reasonable, comprehensive and objective at the evaluation of circuit.
Detailed description of the invention
Fig. 1 is a kind of flow chart of the method for evaluating performance of the integrated circuit of embodiment；
Fig. 2 is the step explanatory diagram that the evaluation method based on threshold value of one embodiment is ranked up；
Fig. 3 is the flow chart of the method for evaluating performance of the integrated circuit of another embodiment；
Fig. 4 is the flow chart of the method for evaluating performance of the integrated circuit of one embodiment；
Fig. 5 is evaluation schematic diagram when score value difference is less than threshold value two-by-two in one embodiment；
Fig. 6 is the functional block diagram of the device for evaluating performance of the integrated circuit of one embodiment.
Specific embodiment
A kind of comprehensive performance evaluation method of integrated circuit, as shown in Figure 1, comprising the following steps:
S102: the measured value of the relevant parameter of N number of to-be-measured integrated circuit is obtained, and elementary item score value is obtained based on measured value
With addition Item score value.
Specifically, the relevant parameter item based on FPGA device, its parameter value is measured and compared with nominal value, based on comparing knot
Fruit calculates separately its elementary item score value (Di) and addition Item score value (Ei).Elementary item expression meets FPGA device basic function and property
The parameter item and its index that can be required, what is characterized is the normal value whether FPGA device has reached design requirement.Addition Item
Indicate that the related parameter of FPGA device can be obtained better performance under the premise of meeting basic function and performance requirement and refer to
Scale value, characterization is surplus of the FPGA device beyond design requirement normal value.
S104: the elementary item score value of each to-be-measured integrated circuit is compared with reference value, if each to-be-measured integrated circuit
Elementary item score value is both less than reference value, thens follow the steps:
S106: each to-be-measured integrated circuit is ranked up to obtain final ranking results using the evaluation method based on threshold value.
Reference value in the present embodiment is elementary item total score.By the elementary item score value of each to-be-measured integrated circuit respectively with ginseng
It examines value to be compared, if the elementary item score value of each to-be-measured integrated circuit is both less than reference value, uses the evaluation side based on threshold value
Method is ranked up each to-be-measured integrated circuit to obtain final ranking results.Evaluation method based on threshold value, as shown in Figure 2, comprising:
S1061: it is sorted in advance according to the elementary item score value of each to-be-measured integrated circuit.
Pre- sequence is carried out according to the sequence of the elementary item score value of each to-be-measured integrated circuit.If D is elementary item score value, E is attached
Plus item score value, R are preset threshold.
In one embodiment, elementary item score value of the sequence based on integrated circuit to be detected as low as big progress certainly in advance.It is false
If the result to sort in advance are as follows: D1≤Di≤Dj≤DN
S1062: successively by the difference of the elementary item score value of the two neighboring to-be-measured integrated circuit after pre- sequence and default threshold
Value is compared, if being less than, thens follow the steps S1063, if more than S1064 is thened follow the steps.
S1063: elementary item score value and addition Item score value based on two to-be-measured integrated circuits adjust pre- ranking results
It is whole to obtain final ranking results.
S1064: maintain the result to sort in advance constant.
If the difference of the elementary item score value of two to-be-measured integrated circuits of arbitrary neighborhood after pre- sequence is greater than and preset threshold,
Then maintain the result to sort in advance constant.
Even Dj-Di>=R, wherein i<j, i ∈ N, j ∈ N, then jth #FPGA comes before the i-th #FPGA.
The otherness that preset threshold characterizes different to-be-measured integrated circuits is horizontal, the elementary item point of two to-be-measured integrated circuits
The difference of value exceeds the threshold value, i.e. the absolute value of the difference of elementary item score value is greater than preset threshold, then it is assumed that two collection to be measured
It can be distinguished at the overall performance level of circuit.If the difference of the elementary item score value of two to-be-measured integrated circuits is default less than this
Threshold value, then it is assumed that the overall performance level of two to-be-measured integrated circuits can not be distinguished, then according to two integrated electricity to be measured
The elementary item score value and addition Item score value on road are adjusted pre- ranking results.I.e. in the overall performance of two to-be-measured integrated circuits
When level can not be distinguished, in conjunction with to-be-measured integrated circuit elementary item score value and addition Item score value the case where to pre- ranking results into
Row adjustment, has comprehensively considered the elementary item of to-be-measured integrated circuit and the influence of addition Item.
Preset threshold can be set according to fine requirement of the user to evaluation.If user is high to the fine requirement of evaluation, can set
A fixed lesser threshold value can set a biggish threshold value if requirement of the user to evaluation is rough.
After step 106, further includes:
S108: based on the output of final ranking results to the evaluation result of to-be-measured integrated circuit.
The comprehensive performance evaluation method of above-mentioned to-be-measured integrated circuit is all small in the elementary item score value of each to-be-measured integrated circuit
When reference value, each to-be-measured integrated circuit is ranked up using the evaluation method based on threshold value, specifically, first by each collection to be measured
It is ranked up at circuit according to elementary item score value, when the difference of two adjacent to-be-measured integrated circuits is less than preset threshold, knot
It closes elementary item score value and addition Item score value is adjusted pre- ranking results, comprehensively considered the elementary item of integrated circuit and add
The influence of item, keeps the evaluation of integrated circuit more practical, reasonable, comprehensive and objective.
Specifically, if Dj-Di< R, wherein i < j, i ∈ N, j ∈ N, then step S1063, based on two to-be-measured integrated circuits
Elementary item score value and addition Item score value are adjusted pre- ranking results.It is specific it is several under several situations,
If one, to be measured integrated electricity of the sum of the elementary item score value and addition Item of previous to-be-measured integrated circuit less than the latter
The elementary item score value on road and the sum of addition Item, then maintain pre- ranking results constant.
That is, if Ei+Di<Ej+Dj, then original sequence is maintained, j-th of to-be-measured integrated circuit is come into i-th of integrated electricity to be measured
Before road.
If two, to be measured integrated electricity of the sum of the elementary item score value and addition Item of previous to-be-measured integrated circuit greater than the latter
The elementary item score value on road and the sum of addition Item then exchange the position of the two in pre- ranking results.
That is Ei+Di>Ej+Dj, then the position of the two is exchanged, i-th of to-be-measured integrated circuit is come into j-th of integrated electricity to be measured
Before the A of road.
If three, to be measured integrated electricity of the sum of the elementary item score value and addition Item of previous to-be-measured integrated circuit equal to the latter
The elementary item score value on road and the sum of addition Item, even Ei+Di=Ej+Dj, 2 kinds of situations can be divided to be determined at this time:
If 1), Dj>Di, then original sequence is maintained, before j-th of to-be-measured integrated circuit is come i-th of to-be-measured integrated circuit
Face；
If 2), Dj=Di, then sequence of two to-be-measured integrated circuits in pre- sequence is arranged side by side, i.e. j-th of to-be-measured integrated circuit
It is arranged side by side with i-th of to-be-measured integrated circuit ranking.
In another embodiment, in step S104, as shown in figure 3, if M integrated electricity to be measured in each to-be-measured integrated circuit
The elementary item score value on road is equal to reference value；Wherein M < N is thened follow the steps:
S1051:M to-be-measured integrated circuit is ranked up to obtain first part's ranking results according to addition Item score value.
For in to-be-measured integrated circuit, elementary item score value is equal to M to-be-measured integrated circuit of reference value, according to addition Item point
Value is ranked up to obtain the ranking results of first part.Specifically,
If D is the evaluation and test score value of elementary item, E is addition Item score value.D might as well be set1=Di=Dj=DM.It only needs to M
FPGA carries out the sequence of addition Item score value.It enablesIt indicates to after the progress of different FPGA device addition Item total scores from big to small ranking
Vector, i.e.,Wherein SiThe addition Item total score for indicating i-th of FPGA device, indicating as i=1 should
FPGA device overall performance level is optimal.It is so as follows to FPGA addition Item ranking evaluation algorithms, wherein function sort
() indicates to carry out the set in () sorting operation from big to small.
S1052: it is less than N-M to-be-measured integrated circuit of reference value to elementary item score value using the evaluation method based on threshold value
It is ranked up to obtain second part ranking results.
For in to-be-measured integrated circuit, elementary item score value is less than N-M to-be-measured integrated circuit of reference value, using based on threshold
The evaluation method of value obtains second part ranking results.Identical as front based on the evaluation method of threshold value, details are not described herein.
S1053: the final of each to-be-measured integrated circuit is obtained according to first part's ranking results and second part ranking results
Ranking results.
It should be understood that the sequence of first part's ranking results is sorted in second part ties in final ranking results
Before the sequence of fruit.That is elementary item score value is more preferable equal to the comprehensive performance of the to-be-measured integrated circuit of reference value.
In the present embodiment, in to-be-measured integrated circuit, elementary item score value be equal to the to-be-measured integrated circuit of reference value according to
Added value is ranked up, for elementary item score value be less than reference value to-be-measured integrated circuit using the evaluation method based on threshold value into
Row sequence, comprehensively considered the elementary item of integrated circuit and the influence of addition Item, make the evaluation of integrated circuit it is more practical, close
It manages, is comprehensive and objective.
In another embodiment, if in step 104, the elementary item score value of N number of to-be-measured integrated circuit is equal to reference value,
Then each to-be-measured integrated circuit is ranked up according to addition Item score value to obtain final ranking results.
Specifically, setting D as elementary item score value, E is addition Item score value.D might as well be set1=Di=Dj=DNN number of FPGA is based on
Addition Item score value is ranked up.It enablesIndicate to carry out different FPGA device addition Item total scores from big to small after ranking to
Amount, i.e.,Wherein SiThe addition Item total score for indicating i-th of FPGA device indicates the FPGA device as i=1
Part overall performance level is optimal.So to shown under FPGA addition Item ranking evaluation algorithms, wherein function sort () expression pair
Set in () carries out sorting operation from big to small.
The comprehensive performance evaluation method of above-mentioned integrated circuit is widely used, can be to all comprising elementary item and addition Item
The integrated circuit of equal essential elements of evaluation is evaluated.Below by taking N=3 as an example, the comprehensive performance evaluation method of FPGA device is carried out
Explanation.Specific evaluation procedure is as shown in Figure 4.
Specifically, determining respectively according to following condition:
1) if three FPGA device elementary item score values are both less than reference value namely three FPGA devices all do not obtain elementary item
Total score full marks value, then three FPGA devices are carried out according to decision condition 5；
If 2) an only FPGA device elementary item score value obtains elementary item total score full marks value, which is to comment
It valence the 1st, is ranked up without the evaluation method based on threshold value；Other two FPGA devices according to decision condition 6 into
Row；
If 3) any two FPGA devices elementary item score value obtains elementary item total score full marks value, which is adopted
It is ranked up with the evaluation method based on threshold value and is carried out according to decision condition 7, third man FPGA device is evaluation the 3rd；
4) if three FPGA device elementary item score values all obtain elementary item total score full marks value, at this time three FPGA devices
It is all ranked up using the evaluation method based on threshold value and is carried out according to decision condition 8.
Decision condition 5 is described as follows:
If A, B, C respectively represent three FPGA devices, D is elementary item score value, and E is addition Item score value, and R is the threshold of setting
Value, might as well set DA≤DB≤DC。
(1) if DB-DA>=R and DC-DB>=R, then C is evaluation the 1st, and B is evaluation the 2nd, and A is evaluation the 3rd, is not necessarily to
Carry out addition Item evaluation；
(2) if DB-DA>=R and DC-DB< R, then A is evaluation the 3rd.B and C carry out addition Item evaluation again, and evaluation rule is such as
Under:
If EB+DB<EC+DC, then C is evaluation the 1st, and B is evaluation the 2nd；
If EB+DB>EC+DC, then B is evaluation the 1st, and C is evaluation the 2nd；
If EB+DB=EC+DC, 2 kinds of situations can be divided to be determined at this time:
If A, DC>DB, then C is evaluation the 1st, and B is evaluation the 2nd；
If B, DC=DB, then B and C is listed as evaluation the 1st, and A is identified as evaluation the 2nd at this time；
(3) if DB-DA< R and DC-DB>=R, then C is evaluation the 1st.A and B carry out addition Item evaluation again, and evaluation rule is such as
Under:
If EA+DA<EB+DB, then B is evaluation the 2nd, and A is evaluation the 3rd；
If EA+DA>EB+DB, then A is evaluation the 2nd, and B is evaluation the 3rd；
If EA+DA=EB+DB, 2 kinds of situations can be divided to be determined at this time:
If A, DB>DA, then B is evaluation the 2nd, and A is evaluation the 3rd；
If B, DB=DA, then A and B is listed as evaluation the 2nd；
(4) if DB-DA< R and DC-DB< R, evaluation schematic diagram at this time as shown in figure 5, can point following two situation begged for
By:
If DC-DA< R, then A, B, C carry out addition Item evaluation, evaluate according to the following rules at this time:
1), elementary item and addition Item total score are highest to evaluate the 1st, and elementary item and addition Item total score are minimum for evaluation
3rd, elementary item and addition Item total score are that intermediate score value is evaluation the 2nd；
2) if E, occursA+DA=EB+DB=EC+DC, then three FPGA device comprehensive performances are listed as evaluation the 1st；
3) if certain two FPGA device elementary item, occurs and addition Item total score is identical, and its value is than third man FPGA
Device elementary item and addition Item total score want high, then this two FPGA devices are listed as evaluation the 1st, and third man FPGA device is
Evaluate the 2nd；
4) if certain two FPGA device elementary item, occurs and addition Item total score is identical, and its total score is than third family
FPGA device elementary item and addition Item total score want low, then this two FPGA devices are listed as evaluation the 2nd, third man FPGA device
Part is evaluation the 1st；
DC-DA>=R can be divided into two kinds of situations at this time and discuss:
If 1), DB-DA≤0.5×(DC-DA), then C is evaluation the 1st, and A and B carry out addition Item evaluation, evaluation rule again
It is as follows:
If 2), EA+DA<EB+DB, then B is evaluation the 2nd, and A is evaluation the 3rd；
If 3), EA+DA>EB+DB, then A is evaluation the 2nd, and B is evaluation the 3rd；
If 4), EA+DA=EB+DB, 2 kinds of situations can be divided to be determined at this time:
If DB>DA, then B is evaluation the 2nd, and A is evaluation the 3rd；
If DB=DA, then A and B is listed as evaluation the 2nd；
If 5), DB-DA>0.5×(DC-DA), then A is evaluation the 3rd, and B and C carry out addition Item evaluation again, and evaluation rule is such as
Under:
If EB+DB<EC+DC, then C is evaluation the 1st, and B is evaluation the 2nd；
If EB+DB>EC+DC, then B is evaluation the 1st, and C is evaluation the 2nd；
If EB+DB=EC+DC, 2 kinds of situations can be divided to be determined at this time:
If DC>DB, then C is evaluation the 1st, and B is evaluation the 2nd；
If DC=DB, then B and C is listed as evaluation the 1st, and A is identified as evaluation the 2nd at this time；
Decision condition 6 is described as follows:
If A, B respectively represents any two FPGA devices, D is the evaluation and test score value of elementary item, and E is the evaluation and test point of addition Item
Value, R are the threshold value of setting.Without loss of generality, D might as well be setA≤DB。
(1) if DB-DA>=R, then B is evaluation the 2nd, and A is evaluation the 3rd, without carrying out addition Item evaluation；
(2) if DB-DA< R, then A and B carries out addition Item evaluation, and evaluation rule is as follows:
If EB+DB<EA+DA, then A is evaluation the 2nd, and B is evaluation the 3rd；
If EB+DB>EA+DA, then B is evaluation the 2nd, and A is evaluation the 3rd；
If EB+DB=EA+DA, 2 kinds of situations can be divided to be determined at this time:
If DB>DA, then B is evaluation the 2nd, and A is evaluation the 3rd；
If DB=DA, then A and B is listed as evaluation the 2nd；
Decision condition 7 is described as follows:
If A, B respectively represents any two FPGA devices, D is the evaluation and test score value of elementary item, and E is the evaluation and test point of addition Item
Value, R are the threshold value of setting.Without loss of generality, D might as well be setA=DBAnd EA≤EB。
(1) if EB>EA, then B is evaluation the 1st, and A is evaluation the 2nd；
(2) if EB=EA, then A and B is listed as evaluation the 1st, and C can be regarded as evaluation the 2nd at this time；
Decision condition 8 is described as follows:
If A, B, C respectively represent three FPGA devices, D is the evaluation and test score value of elementary item, and E is the evaluation and test score value of addition Item, R
For the threshold value of setting.Without loss of generality, D might as well be setA=DB=DCAnd EA≤EB≤EC。
(1) if EA<EB<EC, then C is evaluation the 1st, and B is evaluation the 2nd, and A is evaluation the 3rd；
(2) if EC>EBAnd EB=EA, then C is evaluation the 1st, and A and B are listed as evaluation the 2nd；
(3) if EB>EAAnd EB=EC, then B and C is listed as evaluation the 1st, and A is evaluation the 2nd；
(4) if EA=EB=EC, then A, B and C are listed as evaluation the 1st；
In above-mentioned each decision condition, R is the threshold value set in the invention patent, and the size of value is dependent on specifically
Application demand (2%-5% for being such as set as total score).By carrying out ranking evaluation to different FPGA devices, it can select
Optimal FPGA device.
A kind of comprehensive performance evaluation device of integrated circuit, includes: parameter acquisition module 601 as shown in Figure 6, is based on threshold value
Evaluation module 602, sorting module 603 and evaluation module 604.
Parameter acquisition module 601, the measured value of the relevant parameter for obtaining N number of to-be-measured integrated circuit, and based on measurement
Value obtains elementary item score value and addition Item score value.
Sorting module 603, for calling and being based on threshold when the elementary item score value of each to-be-measured integrated circuit is both less than reference value
The evaluation module 602 of value is ranked up each to-be-measured integrated circuit to obtain final ranking results；
Evaluation module 604, for the evaluation result based on final ranking results output integrated performance；
Evaluation module based on threshold value includes pre-ranking module 6021 and adjustment module 6022.
Pre-ranking module 6021, for being sorted in advance according to the elementary item score value of each to-be-measured integrated circuit；
Module 6022 is adjusted, the difference of the elementary item score value for two to-be-measured integrated circuits of arbitrary neighborhood after pre- sequence
When value is less than preset threshold, elementary item score value and addition Item score value based on two to-be-measured integrated circuits carry out pre- ranking results
Adjustment obtains ranking results.
The comprehensive performance evaluation device of above-mentioned integrated circuit is both less than joined in the elementary item score value of each to-be-measured integrated circuit
When examining value, each to-be-measured integrated circuit is ranked up using the evaluation method of threshold value, specifically, first by each to-be-measured integrated circuit root
It is ranked up according to elementary item score value, when the difference of two adjacent to-be-measured integrated circuits is less than preset threshold, in conjunction with elementary item
Score value and addition Item score value are adjusted pre- ranking results, have comprehensively considered the elementary item of integrated circuit and the shadow of addition Item
It rings, keeps the evaluation of integrated circuit more practical, reasonable, comprehensive and objective.
In another embodiment, sorting module 603 are also used in each to-be-measured integrated circuit, M to-be-measured integrated circuit
Elementary item score value be equal to reference value when, M to-be-measured integrated circuit is ranked up to obtain first part according to addition Item score value
Ranking results；N-M to-be-measured integrated circuit for calling the evaluation module based on threshold value to be less than reference value to elementary item score value carries out
Sequence obtains second part ranking results；It is obtained according to first part's ranking results and second part ranking results each to be measured integrated
The final ranking results of circuit；Wherein M < N.
In another embodiment, sorting module 603 are also used to be equal in the elementary item score value of each to-be-measured integrated circuit
When reference value, to-be-measured integrated circuit is ranked up according to addition Item score value to obtain final ranking results.
In another embodiment, in advance sequence the elementary item score value based on to-be-measured integrated circuit to be detected from as low as greatly into
Row；Adjustment module 6022 is for the latter to-be-measured integrated circuit in two to-be-measured integrated circuits of arbitrary neighborhood after sequence with before
When the difference of the elementary item score value of one to-be-measured integrated circuit is less than preset threshold, if the elementary item of previous to-be-measured integrated circuit
The sum of score value and addition Item score value then exists greater than the elementary item score value of the to-be-measured integrated circuit of the latter and the sum of addition Item score value
The position of both exchanges in pre- ranking results.
In another embodiment, adjustment module 6022 is also used to the elementary item score value in two neighboring to-be-measured integrated circuit
With it is addition Item score value and identical when, if the elementary item score value of two to-be-measured integrated circuits is equal, two to-be-measured integrated circuits
Sequence in pre- sequence is arranged side by side.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of comprehensive performance evaluation method of integrated circuit characterized by comprising
It obtains the measured value of the relevant parameter of N number of to-be-measured integrated circuit, and elementary item score value and attached is obtained based on the measured value
Plus item score value, the elementary item indicate the parameter item and its index that meet FPGA device basic function and performance requirement, characterization
Be normal value that whether FPGA device reaches design requirement, the addition Item indicates the related parameter of the FPGA device
It can be obtained better performance index value under the premise of meeting basic function and performance requirement, characterization is the FPGA
Device exceeds the surplus of design requirement normal value；
If the elementary item score value of each to-be-measured integrated circuit is both less than reference value, using the evaluation method based on threshold value to described each
To-be-measured integrated circuit is ranked up to obtain final ranking results；
Evaluation result based on the final ranking results output integrated performance；
The evaluation method based on threshold value the following steps are included:
It is sorted in advance according to the elementary item score value of each to-be-measured integrated circuit；
If the difference of the elementary item score value of two to-be-measured integrated circuits of arbitrary neighborhood after pre- sequence is less than preset threshold, it is based on
The elementary item score value and addition Item score value of two to-be-measured integrated circuits are adjusted pre- ranking results to obtain ranking results, described
The otherness that preset threshold characterizes different to-be-measured integrated circuits is horizontal；
If the elementary item score value of M to-be-measured integrated circuit is equal to the reference value in each to-be-measured integrated circuit, then execute with
Lower step:
It is ranked up the M to-be-measured integrated circuit to obtain first part's ranking results according to addition Item score value；
Using the evaluation method based on threshold value to elementary item score value be less than the N-M to-be-measured integrated circuits of the reference value into
Row sequence obtains second part ranking results；
The final row of each to-be-measured integrated circuit is obtained according to first part's ranking results and the second part ranking results
Sequence result；Wherein M < N.
2. the method according to claim 1, wherein if the elementary item score value of each to-be-measured integrated circuit is equal to institute
Reference value is stated, then the to-be-measured integrated circuit is ranked up according to addition Item score value to obtain final ranking results.
3. the method according to claim 1, wherein the pre- base of the sequence based on the integrated circuit to be detected
The as low as big progress certainly of this item score value；
If the latter to-be-measured integrated circuit and previous integrated electricity to be measured in two to-be-measured integrated circuits of arbitrary neighborhood after sequence
The difference of the elementary item score value on road is less than preset threshold, the elementary item score value and addition Item based on two to-be-measured integrated circuits
The step of score value is adjusted pre- ranking results include:
If the sum of the elementary item score value of previous to-be-measured integrated circuit and addition Item score value is greater than the to-be-measured integrated circuit of the latter
Elementary item score value and addition Item score value sum, then in pre- ranking results exchange both position.
4. according to the method described in claim 3, it is characterized in that, two neighboring to-be-measured integrated circuit elementary item score value and
When addition Item score value and identical, if the elementary item score value of two to-be-measured integrated circuits is equal, two to-be-measured integrated circuits exist
Sequence in pre- sequence is arranged side by side.
5. a kind of comprehensive performance evaluation device of integrated circuit characterized by comprising parameter acquisition module, based on threshold value
Evaluation module, sorting module and evaluation module；
The parameter acquisition module, the measured value of the relevant parameter for obtaining N number of to-be-measured integrated circuit, and it is based on the measurement
Value obtains elementary item score value and addition Item score value, and the elementary item indicates the ginseng for meeting FPGA device basic function and performance requirement
Several and its index, what is characterized is the normal value whether FPGA device reaches design requirement, and the addition Item indicates institute
Stating the related parameter of FPGA device can be obtained better performance index under the premise of meeting basic function and performance requirement
Value, characterization is surplus of the FPGA device beyond design requirement normal value；
The sorting module, for being based on described in calling when the elementary item score value of each to-be-measured integrated circuit is both less than reference value
The evaluation module of threshold value is ranked up to obtain final ranking results to each to-be-measured integrated circuit；
The evaluation module, for the evaluation result based on the final ranking results output integrated performance；
The evaluation module based on threshold value includes pre-ranking module and adjustment module；
The pre-ranking module, for being sorted in advance according to the elementary item score value of each to-be-measured integrated circuit；
The difference of the adjustment module, the elementary item score value for two to-be-measured integrated circuits of arbitrary neighborhood after pre- sequence is small
When preset threshold, elementary item score value and addition Item score value based on two to-be-measured integrated circuits are adjusted pre- ranking results
Ranking results are obtained, the otherness that the preset threshold characterizes different to-be-measured integrated circuits is horizontal；
The sorting module is also used in each to-be-measured integrated circuit, and the elementary item score value of M to-be-measured integrated circuit is equal to
When the reference value, it is ranked up the M to-be-measured integrated circuit to obtain first part's ranking results according to addition Item score value；
The N-M to-be-measured integrated circuits for calling the evaluation module based on threshold value to be less than the reference value to elementary item score value are arranged
Sequence obtains second part ranking results；According to first part's ranking results and the second part ranking results obtain respectively to
Survey the final ranking results of integrated circuit；Wherein M < N.
6. device according to claim 5, which is characterized in that the sorting module is also used in each to-be-measured integrated circuit
Elementary item score value when being equal to the reference value, the to-be-measured integrated circuit is ranked up to obtain most according to addition Item score value
Whole ranking results.
7. device according to claim 5, which is characterized in that the pre- base of the sequence based on the integrated circuit to be detected
The as low as big progress certainly of this item score value；The adjustment module is for latter in two to-be-measured integrated circuits of arbitrary neighborhood after sequence
When the difference of the elementary item score value of a to-be-measured integrated circuit and previous to-be-measured integrated circuit is less than preset threshold, if it is previous to
Survey integrated circuit elementary item score value and addition Item score value sum greater than the latter to-be-measured integrated circuit elementary item score value and
The sum of addition Item score value then exchanges the position of the two in pre- ranking results.
8. device according to claim 7, which is characterized in that the adjustment module is also used to two neighboring to be measured integrated
When the elementary item score value of circuit and addition Item score value and identical, if the elementary item score value of two to-be-measured integrated circuits is equal,
Sequence of two to-be-measured integrated circuits in pre- sequence is arranged side by side.
9. a kind of computer equipment, including memory and processor, the memory are stored with computer program, feature exists
In the step of processor realizes any one of claims 1 to 4 the method when executing the computer program.
10. a kind of computer readable storage medium, is stored thereon with computer program, which is characterized in that the computer program
The step of method described in any one of Claims 1-4 is realized when being executed by processor.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101650746A (en) * | 2009-09-27 | 2010-02-17 | 中国电信股份有限公司 | Method and system for verifying sequencing results |
| CN104639389A (en) * | 2014-12-31 | 2015-05-20 | 北京奇虎科技有限公司 | Router evaluating device and method |
| CN105243923A (en) * | 2015-11-10 | 2016-01-13 | 广西职业技术学院 | Data sorting process dynamic implementation method for teaching demonstration |
| CN105701735A (en) * | 2016-04-07 | 2016-06-22 | 国网甘肃省电力公司电力科学研究院 | Loss reduction potential estimation method and device for power distribution network |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE60023258D1 (en) * | 2000-01-18 | 2005-11-24 | St Microelectronics Srl | Method for testing a CMOS integrated circuit |
| CN102116841B (en) * | 2011-01-04 | 2014-09-03 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101650746A (en) * | 2009-09-27 | 2010-02-17 | 中国电信股份有限公司 | Method and system for verifying sequencing results |
| CN104639389A (en) * | 2014-12-31 | 2015-05-20 | 北京奇虎科技有限公司 | Router evaluating device and method |
| CN105243923A (en) * | 2015-11-10 | 2016-01-13 | 广西职业技术学院 | Data sorting process dynamic implementation method for teaching demonstration |
| CN105701735A (en) * | 2016-04-07 | 2016-06-22 | 国网甘肃省电力公司电力科学研究院 | Loss reduction potential estimation method and device for power distribution network |
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