CN106599516A - Method and device for automatically generating test vectors based on circuit board - Google Patents
Method and device for automatically generating test vectors based on circuit board Download PDFInfo
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- CN106599516A CN106599516A CN201611259391.4A CN201611259391A CN106599516A CN 106599516 A CN106599516 A CN 106599516A CN 201611259391 A CN201611259391 A CN 201611259391A CN 106599516 A CN106599516 A CN 106599516A
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
The invention discloses a method and a device for automatically generating test vectors based on a circuit board. Input design of circuits and input design of other hardware are converted into unified RTL (Register Transfer Level) design, then the RTL design is converted into a specific software model (LLVM Bytecode) which can be accepted by a symbolic execution tool, then optimization and matching for the test vectors and test paths are carried out by using the symbolic execution tool and combining artificial intelligence algorithms such as particle swarms, and various test vectors are generated, so that the problem that the circuit board cannot be tested based on symbolic execution in the prior art is effectively solved.
Description
Technical field
The present invention relates to circuit testing technology field, more particularly to a kind of automatic test vector generation side based on circuit board
Method and device.
Background technology
Semiology analysis are the program analysis theories of a kind of important formalization and automatization, are that a kind of generation can cover spy
Determine the method model of execution route test case, can be combined with each other with the abstract and reasoning of program, model inspection scheduling theory,
The aspects such as automatic test, defects detection, the verification and validation of program, the correctness proof of program have preferable application prospect.
At present, semiology analysis have been widely used for Generation of software test case and achieve good effect.
For hardware circuit design, the present invention needs quickly and efficiently to generate test vector to detect hardware designs and carry
The code coverage of high hardware designs.But, circuit board can not be tested by semiology analysis at present, therefore, such as
What can carry out test based on semiology analysis to circuit board becomes now the urgently technical issues that need to address.
The content of the invention
In view of above-mentioned analysis, the present invention is intended to provide a kind of automatic test vector generation method and dress based on circuit board
Put, with solving the problems, such as to be tested circuit board based on semiology analysis in prior art.
To solve the above problems, the present invention is mainly achieved through the following technical solutions：The invention provides a kind of base
In the automatic test vector generation method of circuit board, the method includes：The circuit design and hardware designs of input are converted to into system
One RTL design；RTL design is converted to can be by the software model of semiology analysis instrument；By semiology analysis instrument and combine
Intelligent algorithm carries out the optimizing of test vector and test path and matches, and generates test vector.
Further, the method also includes：The test vector of generation is combined into RTL design, application hardware design and simulation is soft
Part is emulated, and generates corresponding test vector coverage rate report, and to test vector entry evaluation is carried out.
Further, the test vector of generation is combined into RTL design, application hardware design and simulation software is emulated, is had
Body includes：
The test vector that semiology analysis are generated is carried out into driving simulation software, is emulated by calling Modelsim engine implementations,
Calculate the reachable coverage rate of test vector.
Further, also include:
Require when the test vector for generating is unsatisfactory for coverage rate, then line parameter is entered by intelligent algorithms such as populations and sought
To meet coverage rate requirement, particle cluster algorithm includes excellent or manual modification parameter：
Particle cluster algorithm realizes that step is as follows：
The initialization test vector produced using symbolic excution methodology；
Test vector is generated at random particle initial population using particle cluster algorithm；
According to test vector, the faulty adaptive value of institute in circuit-under-test is calculated, select of wherein adaptive value maximum
Failure is used as target faults.And the vector that can evoke the failure is all added in a set E；
Initialization population；
Calculate the adaptive value corresponding to each test vector in population；
The setting of optimal location；
Particle of future generation is generated according to particle cluster algorithm evolution equation；
Calculate the adaptive value corresponding to test vector；
Adaptive value corresponding to each test vector is compared with the adaptive value of the desired positions for being experienced, by the two
Larger one is used as current desired positions；
Adaptive value corresponding to each test vector is compared with the adaptive value of the global desired positions for being experienced, will
In the two larger one as current global desired positions；
Such as not up to default maximum generation, then go back to (g) step；Optimal vector is otherwise generated, into next step；
All failures being detected are deleted from bug list；
Whether failure judgement table is empty (check whether in bug list faulty be all detected), if it is empty,
Then algorithm terminates；Otherwise, (b) step is returned.
Require when the test vector for generating meets, test vector is converted into the file that correspondence meets IEEE1445 standards,
And be applied on hardware and emulated, by the detection to excitation, input and output pin etc., the test arrow that further assessment is generated
Amount.
Further, the circuit design and hardware designs of input are converted to into unified RTL design, are specifically included：Pass through
The circuit design and hardware designs of input are converted to the unified RTL design based on VHDL language by VHDL crossover tools.
On the other hand, present invention also offers a kind of automatic test vector generation device based on circuit board, the device bag
Include：
Converting unit, for the circuit design and hardware designs of input to be converted to into unified RTL design, by RTL design
Being converted to can be by the software model of semiology analysis instrument；
Processing unit, for carrying out test vector and test path by semiology analysis instrument and with reference to intelligent algorithm
Optimizing with match, generate test vector.
Further, the device also includes：Simulation unit, for the test vector of generation to be combined into RTL design, application is hard
Part design and simulation software is emulated, and generates corresponding test vector coverage rate report, and to test vector entry evaluation is carried out.
Further, the simulation unit is additionally operable to, and the test vector that semiology analysis are generated is come into driving simulation software, leads to
Cross and call Modelsim engine implementations to emulate, calculate the reachable coverage rate of test vector.
Further, the simulation unit is additionally operable to, and requires when the test vector for generating is unsatisfactory for coverage rate, then by people
Work intelligent algorithm carries out parameter optimization or manual modification parameter to meet coverage rate requirement；Want when the test vector for generating meets
Ask, test vector is converted into correspondence and meets the file of IEEE1445 standards, and is applied on hardware and is emulated, by swashing
Encourage, the detection of input and output pin etc., the test vector that further assessment is generated.
Further, the converting unit is additionally operable to, and is set the circuit design and hardware of input by VHDL crossover tools
Meter is converted to the unified RTL design based on VHDL language.
The present invention has the beneficial effect that：
The present invention is converted into by the circuit design (Protel net meter files) being input into and other hardware designs of input
Unified RTL (Register Transfer Level, Method at Register Transfer Level) designs, RTL design is further converted to can be by symbol
The receptible specific software model (LLVM Bytecode) of execution instrument institute, and then using semiology analysis instrument and combine grain
The intelligent algorithms such as subgroup carry out the optimizing of test vector and test path and match, and generate various test vector, so as to
Efficiently solve the problems, such as to be tested circuit board based on semiology analysis in prior art.
Other features and advantages of the present invention will illustrate in the following description, and partial become from description
It is clear that or being understood by implementing the present invention.The purpose of the present invention and other advantages can by the description write,
Specifically noted structure is realizing and obtain in claims and accompanying drawing.
Description of the drawings
Fig. 1 is a kind of schematic flow sheet of automatic test vector generation method based on circuit board of the embodiment of the present invention；
Fig. 2 is embodiment of the present invention particle cluster algorithm schematic flow sheet；
Fig. 3 is that design input unification is changed into Verilog HDL schematic diagrams by the embodiment of the present invention；
Fig. 4 is embodiment of the present invention Verilog code transformational relation figure；
Fig. 5 is embodiment of the present invention Verilog editing interface figure；
Fig. 6 is the stage schematic diagram of embodiment of the present invention traditional static compiler；
Fig. 7 is the three phases design diagram of embodiment of the present invention LLVM；
Fig. 8 is embodiment of the present invention model conversion interface schematic diagram；
Fig. 9 is that the embodiment of the present invention generates driving function schematic diagram；
Figure 10 is embodiment of the present invention coverage rate report schematic diagram；
Figure 11 is embodiment of the present invention software deployment schematic diagram；
Figure 12 is that a kind of structure of automatic test vector generation device based on circuit board according to embodiments of the present invention is shown
It is intended to.
Specific embodiment
Below in conjunction with the accompanying drawings specifically describing the preferred embodiments of the present invention, wherein, accompanying drawing constitutes the application part, and
It is used to together with embodiments of the present invention explain the principle of the present invention.For purpose of clarity and simplification, when it may make the present invention
Theme it is smudgy when, illustrating in detail for known function and structure in device described herein will be omitted.
The invention provides a kind of automatic test vector generation method and device based on circuit board, the present invention is by input
Circuit design (Protel net meter files) and input other hardware designs be converted into unified RTL design, RTL design enters
And being converted to by the receptible specific software model (LLVM Bytecode) of semiology analysis instrument institute, and then can utilize symbol
Execution instrument simultaneously carries out the optimizing of test vector and test path and matches with reference to intelligent algorithms such as populations, generates various
Test vector.Below in conjunction with accompanying drawing and several embodiments, the present invention will be described in further detail.It should be appreciated that this
The described specific embodiment in place limits the present invention only to explain the present invention, not.
Embodiment of the method
A kind of automatic test vector generation method based on circuit board is embodiments provided, referring to Fig. 1, the method
Including：
The circuit design and hardware designs of input are converted to into unified RTL design；
RTL design is converted to can be by the software model of semiology analysis instrument；
Carry out the optimizing of test vector and test path and match by semiology analysis instrument and with reference to intelligent algorithm,
Generate test vector.
That is, the present invention is by the circuit design (Protel net meter files) of input and other hardware designs of input
Unified RTL (Register Transfer Level, Method at Register Transfer Level) designs are converted into, RTL design is further converted to
Can be by the receptible specific software model (LLVM Bytecode) of semiology analysis instrument institute, and then using semiology analysis instrument
And carry out the optimizing of test vector and test path and match with reference to intelligent algorithms such as populations, generate various test arrow
Amount.Circuit board can not be tested based on semiology analysis in so as to efficiently solve the problems, such as prior art.
That is, the present invention when generate test vector be unsatisfactory for coverage rate require when, then by population et al.
Work intelligent algorithm carries out parameter optimization or manual modification parameter to meet coverage rate requirement, particle cluster algorithm flow chart such as Fig. 2 institutes
Show, specifically include：
Particle cluster algorithm realizes that step is as follows：
The initialization test vector produced using symbolic excution methodology；
Test vector is generated at random particle initial population using particle cluster algorithm；
According to test vector, the faulty adaptive value of institute in circuit-under-test is calculated, select of wherein adaptive value maximum
Failure is used as target faults.And the vector that can evoke the failure is all added in a set E；
Initialization population；
Calculate the adaptive value corresponding to each test vector in population；
The setting of optimal location；
Particle of future generation is generated according to particle cluster algorithm evolution equation；
Calculate the adaptive value corresponding to test vector；
Adaptive value corresponding to each test vector is compared with the adaptive value of the desired positions for being experienced, by the two
Larger one is used as current desired positions；
Adaptive value corresponding to each test vector is compared with the adaptive value of the global desired positions for being experienced, will
In the two larger one as current global desired positions；
Such as not up to default maximum generation, then go back to (g) step；Optimal vector is otherwise generated, into next step；
All failures being detected are deleted from bug list；
Whether failure judgement table is empty (check whether in bug list faulty be all detected), if it is empty,
Then algorithm terminates；Otherwise, (b) step is returned.
When being embodied as, the method described in the embodiment of the present invention also includes：The test vector of generation is combined into RTL design,
Application hardware design and simulation software is emulated, and generates corresponding test vector coverage rate report, and test vector is carried out tentatively
Assessment.
The test vector of generation is combined RTL design by the embodiment of the present invention, and application hardware design and simulation software is emulated,
Specifically include：
The test vector that semiology analysis are generated is carried out into driving simulation software, is emulated by calling Modelsim engine implementations,
Calculate the reachable coverage rate of test vector.
The embodiment of the present invention also includes:Require when the test vector for generating is unsatisfactory for coverage rate, then calculated by artificial intelligence
Method carries out parameter optimization or manual modification parameter to meet coverage rate requirement；
Require when the test vector for generating meets, test vector is converted into the file that correspondence meets IEEE1445 standards,
And be applied on hardware and emulated, by the detection to excitation, input and output pin etc., the test arrow that further assessment is generated
Amount.
When being embodied as, the circuit design and hardware designs of input are converted to into unified RTL described in the embodiment of the present invention
Design, specifically includes：The circuit design and hardware designs of input are converted to by VHDL crossover tools unified based on VHDL
The RTL design of language.
Detailed explanation and explanation is carried out to method of the present invention below in conjunction with Fig. 3 to Figure 11：
The circuit design (Protel net meter files) of input and other hardware designs of input are converted into unified RTL and set
Meter, RTL design further be converted to can by semiology analysis instrument receptible specific software model (LLVM Bytecode),
And then using semiology analysis instrument and with reference to the intelligent algorithms such as population carry out the optimizing of test vector and test path with
Matching, generates various test case.The test case of generation is entered with reference to RTL design file application hardware design and simulation software
Row emulation, generates corresponding test case coverage rate report, and to test vector entry evaluation is carried out.If the test vector for generating
Coverage rate requirement is unsatisfactory for, then to carry out parameter optimization or manual modification parameter by intelligent algorithm will to meet coverage rate
Ask；If the test vector for generating meets required, test case is converted into correspondence and meets IEEE1445 standards (complex digital electricity
Drive test tries exchange format) file, and then be applied on hardware and emulated, by the inspection to excitation, input and output pin etc.
Survey, the test vector that further assessment is generated.
Test vector generates methods and techniques used and is largely divided into four broad aspects：Circuit design to software model is changed,
Semiology analysis, RTL Simulation Evaluations, hardware verification.
System input includes Protel net meter files and chip RTL design.Protel is retouched there is provided an efficient hardware
The design tool of predicate speech, it supports two separate modes of design：Both file can be directly write using VHDL language,
Can be by drawing principle figure direct compilation into VHDL files.It is graphically relatively more directly perceived, it is readily appreciated that, easily realize.
With the mode of language, the mode such as non-graphic describes hardware circuit, is easily modified, and easily preserves.The system supports two ways,
Both user input and editor's Protel net meter files had been allowed, the chip RTL of user input and editor based on VHDL language had also been allowed
Design.
As shown in figure 3, once user completes Protel net meter files and RTL design, it is possible to use VHDL crossover tools
Protel net meter files and RTL design are converted to into the unified RTL design based on VHDL language.
At present, semiology analysis instrument can only support that based on the RTL design of Verilog this method utilizes existing instrument (for example
X-HDL, Synaptics Tools), conversion is the RTL design based on Verilog of equal value based on the RTL design of VHDL language,
Design after conversion can be emulated and tested with RTL simulation softwares (Modelsim).
As shown in figure 4, the Verilog code for generating, by being used as crossover tool using Verilator, further conversion
Into C++ codes.Verilator be one be used for Verilog design emulator, can change Verilog code to C
++/SystemC codes.Verilator is not simply to change Verilog into C++/SystemC, its generation simultaneously to generating
Code is optimized, and then the code of generation is fast and effeciently performed.In the method, the work(of Verilator is borrowed
Verilog code can be changed into C++ codes.
As shown in figure 5, the present invention provides the user a graphic interface carries out the editor of Verilog design, while with
Family by critical transition Verilog design to corresponding C++ files, and can be browsed and edited to file, be passed through
C++ files after Verilator conversions are called in order to user and operate there is provided direct interface.It is all of
Verilog design and corresponding C++ files will be stored under same engineering catalogue.
The later C++ codes of conversion directly can not be received by semiology analysis instrument, be needed further with LLVM frames
Frame changes C++ codes to required intermediary bytes code.
LLVM is the abbreviation of Low Level Virtual Machine (low level virtual machine), is in fact a compiler frame
Frame.LLVM cannot completely represent this project with the continuous development of this project, and simply this call is always
Continuity is got off.LLVM is a project increased income.It is a research project of Illinois when it is earliest, chief leading cadre
It is Chris Lattner, he takes office in Apple now.Apple is also at present one of main sponsor of LLVM projects.LLVM
Main Function be that it can be used as the rear end of polyglot, it can provide the unrelated optimization of programmable language and for a lot
Plant the code building function of CPU.In addition LLVM has been not only at present a programming framework, and it further comprises at present many sons
Project, such as the most clang of great reputation.The advantage of LLVM is to increase income, and has the good IR language of expression-form, and module is turned into
It is especially good.LLVM this framework has had at present can be used based on the substantial amounts of instrument of this framework.LLVM can be carried out
The compiling duration optimization of program language, link optimized, compiled online optimization, code building.The project of LLVM be a modularity and
The set of reusable compiler and tool technique.
Before LLVM IR are introduced, the structure for taking off LLVM has been needed first.Traditional static compiler is divided into three phases
Such as Fig. 6 and Fig. 7：Front end, optimization and rear end.Advantage of this is that and support a kind of new programming language if desired, then only
Need to realize a kind of new front end.A kind of new hardware device is supported if desired, and that only needs to realize a new rear end.And
Optimizing phase, it was a general stage, whether supports new programming language because being to have been directed to unified LLVM IR
Speech, or new hardware device is supported, all the optimizing phase need not be made an amendment here.So LLVM it can be seen
The effect of IR.LLVM IR mainly have three kinds of forms：A kind of is the compiler intermediate language in internal memory；One kind is stored on hard disk
Binary system intermediate language (with .bc endings), it is last it is a kind of be readable intermediate form (with .ll endings).Layout in these three
Formula is essentially equal.LLVM IR are LLVM optimizations and the key for carrying out code building.According to readable IR, it is known that again
Before ultimately generating object code, which type of code is the present invention generated.And according to IR, the present invention can select to make
Different executable codes are generated with different rear ends.Meanwhile, because having used unified IR, the present invention can be reused
The optimization function of LLVM, even if the present invention uses self-designed programming language.In the method, turned using LLVM frameworks
C++ codes are changed to required LLVM bytecodes (including with .bc endings and with .ll two kinds of forms of ending).
The characteristics of code of LLVM is represented is to provide supports the complicated program high-level information analyzed and change, such as type,
Again random procedure can be represented simultaneously, and support various optimizations.The abstract key operation of general processor of the instruction set of LLVM,
Avoid the specific part of machine, such as physical register, streamline etc. simultaneously.LLVM instruction set is fairly simple, only 31
Operation code, most instructions are the forms of three-address code.LLVM includes countless multiple virtual registers for having a type, these depositors
The data (boolean, integer, floating number and pointer) of fundamental type can be preserved.Depositor is SSA in LLVM assembly codes
(Static Single Assignment) form.Core position is not SSA form, and reason is, pointer may point to many
Individual core position.In LLVM assembly codes, the CFG (Control Flow Graph) of function is constructed out, this point
It is particularly useful, because many static analyses depend on the CFG of function, including semiology analysis.Here the node of CFG is basic block
(basic block), rather than single statement.Data in LLVM assembly codes have the type of determination, and it provides a language
Independent type system, including four simple types：Void, boolean, integer and floating number, and four derived types：Pointer,
Array, structure and function.This simple type system can realize the type of most high-level languages, such as, in C++
Class can use the combination of the array of structure, function and function pointer to realize.Instruction getelementptr is used for realizing pointer
Arithmetic, it can calculate the address of the member of composite type (structure or array) data.Getelementptr is caused in LLVM
Subsidiary type information is possibly realized in assembly code.In the assembly code of LLVM, all of heap data is instructed using malloc
Storage allocation, return has type pointer.Data in all stacks instruct storage allocation using alloca, and returning has type to refer to
Pin.Global variable and function define the address of an execution corresponding object.So, all of addressable objects have finger
To its pointer, all of internal memory operation, including function call are performed by pointer.Internal memory and depositor it
Between carry out data transfer by load and store instructions doing.Another innovative point during the code of LLVM is represented is to make
The support to the abnormality processing in high-level language is realized with two instructions of invoke and unwind.This mechanism supports that one kind is taken out
As exception handling models, machine independence.
As shown in figure 8, the present invention provides the user a graphical boundary-face carries out the conversion of model, and allow user couple
File is browsed and edited, and the bytecode after LLVM conversions employs SSR forms.The byte code files of all generations will
Under being stored in same engineering catalogue.
Verilog design is changed into into corresponding LLVM bytecodes, Verilog examples given above may finally be turned
It is changed to following LLVM bytecodes.
Semiology analysis are a kind of method for generating test case of path-oriented, and the target to be reached is automatically generated can be held
The corresponding test case of all reachable paths of line program.KLEE generates the very capable of test case using semiology analysis, can be with
Be considered at present best semiology analysis instrument of increasing income, it can automatic Data Generation Test, the test data can be multiple at one
High coverage rate is realized in the miscellaneous various and intensive program of context.KLEE is had been applied in GNU COREUTIL practicality external members
All of 89 independent programs, these programs are installed on ten hundreds of Unix systems, and can be described as existing
Single most important program test collection of increasing income.The test data that KLEE is generated has reached very high row coverage rate, average each work
Tool it is important that has defeated the code coverage of the hand-written test case of developer more than 90%.When KLEE is applied to
It is as a result more preferable when on 75 identical instruments of BUSYBOX embedded system external members, cover on 31 instruments wherein
Rate has reached 100%.Meanwhile, KLEE is an error-checking tool, except conventional code error, it is also possible to which audit function is wrong
By mistake.KLEE uses constraint solver STP, plays the operating system of process symbol process and the dual role of interpreter.KLEE
Internal memory is considered as multiple without type-byte array, is that each data object generates a single byte arrays.Without class type-word
Joint number group enables KLEE accurately to process the unsafe internal storage access of type.It is specific big that KLEE requires that data object has
It is little, so it can not support size uncertain data.KLEE can not direct supporting pointer, it is by one that it processes the method for pointer
Plant pile pitching method and determine the object that pointer is pointed to.For pointer dereference, first by a record variable to its byte arrays
Mapping table find pointer sensing the corresponding byte arrays of object, then calculate pointer relative to this byte arrays skew
Amount, finally accesses the element of array as subscript using side-play amount.Path condition is the constraint with regard to byte arrays, and array is carried out
Reasoning is the key of STP.STP ensure that its performance by being optimized to array reasoning.STP is one for quantifier-free one
The bit vector of rank logical formula form and the decision process of bit vector array linear arithmetic.STP provides three kinds of data types：Cloth
That, bit vector and bit vector array.Wherein, bit vector is the bit sequence of regular length.Meanwhile, STP supports that position connection and position carry
Extract operation, to support the memory model of KLEE.STP supports all of arithmetical operation, position level boolean operation and relational operation etc., generation
Predicate in code is converted into the constraint to bit vector.By a series of level conversions and the optimization for bit vector and array,
Bit vector constraint is converted into the formula of propositional logic of CNF normal form forms, then submits to a standard SAT solver judgement.
In the method, KLEE is applied to the LLVM bytecodes generation test case that the first step is obtained.KLEE is carried itself
Help generate test case for several test paths and the strategy of test case optimizing.KLEE provides four kinds and main searches
Rope is heuristic：
Depth-first search (DFS)：Ergodic state is in depth-first order.
Random manner is searched for：One state of random selection goes to explore.
Random walk is selected：One path of random selection is gone to explore.
The random search (Non Uniform Random Search, NURS) of non-uniform Distribution：Select a random shape
State is according to given distribution.Distribution can be based on to minimum range (the minimum distance to an for being not carried out instructing
Uncovered instruction, MD2U), query cost etc..The NURS strategies for having had six kinds of correlations at present are comprised in
In KLEE：
NURS-covnew：It is tactful using the NURS based on Coverage-New.
NURS-md2u：It is tactful using the NURS based on MD2U.
NURS-depth：It is tactful using the NURS based on 2^depth.
NURS-icnt：It is tactful using the NURS based on Instr-Count.
NURS-cpicnt：It is tactful using the NURS based on CallPath-Instr-Count.
NURS-qc：It is tactful using the NURS based on query cost.
The strategy of KLEE acquiescences is the Crossover Strategy of random walk selection and NURS-covnew.In the method, will adopt
The test path and the strategy of test case optimizing that KLEE is provided is tested, and calls STP to solve Symbolic Execution generation
Path restrictive condition so that generate test case.
In order to hardware designs are carried out with semiology analysis, the present invention also needs to generate corresponding main functions to drive hardware to set
Meter.One specific example is as shown in Figure 9.
By having carried out preliminary Test cases technology to the LLVM bytecodes generated based on finite state machine using KLEE,
Here the random walk initially with KLEE acquiescences selects the Crossover Strategy with NURS-covnew, 18 tests is generated altogether and is used
Example.
Here the test case for providing a KLEE generation is as follows：
It is as follows that the test case for changing KLEE acquiescence generations may be appreciated form by this method into user：
Corresponding Verilog design has two input input1 and input2, in this test case, by sending not
With data to input1 and input2 in continuous 4 clock cycle, so as to transfering state machine is to corresponding state.
Decide whether to develop new Test Strategy based on preliminary test result.Due to the LLVM that this method is provided
Bytecode is, so the Test Strategy of KLEE acquiescence differ surely obtain preferable effect converted next by a hardware designs
Really.It is the software of open source code based on KLEE, this method can develop more strategies.The spy designed by combined with hardware
Point, research and development meet the strategy of the Test cases technology of actual demand.
The test case that this method application semiology analysis are generated carrys out driving simulation software, by calling Modelsim engine realities
Now emulate, and then calculate the coverage rate that test case can reach, as shown in Figure 10.Modelsim code coverage functions Code
Coverage, can be reported out statement (sentence), branch (branch), condition (condition), expression (tables
Up to), toggle (signal upset), various coverage rate situations such as fsm (finite state machine).The Verilog that step one is obtained is set
Meter is emulated by Modelsim, can be step-wise execution by whole program, and making designer be immediately seen his program next step will hold
Capable sentence, and the currency of aleatory variable can be checked at any step any moment of Cheng Zhihang.
When Modelsim emulation is carried out, using Verilog procedural interfaces (Verilog Procedural
Interface, VPI) enter row data communication.VPI interfaces can make the behavioral scaling coded description of digital circuit directly invoke C language
Function, and the C language function used can also call the Verilog system tasks of standard.Verilog program structures are IEEE
A part for 1364 programming language interface standards.
Verilog procedural interfaces (Verilog Procedural Interface, VPI), are initially referred to as programming language
Interface (Program Language Interface, PLI) 2.0, is a Verilog procedural interface for C language.It can
So that the behavioral scaling coded description of digital circuit directly invokes the function of C language, and the C language function used can also call mark
Accurate Verilog system tasks.Verilog program structures are a parts for the programming language interface standards of IEEE 1364.It is newest
Version be 2005 update.VPI interfaces mainly provide following three kinds of functions.First, VPI interfaces permission user writes and makes by oneself
The system task and system function of justice.User writes out corresponding VPI programs and is connected to after emulator, it is possible to
These system task and function used in the verilog programs oneself write.Once these task/function
It is called in simulation process, emulator will find VPI programs that corresponding user writes to perform, so as to realize emulator
Customization.Secondly, v interfaces also allow user to carry out with the verilog hardware of instantiation in emulator in the VPI programs of oneself
Interaction, such as read the value of a wire, and to a row reg value is write, and arranges delay of a cell, etc..Say without exaggeration that, it is right
For VPI programs, the verilog examples in emulator are entirely transparent, and user wants to make these hardware what operation
Can be with.There is this function, user just can perform some and use verilog in self-defining task/function to hardware
Language is difficult to the operation for completing.Finally, some specific operations need to respond the change of some signals in simulation process.
Although the present invention can monitor the change of a small amount of signal with always, but if needing to monitor a large amount of signals, this mechanism is simultaneously
It is unrealistic.VPI interfaces solve this problem there is provided a kind of Function call-backing mechanism.User can be by signals such as certain wire/reg
The C function in a VPI program is hung up, later whenever the signal intensity, this C function all can be called, so as to easily
Realize signal monitoring.In fact, the system task for much beating waveform are realized with this method.Except described above
These mechanism outside, VPI can also allow user's control emulate process, such as suspend, exit, write information etc. toward in log files.Also
Can be with the data of gathering simulation process, such as current simulation time etc..These functions are same less not in actual PLI programs
.
Typical case's application of VPI mainly includes：
A) the common emulation of verilog models and C model is realized.Abroad, for more complicated system, developer Jing
Often need to make a C model that can be worked first, be then rewritten as verilog by module ground, so can realize
One comparison safety, progressive development process.Also some more complicated hardware cell storehouses, the floating point unit for especially customizing
Storehouse, its phantom is all C model, at this moment it is necessary that connecting two kinds of models with VPI.
B) test and excitation is produced, produces checking vector or directly verified.This be VPI programs it is the most frequently used be also main
Function.More complicated system is frequently necessary to determine next excitation according to the response of upper one excitation that this requires process
Control is made very well.But, everybody used verilog's both knows about, and the process control of verilog is very weak, it is difficult to
The programme-control of complexity is write out in testbench.And C has in this absolute advantage.Therefore, length can be taken using VPI
Benefit is short, realizes an efficient analogue system.
C) simulation process and result are captured, and is easy to be exported in the way of receiving by user.For a typical example, ripple is beaten
Shape is exactly this application.Give one example again, the present invention imitates a MPEG4 decoding chip, can output code flow VPI is real-time
After collection conversion, directly directly got on screen with the mode of real image, so the present invention just very directly perceived can must observe this
The effect of the hardware of invention design.
D) simulation process is analyzed, calculates performance parameter.Power consumption analysis are exactly the upset situation that each cell is noted down with VPI,
Then power consumption is calculated according to upset number of times.
E) software and hardware combined emulation.Now, the pure IC for working in hardware is few, when substantial amounts of IC works all
Need the participation and control of software.Leave these control softwares to be emulated, working environment is untrue, is likely to result in motivation model
Omission.If without VPI, the present invention just can only be controlled with verilog come the simulation softward in testbench, but verilog
The control of complexity may not described at all.Connect control software and emulator using PLI, the present invention just can simulate actual
Chip operation environment and process.There is an extra benefit in addition：Control software itself also can be adjusted in this process
Examination.
In the method for the invention, using VPI interfaces transmit test case to Verilog engineerings.Use this side
Method, can guarantee that substantial amounts of test case can pass to Verilog engineerings and carry out emulation and coverage rate calculating.Meanwhile, generation
Coverage rate report can feed back to the instrument of semiology analysis, go to instruct further Test cases technology, so move in circles, no
Break to improve coverage rate to reach requirement.
Can be seen that for general design from the coverage rate for obtaining, the generation that this method can be quickly is effectively tested
Use-case, reaches higher coverage rate.
DTIF data format requirements are provided according to company, the test case for generating is changed into DTIF files, and then instructs hard
Part is verified.By encouraging to circuit board, the detection of the signal such as input and output pin, the coverage rate of correlation can be calculated.
Software and deployment needed for this method is as shown in figure 11：User is designed Input Software Altium by this method
Designer 2013 and RTL simulation softwares Modelsim are deployed on windows platform, facilitate user to be input into and emulated.
Backstage semiology analysis engine and test vector generating portion are deployed in into Linux platform.Pass through network between two platforms
Socket is communicated.
Below whole flow process is introduced with an example, started to last from RTL design based on Verilog language
Test vector generate and test coverage statistics.
The design of this example describes a finite automata, for checking whether a serial input meets designated word
Symbol string.
Bytecode after conversion generates engine and receives as input by vector, generates efficient test vector following (below
Only one test vector example)：
The test vector of generation can further be used for RTL design emulation testing and actual hardware test.
Device embodiment
Embodiments provide a kind of automatic test vector generation device based on circuit board, referring to Figure 12, the dress
Put including：
Converting unit, for the circuit design and hardware designs of input to be converted to into unified RTL design, by RTL design
Being converted to can be by the software model of semiology analysis instrument；
Processing unit, for carrying out test vector and test path by semiology analysis instrument and with reference to intelligent algorithm
Optimizing with match, generate test vector.
When being embodied as, device of the present invention also includes:Simulation unit, the test vector for generating is combined
RTL design, application hardware design and simulation software is emulated, and corresponding test vector coverage rate report is generated, to test vector
Carry out entry evaluation.
Specifically, the simulation unit described in the embodiment of the present invention is additionally operable to, and the test vector of semiology analysis generation is driven
Dynamic simulation software, is emulated by calling Modelsim engine implementations, calculates the reachable coverage rate of test vector.
Further, the simulation unit described in the embodiment of the present invention is additionally operable to, when the test vector for generating is unsatisfactory for covering
Rate requires, then carries out parameter optimization or manual modification parameter by intelligent algorithm to meet coverage rate requirement；When what is generated
Test vector meets requirement, and test vector is converted into the file that correspondence meets IEEE1445 standards, and it is enterprising to be applied to hardware
Row emulation, by the detection to excitation, input and output pin etc., the test vector that further assessment is generated.
Converting unit of the present invention is additionally operable to when being embodied as, by VHDL crossover tools by be input into circuit design and
Hardware designs are converted to the unified RTL design based on VHDL language.
The present invention is converted into by the circuit design (Protel net meter files) being input into and other hardware designs of input
Unified RTL (Register Transfer Level, Method at Register Transfer Level) designs, RTL design is further converted to can be by symbol
The receptible specific software model (LLVM Bytecode) of execution instrument institute, and then using semiology analysis instrument and combine grain
The intelligent algorithms such as subgroup carry out the optimizing of test vector and test path and match, and generate various test vector, so as to
Efficiently solve the problems, such as to be tested circuit board based on semiology analysis in prior art.
The above, the only present invention preferably specific embodiment, but protection scope of the present invention is not limited thereto,
Any those familiar with the art the invention discloses technical scope in, the change or replacement that can be readily occurred in,
All should be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Enclose and be defined.
Claims (10)
1. a kind of automatic test vector generation method based on circuit board, it is characterised in that include：
The circuit design and hardware designs of input are converted to into unified RTL design；
RTL design is converted to can be by the software model of semiology analysis instrument；
Carry out the optimizing of test vector and test path and match by semiology analysis instrument and with reference to intelligent algorithm, generate
Test vector.
2. method according to claim 1, it is characterised in that also include：
The test vector of generation is combined into RTL design, application hardware design and simulation software is emulated, generate corresponding test arrow
Amount coverage rate report, to test vector entry evaluation is carried out.
3. method according to claim 2, it is characterised in that the test vector of generation is combined into RTL design, application hardware
Design and simulation software is emulated, and is specifically included：
The test vector that semiology analysis are generated is carried out into driving simulation software, is emulated by calling Modelsim engine implementations, calculated
The reachable coverage rate of test vector.
4. method according to claim 2, it is characterised in that also include:
Require when the test vector for generating is unsatisfactory for coverage rate, then parameter optimization or manual modification are carried out by intelligent algorithm
Parameter is required with meeting coverage rate；
Require when the test vector for generating meets, test vector is converted into the file that correspondence meets IEEE1445 standards, and should
Use and emulated on hardware, by the detection to excitation, input and output pin etc., the test vector that further assessment is generated.
5. method according to claim 1, it is characterised in that the circuit design and hardware designs of input are converted to into unification
RTL design, specifically include：
The circuit design and hardware designs of input are converted to by VHDL crossover tools unified are set based on the RTL of VHDL language
Meter.
6. a kind of automatic test vector generation device based on circuit board, it is characterised in that include：
Converting unit, for the circuit design and hardware designs of input to be converted to into unified RTL design, RTL design is changed
For can be by the software model of semiology analysis instrument；
Processing unit, for carrying out seeking for test vector and test path by semiology analysis instrument and with reference to intelligent algorithm
It is excellent with match, generate test vector.
7. device according to claim 6, it is characterised in that also include:
Simulation unit, for the test vector of generation to be combined into RTL design, application hardware design and simulation software is emulated, raw
Into the report of corresponding test vector coverage rate, entry evaluation is carried out to test vector.
8. device according to claim 7, it is characterised in that
The simulation unit is additionally operable to, and the test vector that semiology analysis are generated is come into driving simulation software, by calling
Modelsim engine implementations are emulated, and calculate the reachable coverage rate of test vector.
9. device according to claim 7, it is characterised in that the simulation unit is additionally operable to, when the test vector for generating
Coverage rate requirement is unsatisfactory for, then carrying out parameter optimization or manual modification parameter by intelligent algorithm will to meet coverage rate
Ask；Require when the test vector for generating meets, test vector is converted into correspondence and meets the file of IEEE1445 standards, and applies
Emulated on hardware, by the detection to excitation, input and output pin etc., the test vector that further assessment is generated.
10. device according to claim 6, it is characterised in that
The converting unit is additionally operable to, and is converted to the circuit design and hardware designs of input by VHDL crossover tools unified
RTL design based on VHDL language.
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| CN107478978A (en) * | 2017-07-27 | 2017-12-15 | 天津大学 | Hardware Trojan horse optimal inspection vector generation method based on population |
| WO2019109589A1 (en) * | 2017-12-04 | 2019-06-13 | 石家庄创天电子科技有限公司 | Method and device for performing circuit design based on artificial intelligence |
| CN108132799A (en) * | 2017-12-25 | 2018-06-08 | 首都师范大学 | Interprocedual static program analysis information extracting method, device and equipment |
| CN108132799B (en) * | 2017-12-25 | 2021-03-16 | 首都师范大学 | Inter-process static program analysis information extraction method, device and equipment |
| CN109325145A (en) * | 2018-09-19 | 2019-02-12 | 上海哔哩哔哩科技有限公司 | Acquisition methods, terminal and the computer readable storage medium of video thumbnails |
| CN109325145B (en) * | 2018-09-19 | 2021-10-12 | 上海哔哩哔哩科技有限公司 | Video thumbnail obtaining method, terminal and computer readable storage medium |
| CN109992459A (en) * | 2019-03-29 | 2019-07-09 | 苏州中晟宏芯信息科技有限公司 | Data transfer device, device, equipment and storage medium |
| CN109992459B (en) * | 2019-03-29 | 2023-03-28 | 合芯科技(苏州)有限公司 | Data conversion method, device, equipment and storage medium |
| CN111858216A (en) * | 2020-07-23 | 2020-10-30 | 记忆科技(深圳)有限公司 | Method, apparatus, device and medium for improving testability coverage of SSD |
| WO2024045436A1 (en) * | 2022-09-01 | 2024-03-07 | 中山大学 | Graphical high-level synthesis circuit performance analysis method, system, apparatus, and medium |
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