CN106598184B

CN106598184B - Performing cross-domain thermal control in a processor

Info

Publication number: CN106598184B
Application number: CN201611246335.7A
Authority: CN
Inventors: X·C·曼; M·N·迪瑞; J·D·施瓦茨; S·H·冈瑟; J·J·谢拉; S·M·康拉德; A·N·阿南塔克里什南
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2012-08-31
Filing date: 2013-06-27
Publication date: 2020-08-25
Anticipated expiration: 2033-06-27
Also published as: CN104508593B; GB2520848A; US9189046B2; US9063727B2; WO2014035542A1; GB201700131D0; CN106598184A; US20140068293A1; GB2547977A; GB2520848B; CN104508593A; US20140068291A1

Abstract

The invention relates to performing cross-domain thermal control in a processor. In one embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one uncore circuit. The domains may operate at independent frequencies, and a power control unit coupled to the domains may include thermal logic that causes a reduction in frequency of the first domain in response to an occurrence of a thermal event in the second domain. Other embodiments are described and claimed.

Description

Performing cross-domain thermal control in a processor

The application is a divisional application of a Chinese patent application with the application number of 201380040144.3 on the 6 th and 27 th months in 2013 and the name of 'cross-domain thermal control in a processor'.

Background

As technology in the semiconductor arts advances, devices such as processors include more and more circuitry. Over time, processor designs have evolved from a collection of independent Integrated Circuits (ICs) to a single integrated circuit, to multi-core processors that include multiple processor cores within a single IC package. Over time, more and more cores and associated circuitry are being included in processors and other semiconductors.

Multicore processors are being expanded to include additional functionality by incorporating other functional units within the processor. Typically, a multi-core processor has a global power budget and a global thermal budget. The power budget is set so that at least the power level specified as an average is not exceeded. The thermal budget is set so that the thermal throttle (the maximum allowable temperature at which the processor can safely operate) is not exceeded. While these common budgets exist, there is no mechanism to adaptively share budgets across the various circuits present in a processor.

Brief Description of Drawings

FIG. 1 is a block diagram of a processor according to an embodiment of the invention.

FIG. 2 is a block diagram of a processor according to another embodiment of the invention.

FIG. 3 is a flow diagram of a method for performing cross-domain thermal control in accordance with an embodiment of the present invention.

FIG. 4 is a flow diagram of a method for performing cross-domain thermal control in accordance with another embodiment of the present invention.

FIG. 5 is a block diagram of a processor according to an embodiment of the invention.

FIG. 6 is a block diagram of a multi-domain processor according to another embodiment of the invention.

FIG. 7 is a block diagram of a system according to an embodiment of the invention.

FIG. 8 is a block diagram of another embodiment of a processor, according to one embodiment of the invention.

Detailed Description

In various embodiments, a processor having multiple independent domains may be controlled to prevent the temperature of any one of the domains from exceeding the maximum junction temperature. As used herein, the term "maximum junction temperature" is the highest temperature that a semiconductor product is designated to operate at all without damage. This temperature may be determined during device characterization, during manufacturing, and during testing in a laboratory environment, and stored in non-volatile memory or in fuse logic of the device, as examples. However, the pinch point, which may be set at or below this junction temperature, may be configured, for example by software or firmware, to a value below the highest junction temperature Tj. As such, an Original Equipment Manufacturer (OEM) may throttle down the throttle point as a function of Tj (e.g., using a basic input/output system (BIOS)). By way of example, and not limitation, for a multicore processor, the pinch point may be set between approximately 80 and 110 degrees Celsius.

Note that this throttle point may be achieved for different performance levels of the processor. For example, according to an Operating System (OS) based mechanism, i.e., the Advanced Configuration and Platform Interface (ACPI) standard (e.g., rev.3.0b, published 10.10.10.2006), a processor may operate at various performance states or levels, i.e., from P0 to PN. In general, the P1 performance state may correspond to the highest guaranteed performance state that may be requested by the OS. In addition to this P1 state, the OS may request a higher performance state, i.e., the P0 state. As such, this P0 state may be an opportunistic state in which the processor hardware may configure the processor, or at least portions thereof, to operate at a higher than guaranteed frequency when power and/or thermal budgets are available. In many implementations, the processor may include a plurality of so-called bin frequencies (also referred to as P1 frequencies) that are above a guaranteed maximum frequency. At any of these performance states, more likely at the P0 or P1 states, a pinch point may be reached.

The processor may include a throttling mechanism to prevent any component of the processor from operating above its maximum junction temperature. The throttling mechanism may result in a reduction in frequency, which in turn results in a reduction in power consumption, resulting in a reduction in temperature.

Examples described herein relate to a multi-core processor including multiple processor cores and one or more other processing engines and other circuitry. For example, in particular embodiments described herein, a processor package may include a plurality of semiconductor dies, including a so-called Central Processing Unit (CPU) die and at least one other die that may include memory, controller circuitry, or other logic. In one embodiment, there may be multiple independent domains on the CPU die, including a core domain with one or more cores, a graphics domain with one or more graphics engines, and a so-called system agent or uncore domain that includes additional processor circuitry. As used herein, the term "domain" is used to refer to a collection of hardware and/or logic that operates at the same voltage and frequency point. With respect to multi-chip packages (MCPs), it is noted that each die may also be considered an independent domain, although each such die may itself include multiple domains. Although many of the implementations described herein are directed to MCPs in which different domains may exist on different semiconductor dies of a single package, in other implementations, a multi-domain processor may be formed on a single semiconductor die.

In various embodiments, there is a cross-domain thermal interaction such that the temperature of one domain affects the temperature of another domain. These cross-domain interactions may be considered and accounted for when controlling the temperature of each domain. As used herein, a "thermal event" is the occurrence of a temperature of a given domain exceeding a threshold temperature set for such domain. More specifically, to reduce thermal events in one domain, corrective actions such as thermal throttling may be applied in another domain. This may allow a domain experiencing a thermal event to lower its temperature, thus maintaining the processor below its highest junction temperature.

In particular embodiments described herein, a non-CPU domain may provide an indication to a CPU domain of a thermal event occurring in that domain, thus allowing a power controller or other logic within the CPU domain to take corrective action, such as performing a throttling event within the CPU domain (or another domain), thus allowing resolution of the thermal event.

Referring now to FIG. 1, shown is a block diagram of a processor in accordance with one embodiment of the present invention. In fig. 1, processor 100 may be a multi-core processor, which in the illustrated embodiment is an MCP having a first die 120 and a second die 160. As can be seen, the first die 120 may be a CPU die that includes multiple independent domains. It can also be seen that the second die 160 may be a Peripheral Controller Hub (PCH). In general, the PCH may include interface and control circuitry to provide an interface between the processor and various peripheral devices such as input/output (IO) devices, e.g., user input devices (e.g., keyboard, touchpad, mouse or other pointing device, etc.), and storage devices such as mass storage, portable or other such memory, as well as many other peripheral devices.

The CPU die 120 may include multiple domains, including a core domain 125 that may include one or more processor cores, a graphics domain 130 that may include one or more Graphics Processing Units (GPUs), such as one or more graphics cores, and an uncore domain 135 that may include other circuitry of the processor, such as cache memory, memory controllers, other fixed function units, logic circuitry, and so forth.

It is further seen that CPU die 120 also includes a Power Control Unit (PCU) 140. in the illustrated embodiment, power control unit 140 may include thermal control logic 145. In general, PCU140 may be configured with various circuitry, logic, and the like to perform power management operations for a processor.

Note that the view shown in fig. 1 is high-level to illustrate features related to cross-domain thermal control according to one embodiment of the invention, and is not intended to illustrate all processor circuits. Additionally, the location of certain circuitry is logically rather than physically shown, as PCU140 may be physically part of uncore domain 135 in some embodiments.

As further seen in fig. 1, the second die 160 may include one or more thermal sensors 162, which may be implemented by various circuits in one embodiment. As can be seen, these sensors may communicate information to the comparison logic 166, the comparison logic 166 further receiving one or more thermal throttling thresholds. Note that the thermal thresholds, which may be stored in threshold storage 165, such as a set of registers, a look-up table, or other memory, may be received from BIOS 195, for example, in a non-volatile memory that may provide these thermal thresholds. Based on a comparison of one or more temperature values from the sensor to one or more of these thresholds, it may be determined whether a thermal event has occurred. When a thermal event occurs, as determined by comparison logic 166, a signal may be sent to internal throttling state machine 168, which internal throttling state machine 168 may take corrective action within PCH 160 to cause a temperature decrease. In one embodiment, this state machine may perform various thermal throttling activities to allow for temperature drop. Throttling may be achieved by reducing activity within the PCH, for example, by inserting no-operations (nops) into the stream of instructions, reducing frequency, and/or preventing traffic ingress/egress.

In addition, when a thermal event is detected in PCH 160, a thermal event message may be sent from the PCH to CPU die 120, and more particularly to PCU140 over sideband message link 190, which sideband message link 190 may be a Power Management Synchronous (PMSYNC) link in one embodiment. In one embodiment, this indication of a thermal event may be through a single bit communicated on a single lane of the sideband message link. For example, this channel may pass a logic low signal when no thermal event is detected within the PCH. In contrast, when a thermal event is detected, the channel may be caused to pass a logic high signal, thus indicating the occurrence of the thermal event.

While shown at this high level in the embodiment of fig. 1, understand the scope of the present invention is not limited in this regard. For example, although fig. 1 shows an implementation in which the multi-core processor is configured as an MCP including two dies, in another embodiment, the multi-core processor may be a single die processor including circuitry present on the CPU die and circuitry present on the PCH die. In addition, it will be appreciated that additional circuitry may also be present. Or in other embodiments, different types of non-CPU circuits may be present in the multi-core processor. For example, in another embodiment, instead of a PCH die, an integrated memory die may be provided within a multicore processor.

Referring now to FIG. 2, shown is a block diagram of a processor in accordance with another embodiment of the present invention. As shown in FIG. 2, processor 100 may be a multi-chip package within system 101 and may include a CPU die 120, which CPU die 120 may be implemented similar to that of FIG. 1. In contrast, in the embodiment of FIG. 2, processor 100 also includes embedded memory die 170, which embedded memory die 170 may be implemented using embedded dynamic random access memory (eDRAM) and may act as the main or system memory of the system, rather than as a cache for the CPU die (as this die includes integrated cache memory), in one embodiment. As can be seen, this memory die may include one or more temperature sensors 172 configured to provide temperature information to comparison logic 175. It can further be seen that the memory die 170 may include a threshold memory 174, the threshold memory 174 configured to store one or more thresholds, such as a highest junction temperature of the die. Based on this comparison in comparison logic 175, if the value from one or more of thermal sensors 172 exceeds the highest junction temperature, then a thermal event is so identified and may be communicated to CPU die 120, and more specifically, PCU140 over inter-die communication bus 178.

Still referring to fig. 2, note that the system 101 including this processor 100 may also include a PCH 160, which PCH 160 may be the same configuration as the internal PCH of fig. 1. Of course, the system may include many other components, however, the illustration of FIG. 2 is simplified to show those components involved in performing cross-domain thermal control in accordance with one embodiment of the present invention.

Embodiments may be performed in various locations. As one example, the logic of the PCU of the processor may be used to perform cross-domain thermal control in accordance with an embodiment of the present invention. Referring now to FIG. 3, a method for performing cross-domain thermal control in accordance with one embodiment of the present invention is shown. In one embodiment, method 200 of fig. 3 may be performed by thermal logic of the PCU and may be performed iteratively, i.e., once every predetermined interval, which may be approximately 1 millisecond (ms) in one embodiment. In general, the method may be performed based on temperatures of multiple domains of a processor. Such temperature information may be obtained directly from the domain, e.g., from thermal sensors associated with each domain coupled to the PCU (e.g., over a push bus or other link). Alternatively, the temperature information may be determined within the PCU, for example, based on thermal sensor data obtained from these thermal sensors.

As shown in FIG. 3, the method 200 may begin by initializing a package maximum temperature to a CPU die maximum domain temperature (block 210). That is, an implementation is assumed in which the multi-core processor is a multi-chip package that includes a CPU die and at least one other die (in the embodiment of fig. 3, this other die is assumed to be an internal memory die). The highest domain temperature of the CPU die may correspond to the highest temperature recorded for the various temperature sensors present in the multiple domains of the CPU die. For example, referring back to fig. 2, the highest temperature may be the temperature associated with the given one of the kernel, graph, and uncore domain having the highest value. In one embodiment, this package maximum temperature may be stored in a memory location such as a register within the PCU. Control next proceeds to block 215 where the internal memory die temperature may be initialized to a predetermined value, e.g., zero. This value may also be stored in a memory location such as a register of the PCU.

Still referring to FIG. 3, control next passes to diamond 220 where it is determined whether an internal memory die is present and is subject to an active thermal event (diamond 220). This determination may be based on the presence of a status signal or other configuration information of the die. And the indication of an active thermal event may be determined based on receiving a thermal event message from the internal memory die. As discussed above, in one embodiment, this event may be indicated by a communication on a push bus (push bus).

If it is determined that such a thermal event has occurred, control passes to block 225, where cross-domain thermal throttling may be performed on the CPU die. Various operations may be performed within the CPU die to achieve this thermal throttling. As one example, thermal throttling may be performed by reducing the frequency of one or more domains of a die. For example, both the core domain and the graphics domain may reduce their frequencies, e.g., meta-frequencies. As used herein, a "meta-frequency" corresponds to the smallest multiple employed by the update domain frequency. In some embodiments, this element frequency may be an integer multiple of the bus clock frequency, although the scope of the invention is not limited in this respect. As another example, the selected amount may correspond to a predetermined amount of degradation of the frequency bin. For example, the kernel domain frequency may be reduced by 1/N of the meta-frequency. However, rather than reducing the frequency by less than the meta-frequency amount, embodiments allow for multiple iterations of the thermal control algorithm of FIG. 3 to be performed, maintaining a count of the number of 1/N reductions when thermal throttling is indicated. Then, at the natural meta-boundary corresponding to the N/N reductions, the actual frequency reduction for a given domain may be performed. In other embodiments, other ways of throttling the temperature may be performed.

Still referring to fig. 3, next, at block 230, the internal memory die temperature (stored in the registers of the PCU) may be set to the highest fusing temperature of the die. In one embodiment, this value may be stored in a storage location, such as a PCU register, and may correspond to the highest junction temperature of the die. Next, control passes to block 235, where the package maximum temperature may be updated to the highest of both the current package maximum temperature (initialized at block 210) and this maximum fuse temperature. As discussed above, this value may be stored in a storage location, such as a PCU register, which may be reported to one or more foreign agents at block 240. By way of example, this value may be reported to various system components, such as an embedded controller, which in turn may cause control of various system devices, such as fans, for example, increasing fan speed to aid in cooling. This information may further be provided to other system components such as an Operating System (OS), BIOS, or other system software to allow various routines to be executed, for example, to reduce activity in the system and/or processor to further reduce temperature. While shown at this high level in the embodiment of fig. 3, understand the scope of the present invention is not limited in this regard.

In general, the frequency reduction may be performed using the frequency control logic of the PCU, which may cause a given domain to reduce its frequency. As an example, this frequency reduction process includes stopping all useful work of the domain, venting transactions pending in the domain, applying a new frequency (possibly a new voltage) to the domain, and then resuming normal operation in the domain at the new frequency/voltage. Thus, it can be seen that some complexity is involved in the frequency change, which in addition takes some amount of time. Temperature changes may lag frequency changes by an amount that is a function of the thermal capacity of the deployed cooling solution. By controlling the rate of frequency change to match the thermal capacity of the cooling solution, control cycling oscillations and fluctuations in frequency and temperature can be avoided. Accordingly, by only performing such frequency changes when natural meta boundaries are reached, greater efficiency may be achieved. This count of iterations of which the frequency is reduced by 1/N amount may be stored in a temporary memory, such as a register, counter, or other such memory. When the value in such a counter reaches the full number, the actual frequency change may be performed.

Note that the mechanism to reduce the core domain frequency may be implemented in different ways. For example, the frequency control logic of the PCU may receive an instruction to update the core domain frequency. The frequency control logic may, in turn, select various instructions to be transmitted for causing the frequency to shrink. For example, various control signals may be sent to one or more Phase Locked Loops (PLLs) or other frequency control mechanisms to cause the frequency to shrink.

A similar control method may be used for the embodiment of fig. 1 with a multi-core processor that includes a CPU die and a PCH die. Referring now to fig. 4, a method for performing cross-domain thermal control in accordance with another embodiment of the present invention is shown. In one embodiment, the method 300 of fig. 4 may be performed by the thermal logic of the PCU, as described above.

As shown in FIG. 4, the method 300 may begin by initializing a package maximum temperature to a CPU die maximum domain temperature (block 310). That is, an implementation is assumed in which the multi-core processor is a multi-chip package that includes a CPU die and at least one other die (in the embodiment of fig. 4, this other die is assumed to be a PCH die). The highest domain temperature of the CPU die may correspond to the highest temperature recorded for the various temperature sensors present in the multiple domains of the CPU die. In one embodiment, this package maximum temperature may be stored in a memory location such as a register within the PCU. Control next proceeds to block 315 where the PCH die temperature may be initialized to a predetermined value, e.g., zero. This value may also be stored in a memory location such as a register of the PCU.

Still referring to fig. 4, control next proceeds to diamond 320 where it is determined whether a PCH die is present and subject to an active thermal event. This determination may be based on the presence of a status signal or other configuration information of the die. The indication of an active thermal event may be determined based on receiving a thermal event message from the PCH die, which may be indicated by a sideband communication link.

If it is determined that such a thermal event has occurred, control passes to block 325 where cross-domain thermal throttling may be performed on the CPU die. Various operations may be performed within the CPU die to achieve this thermal throttling. As one example, thermal throttling may be performed by reducing the frequency of one or more domains of a die.

Still referring to fig. 4, next, at block 330, the PCH die temperature (stored in registers of the PCU) may be set to the PCH temperature trip point. Next, control passes to block 335 where the package maximum temperature may be updated to the highest of both the current package maximum temperature (initialized at block 310) and the PCH temperature trip point. As described above, this value may be reported to one or more foreign agents at block 340, which may be stored in a storage location such as a PCU register, as discussed above.

Referring now to table 1, shown is a pseudo-code implementation of a thermal control algorithm in accordance with one embodiment of the present invention. Note that in this pseudo-code, the algorithm provides analysis and thermal control of multiple types of non-CPU die within the processor. In particular, the code shows operations performed when initializing a temperature value, determining whether a thermal event occurred in a peripheral (non-CPU) die, and if so, performing a throttling operation and reporting the temperature information to one or more external agents. It can be seen that there may be code for an internal memory die as well as an internal PCH die (although only one of these may be present in a given implementation). Of course, it is to be understood that the scope of the present invention is not limited in this respect, and in other implementations, code may exist that performs cross-domain thermal control for other types of die or domains within a multi-domain package.

TABLE 1

//

EDRAM _ therm _ status// EDC/eDRAM therm _ status reported on the push bus

PCH _ therm _ status/PCH _ therm _ status reported on PMSync

//

Pkg _ max _ temp ═ max (all nuclear, graphical, and non-nuclear sensors);

eDRAM_temperature＝0；

If(EDRAM_present&&EDRAM_therm_status){

cross-thermal throttling activation, i.e., lowering the core/graphics ratio;

eDRAM_temperature＝eDRAM_fused_Tjmax；

pkg_max_temp＝max(pkg_max_temp,eDRAM_temperature)；

}

//

pkg _ max _ temp ═ max (all nuclear, graphical, and non-nuclear sensors);

PCH_temperature＝0

If(PCH_present&&PCH_therm_status){

// activate across thermal throttling, i.e. reduce the frequency of the core and graphics domain;

PCH_Temperature＝PCH_temperature_trip_point；

pkg_max_temp＝max(pkg_max_temp,PCH_temperature)；

}

referring now to FIG. 5, shown is a block diagram of a processor in accordance with one embodiment of the present invention. As shown in FIG. 5, processor 400 may be a multi-core processor including multiple cores 410_a-410_n. In one embodiment, each such core may be an independent power domain and may be configured to operate at an independent voltage and/or frequency and enter turbo frequency mode when there is available headroom. The various cores may be coupled through an interconnect 415 to a system agent or uncore 420 that includes various components. As seen, uncore 420 may include a shared cache memory 430, which may be the last level cache. In addition, the uncore may include an integrated memory controller 440, various interfaces 450, and a power control unit 455.

In various embodiments, power control unit 455 may include thermal control logic 459, which may be logic that controls the CPU domain frequency based not only on the temperature of the domain itself, but also on the temperature of other areas of the processor. In the FIG. 5 embodiment, logic 459 may receive information regarding whether a thermal event occurred in a given non-CPU domain and, if so, perform frequency control for another domain, e.g., a CPU domain, in accordance with an embodiment of the present invention. As further seen in fig. 5, to provide storage of various values for thermal control, a thermal control memory 457 may further be present within PCU 455 to store values such as various maximum temperature values, at least some of which may be communicated to external agents, as described above. This memory may also store Tj for various dies or domains. Although shown in this location in the embodiment of fig. 5, understand the scope of the present invention is not limited in this respect and the storage of this information may be located elsewhere.

With further reference to fig. 5, the processor 400 may communicate with a system memory 460, for example, over a memory bus, which system memory 460 may be located on another die embedded in the package, the CPU die including the rest of the circuitry of the processor 400. In addition, various off-package components, such as peripherals, mass storage, and the like, may be connected through interface 450. Although shown with this particular implementation in the embodiment of fig. 5, the scope of the present invention is not limited in this regard.

Referring now to FIG. 6, shown is a block diagram of a multi-domain processor in accordance with another embodiment of the present invention. As shown in the embodiment of fig. 6, processor 500 includes multiple domains. Specifically, core domain 510 may include a plurality of cores 510₀–510_nThe graphics domain 520 may include one or more graphics engines, and there may further be a system agent domain 550. In embodiments, the system agent domain 550 may execute at a fixed frequency and may remain powered on at all times to handle power control events and power management, each of the

domains

510 and 520 may operate at different voltages and/or powers. Note that while only three domains are shown, it is to be understood that the scope of the present invention is not limited in this respect and that additional domains may be present in other embodiments.For example, there may be multiple core domains, each of which includes at least one core.

Generally, each core 510 may further include a lower level cache in addition to execution units and additional processing elements. In turn, the cores may be coupled to each other and to a Last Level Cache (LLC)540₀–540_nA shared cache memory formed by a plurality of units. In various embodiments, LLC 550 may be shared among the cores and the graphics engine, as well as various media processing circuits. As can be seen, ring interconnect 530 thus couples the cores together and provides an interconnect between the cores, graphics domain 520, and system agent circuitry 550.

In the FIG. 6 embodiment, system agent domain 550 may include a display controller 552, which may provide control and interface to an associated display. It is further seen that, according to one embodiment of the present invention, the system agent domain 550 may include a power control unit 555, and the power control unit 555 may include a frequency control logic 559. In various embodiments, this logic may execute an algorithm such as that shown in Table 1, thus dynamically controlling the frequency based on thermal events occurring on non-CPU domains.

As further seen in fig. 6, processor 500 may further include an Integrated Memory Controller (IMC)570 that may provide an interface to a system memory, such as a Dynamic Random Access Memory (DRAM). There may be multiple interfaces 580₀–480_nTo allow interconnection between the processor and other circuitry. For example, in one embodiment, at least one Direct Media Interface (DMI) interface and one or more peripheral component interconnect Express (PCI Express) interfaces may be provided^TM(PCIe^TM) An interface. Still further, compliance may also be provided to provide communication between other agents, such as additional processors or other circuitry

One or more interfaces of a Quick Path Interconnect (QPI) protocol. It is further appreciated that PCH 590 may also be present within processor 500 and, in some embodiments, may be implemented on a separate dieNow. While shown at this high level in the embodiment of fig. 6, understand the scope of the present invention is not limited in this regard.

Embodiments may be implemented in many different system types. Referring now to FIG. 7, shown is a block diagram of a system in accordance with one embodiment of the present invention. As shown in FIG. 7, multiprocessor system 600 is a point-to-point interconnect system, and includes a first processor 670 and a second processor 680 coupled via a point-to-point interconnect 650. As shown in fig. 7, each of

processors

670 and 680 may be multicore processors, including first and second processor cores (i.e.,

processor cores

674a and 674b and

processor cores

684a and 684b), although potentially many more cores may be present in the processors. As described herein, each of the processors may include a PCU or other logic to perform dynamic frequency control of the domains of the processor based on thermal events of the non-CPU domains.

Still referring to FIG. 7, the first processor 670 also includes a Memory Controller Hub (MCH)672 and point-to-point (P-P) interfaces 676 and 678. Similarly, second processor 680 includes a MCH 682 and

P-P interfaces

686 and 688. As shown in FIG. 7, MCH's 672 and 682 couple the processors to respective memories, namely a memory 632 and a memory 634, which may be portions of system memory (e.g., DRAM) locally attached to the respective processors. First processor 670 and second processor 680 may be coupled to a chipset 690 via P-P interconnects 652 and 654, respectively. As shown in FIG. 7, chipset 690 includes

P-P interfaces

694 and 698.

Furthermore, chipset 690 includes an interface 692 to couple chipset 690 with a high performance graphics engine 638 via a P-P interconnect 639. In turn, chipset 690 may be coupled to a first bus 616 via an interface 696. As shown in fig. 7, various input/output (I/O) devices 614 and bus bridge 616 may be coupled to first bus 618, with bus bridge 616 coupling first bus 620 to second bus 920. In one embodiment, various devices may be coupled to second bus 620 including, for example, a keyboard/mouse 622, communication devices 626 and a data storage unit 628 such as a disk drive or other mass storage device which may include code 630. Further, an audio I/O624 may be coupled to the second busAnd a line 620. Embodiments may be incorporated into other types of systems including, for example, smart cellular phones, tablet computers, netbooks, ultrabooks, and the like^TMAnd the like.

Referring to FIG. 8, an embodiment of a processor including multiple cores is shown. Processor 1100 includes any processor or processing device, such as a microprocessor, embedded processor, Digital Signal Processor (DSP), network processor, hand-held processor, application processor, co-processor, system on a chip (SOC), or other device for executing code. In one embodiment, processor 1100 includes at least two cores — cores 1101 and 1102, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 1100 may include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic for supporting a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context unit, a logical processor, a hardware thread, a core, and/or any other element capable of maintaining a state of a processor, such as an execution state or an architectural state. In other words, in one embodiment, a processing element refers to any hardware capable of being independently associated with code, such as software threads, operating systems, applications, or other code. A physical processor generally refers to an integrated circuit that may include any number of other processing elements, such as cores or hardware threads.

A core generally refers to logic located on an integrated circuit capable of maintaining an independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread generally refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. It can be seen that the boundaries between the terms of hardware threads and cores overlap when some resources are shared and others are architecture state specific. Cores and hardware threads are often viewed by an operating system as a single logical processor, where the operating system is able to schedule operations on each logical processor separately.

Physical processor 1100 as shown in FIG. 8 includes two cores — cores 1101 and 1102. Here, cores 1101 and 1102 are considered symmetric cores, i.e., the cores have the same configuration, functional units, and/or logic. In another embodiment, core 1101 comprises an out-of-order processor core, and core 1102 comprises an in-order processor core. However, cores 1101 and 1102 may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated ISA, a co-designed core, or other known core. However, for further discussion, the functional units shown in core 1101 will be described in further detail below, as the units in core 1102 operate in a similar manner.

As depicted, core 1101 includes two

hardware threads

1101a and 1101b, which may be referred to as

hardware thread slots

1101a and 1101 b. Thus, in one embodiment, a software entity such as an operating system potentially views processor 1100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As described above, a first thread may be associated with architecture state registers 1101a, a second thread may be associated with architecture state registers 1101b, a third thread may be associated with architecture state registers 1102a, and a fourth thread may be associated with architecture state registers 1102 b. Here, each of the architecture state registers (1101a, 1101b, 1102a, and 1102b) may be referred to as a processing element, a thread slot, or a thread unit, as described above. As described above, architecture state registers 1101a are replicated in architecture state registers 1101b, and thus individual architecture states/contexts can be stored for logical processor 1101a and logical processor 1101 b. In core 1101, other smaller resources for

threads

1101a and 1101b may also be replicated, such as instruction pointers and renaming logic in allocator and rename block 1130. Some resources, such as reorder buffers in reorder/retirement unit 1135, ILTB 1120, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page table base registers, lower level data cache and data TLB 1115, execution unit 1140, and portions of out-of-order unit 1135 are potentially shared in their entirety.

Processor 1100 typically includes other resources, which may be fully shared, shared through partitions, or dedicated/dedicated to processing elements. In fig. 8, an embodiment of a purely exemplary processor with illustrative logical units/resources of the processor is shown. Note that a processor may include or omit any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As shown, core 1101 comprises a simplified, representative out-of-order (OOO) processor core. However, in-order processors may be utilized in different embodiments. The OOO core includes a branch target buffer 1120 for predicting branches to be executed/taken and an instruction translation buffer (I-TLB)1120 for storing address translation entries for instructions.

Core 1101 further includes a decode module 1125 coupled to fetch unit 1120 for decoding fetched elements. In one embodiment, fetch logic includes respective sequencers associated with

thread slots

1101a, 1101b, respectively. Typically, core 1101 is associated with a first ISA that defines/specifies instructions executable on processor 1100. Machine code instructions that are part of the first ISA often include a portion of the instructions (referred to as opcodes) that reference/specify the instructions or operations to be performed. Decode logic 1125 includes circuitry to recognize these instructions by their opcodes and pass the decoded instructions on the pipeline for processing as defined by the first ISA. For example, in one embodiment, decoder 1125 includes logic designed or adapted to recognize specific instructions, such as transactional instructions. As a result of the recognition by decoder 1125, architecture or core 1101 takes specific, predetermined actions to perform tasks associated with the appropriate instructions. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of them may be new or old instructions.

In one example, allocator and renamer block 1130 includes an allocator to reserve resources, such as a register set to store instruction processing results. However,

threads

1101a and 1101b are potentially capable of out-of-order execution, with allocator and renamer block 1130 also reserving other resources (such as a reorder buffer for tracking instruction results). Unit 1130 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 1100. Reorder/retirement unit 135 includes components such as the reorder buffers, load buffers, and store buffers described above to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

In one embodiment, scheduler and execution unit block 1140 includes a scheduler unit to schedule instructions/operations on the execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Also included is a register set associated with the execution unit for storing information instruction processing results. Exemplary execution units include floating point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

A lower level data cache and data translation buffer (D-TLB)1150 is coupled to execution unit 1140. The data cache is used to store recently used/operated on elements (such as data operands), which are potentially held in a memory coherency state. The D-TLB is to store recent virtual/linear to physical address translations. As a particular example, a processor may include a page table structure to break up physical memory into a plurality of virtual pages.

Here, cores 1101 and 1102 share access to a higher level or further away cache 1110 for caching recently fetched elements. Note that higher level or further refers to cache level increasing or further away from the execution unit. In one embodiment, higher level cache 1110 is a last level data cache — a last level cache in a memory hierarchy on processor 1100, such as a second or third level data cache. However, higher-level cache 1110 is not so limited, as it may be associated with or include an instruction cache. Alternatively, a trace cache, a type of instruction cache, may be coupled after decoder 1125 for storing recently decoded traces.

In the depicted configuration, processor 1100 also includes a bus interface module 1105 and a power controller 1160 that may perform cross-domain thermal control, according to one embodiment of the invention. Historically, controller 1170 has been included in a computing system external to processor 1100. In this scenario, bus interface 1105 communicates with devices external to processor 1100, such as system memory 1175, a chipset (typically including a memory controller hub to connect to memory 1175 and an I/O controller hub to connect to peripherals), a memory controller hub, a northbridge, or other integrated circuit, external to processor 100. And in this scenario, bus 1105 may include any known interconnect, such as a multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherency) bus, a layered protocol architecture, a differential bus, and a GTL bus.

Memory 1175 may be dedicated to processor 1100 or shared with other devices in the system. Common examples of types of memory 1175 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 1180 may include a graphics accelerator, processor, or card coupled to a memory controller hub, a data store coupled to an I/O controller hub, a wireless transceiver, a flash memory device, an audio controller, a network controller, or other known devices.

Note, however, that in the depicted embodiment, controller 1170 is shown as part of processor 1100. More recently, as more logic and devices are integrated on a single die (e.g., SOC), each of these devices may be incorporated on processor 1100. For example, in one embodiment, memory controller hub 1170 is on the same package and/or die as processor 1100. Here, a portion of the core (on-core portion) includes one or more controllers 1170 that interface with other devices, such as memory 1175 and/or graphics device 1180. This configuration, which includes a controller and interconnect for interfacing with such devices, is commonly referred to as an on-core (or un-core) configuration. By way of example, bus interface 1105 includes a ring interconnect having a memory controller for interfacing with memory 1175 and a graphics controller for interfacing with graphics processor 1180. However, in an SOC environment, even more devices such as a network interface, co-processor, memory 1175, graphics processor 1180, and any other known computer device/interface may be integrated onto a single die or integrated circuit to provide a small form factor with high functionality and low power consumption.

Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. Storage media may include, but are not limited to: any type of disk including floppy disks, optical disks, Solid State Drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks; semiconductor devices such as Read Only Memory (ROM), Random Access Memory (RAM) such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Erasable Programmable Read Only Memory (EPROM), flash memory, Electrically Erasable Programmable Read Only Memory (EEPROM); a magnetic or optical card, or any other type of medium suitable for storing electronic instructions.

While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims

1. A processor, comprising:

at least one processor core associated with a first domain;

at least one non-processor core circuit associated with a second domain;

a plurality of thermal sensors, at least a first thermal sensor associated with the first domain and at least a second thermal sensor associated with the second domain; and

a power controller coupled with the first domain and the second domain, the power controller comprising logic to cause a frequency of the first domain to be reduced in response to a temperature of the second domain exceeding a threshold.

2. The processor of claim 1, wherein the non-processor core circuitry comprises a graphics processing unit.

3. The processor of claim 1, wherein the processor further comprises a digital signal processor.

4. The processor of claim 1, wherein the processor further comprises a shared cache memory.

5. The processor of claim 1, further comprising a plurality of processor cores associated with the first domain.

6. The processor of claim 5, wherein at least some of the plurality of processor cores are to operate at independent voltages.

7. The processor of claim 1, wherein the power controller is to cause the first domain and the second domain to operate at different voltages.

8. The processor of claim 1, further comprising at least one high speed peripheral component interconnect interface.

9. A computing system, comprising:

a processor;

a memory coupled with the processor; and

a memory coupled with the processor, wherein the processor comprises:

at least one processor core associated with a first domain;

at least one non-processor core circuit associated with a second domain;

10. The computing system of claim 9, further comprising at least one communication device coupled with the processor.

11. The computing system of claim 9, further comprising an input/output device coupled with the processor.

12. The computing system of claim 9, wherein the computing system comprises a mobile device.

13. A method for power control, comprising:

sensing a temperature of non-processor core circuitry in a second domain of a processor, the processor further comprising a first domain having at least one processor core for executing instructions;

transmitting a message to a power controller of the processor when a temperature of the non-processor core circuitry exceeds a thermal threshold; and

causing a change in a power state of the at least one processor core in response to the message.

14. The method of claim 13, further comprising: sensing the temperature via one or more thermal sensors of the processor.

15. The method of claim 13, wherein the thermal threshold comprises a highest junction temperature.

16. An apparatus for power control, comprising means for performing the method of any of claims 13-15.

17. A machine-readable storage medium having machine-readable instructions stored thereon which, when executed, implement the method of any of claims 13 to 15.