CN106572085B - A kind of chip and matching process from UDF application angle - Google Patents
A kind of chip and matching process from UDF application angle Download PDFInfo
- Publication number
- CN106572085B CN106572085B CN201610910966.8A CN201610910966A CN106572085B CN 106572085 B CN106572085 B CN 106572085B CN 201610910966 A CN201610910966 A CN 201610910966A CN 106572085 B CN106572085 B CN 106572085B
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- module
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- udf
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/325—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the network layer [OSI layer 3], e.g. X.25
Abstract
The present invention provides a kind of chip from UDF application angle, including interface message module, virtual LAN module, three layers of variable head module, multiprotocol label module and four layers of head module, the interface message module, virtual LAN module, three layers of variable head module, multiprotocol label module and four layers of head module are matched as key message, it compiles out the byte number that several groups of deviation posts and each offset point start to take to be configured, takes out user-defined data based on these configurations, finally go to match with accesses control list again.The present invention can flexibly support continually changing network protocol message demand on current agreement face very much, so that the life cycle of chip is longer.
Description
Technical field
The present invention relates to Network Processor technology field more particularly to a kind of chip from UDF application angle and
Method of completing the square.
Background technique
Now with network Development, the development of cloud virtualization technology can gradually appear many new protocol types, mesh
Preceding popular agreement such as vxlan, nvgre etc., whens these protocol encapsulations generally use message three-layer information after carry again
The method of two layers of information, and a kind of new tunneling technique.With the enhancing of interchanger ability, more and more demands are just had
It is the head information for needing to pay close attention to four layers or more.And conventional switch IC is because be hard coded and the development cycle is longer, core first
Piece can not recognize specifically variable protocol type, therefore can not directly meet these needs, it is common practice that by message
On be sent to the method for cpu and go to handle these messages, the Software Protocol Stack on cpu realizes the identifying processing of vxlan/nvgre etc..On
State in scheme, message all on send cpu, cpu resources much more very can all be occupied by passing through Software Protocol Stack and identifying message and handle,
And the user experience that may result in some applications also can be poor, and chip can not do associated safety and statistics.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, the chip from UDF application angle is provided, in reality
The application that the chip encountered in can not be supported, while considering the design cost of chip, reduce cost of manufacture.
To achieve the above object, the following technical solutions are proposed: a kind of chip from UDF application angle by the present invention, packet
Interface message module, virtual LAN module, three layers of variable head module, multiprotocol label module and four layers of head module are included, it is described
Interface message module, virtual LAN module, three layers of variable head module, multiprotocol label module and four layers of head module are as crucial
Information is matched, and is compiled out the byte number that several groups of deviation posts and each offset point start to take and is configured, these are based on
User-defined data are taken out in configuration, finally go to match with accesses control list again.
Preferably, three layers of Changeable head includes IpOption, Ipv6ExtHeader.
Preferably, four layers of head module includes transmission control protocol and User Datagram Protocol.
Preferably, the number of three layers of variable head module is determined by IpOption or Ipv6ExtHeader.
Preferably, the exchange length of the multiprotocol label module includes 4 layer protocol sources and 4 layer protocol purposes.
Preferably, the number of the virtual LAN module is defined by the user to determine.
In addition, the present invention also provides a kind of chip matching process from UDF application angle, by user in message
The processing of the field of concern, is compensated and character boundary, for the critical data of subsequent access control list identification message, from
And such message is abandoned by chip logic, is redirected, strategy, statistical disposition.
The beneficial effects of the present invention are: the present invention provides a kind of design chips scheme, can flexibly support very much at present
Continually changing network protocol message demand, more powerful to specific message processing capacity on agreement face, and makes chip
Life cycle is also longer.
Detailed description of the invention
Fig. 1 is the module diagram of chip design of the invention.
Specific embodiment
Below in conjunction with attached drawing of the invention, clear, complete description is carried out to the technical solution of the embodiment of the present invention.
Referring to Fig. 1, the disclosed chip from UDF application angle, including interface message module, virtually
LAN module, three layers of variable head module, multiprotocol label module and four layers of head module, the interface message module, virtual office
Domain net module, three layers of variable head module, multiprotocol label module and four layers of head module are matched as key message, are compiled out
The byte number that several groups of deviation posts and each offset point start to take is configured, and takes out user-defined number based on these configurations
According to finally going to match with accesses control list again.
Furtherly, three layers of Changeable head includes IpOption, Ipv6ExtHeader；Four layers of head module include
Transmission control protocol and User Datagram Protocol；The number of three layers of variable head module by IpOption or Ipv6ExtHeader Lai
It determines；The exchange length of the multiprotocol label module includes 4 layer protocol sources and 4 layer protocol purposes, the virtual LAN mould
The number of block is defined by the user to determine.
Chip design principle of the present invention is as follows:
Consider that the mechanism of UDF goes to provide flexibility, the typical case of the UDF mentioned from the prior art in the design phase of chip
Two kinds are set out using angles, the former is the head newly defined to be established on well known protocol basis, for example vxlan in udp head
Afterwards, timing match is set in UDF consider some elements: interface message, vlanNum, three layers of Changeable head such as IpOption,
Ipv6ExtHeader length, MPLS label length, four layers of head are tcp, udp etc., are matched these information as key (),
Action goes out several groups of deviation posts and each offset point starts the byte number taken configuration, takes out udf data based on these configurations,
It goes to match with acl again below, because acl action is more flexible, can be done and be located with the coprocessor outside redirect to CPU/
Reason or some speed limits, statistics and discard processing send CPU processing and speed limit etc. such as certain message.UDF matching
Memory is tcam, in order to flexible, can configure mask (mask) according to particular demands.
The present invention also provides a kind of chip matching process from UDF application angle, by paying close attention to user in message
Field processing, compensated and character boundary, for the critical data of subsequent access control list identification message, thus logical
Cross chip logic such message is abandoned, is redirected, strategy, statistical disposition.Key point of the invention is by message
The acquisition of various information goes to obtain offset and len, and is introduced into the processing logic of feature stream by acl.
For example, receiving the message of vxlan altogether, ordinary circumstance is upper cpu, in an embodiment of the present invention, it is assumed that this
The ipsa of message is 1.1.1.1, and the port udp is 4789, then can be resolved to according to the two information by udf parser
Offset is 332bit, len 64bit, then this 64bit is vxlanheader in fact, such as the content of this 64bit message
It is 0x01010101, it then can be this partial content as the critical data of accesses control list, if one acl of configuration
Entry, which also contains 0x01010101, can be matched to this message, thus by chip logic do discarding, redirection,
The behaviors such as strategy, statistics.
Technology contents and technical characteristic of the invention have revealed that as above, however those skilled in the art still may base
Make various replacements and modification without departing substantially from spirit of that invention, therefore, the scope of the present invention in teachings of the present invention and announcement
It should be not limited to the revealed content of embodiment, and should include various without departing substantially from replacement and modification of the invention, and be this patent Shen
Please claim covered.
Claims (6)
1. a kind of chip from UDF application angle, it is characterised in that: including interface message module, virtual LAN module,
Three layers of variable head module, multiprotocol label module and four layers of head module, the interface message module, virtual LAN module, three
The variable head module of layer, multiprotocol label module and four layers of head module are matched as key message, compile out several groups of bits of offset
It sets the byte number for starting to take with each offset point to be configured, takes out user-defined data based on these configurations, finally again
It goes to match with accesses control list.
2. the chip according to claim 1 from UDF application angle, which is characterized in that three layers of Changeable head packet
Include IpOption and Ipv6ExtHeader.
3. the chip according to claim 1 from UDF application angle, which is characterized in that four layers of head module packet
Include transmission control protocol and User Datagram Protocol.
4. the chip according to claim 1 from UDF application angle, which is characterized in that three layers of Changeable head mould
The number of block is determined by IpOption or Ipv6ExtHeader.
5. the chip according to claim 1 from UDF application angle, which is characterized in that the multiprotocol label mould
The exchange length of block includes 4 layer protocol sources and 4 layer protocol purposes.
6. the chip according to claim 1 from UDF application angle, which is characterized in that the virtual LAN mould
The number of block is defined by the user to determine.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610910966.8A CN106572085B (en) | 2016-10-19 | 2016-10-19 | A kind of chip and matching process from UDF application angle |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610910966.8A CN106572085B (en) | 2016-10-19 | 2016-10-19 | A kind of chip and matching process from UDF application angle |
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| Publication Number | Publication Date |
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| CN106572085A CN106572085A (en) | 2017-04-19 |
| CN106572085B true CN106572085B (en) | 2019-10-11 |
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| CN201610910966.8A Active CN106572085B (en) | 2016-10-19 | 2016-10-19 | A kind of chip and matching process from UDF application angle |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108270699B (en) * | 2017-12-14 | 2020-11-24 | 中国银联股份有限公司 | Message processing method, shunt switch and aggregation network |
| CN110035074A (en) * | 2019-04-01 | 2019-07-19 | 盛科网络（苏州）有限公司 | A kind of chip implementing method and device of ACL matching UDF message |
| CN113438252B (en) * | 2021-07-08 | 2023-01-10 | 恒安嘉新（北京）科技股份公司 | Message access control method, device, equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003056763A1 (en) * | 2001-12-21 | 2003-07-10 | Chip Engines | Reconfigurable data packet header processor |
| CN102970227A (en) * | 2012-11-12 | 2013-03-13 | 盛科网络（苏州）有限公司 | Method and device for achieving virtual extensible local area network (VXLAN) message transmitting in application specific integrated circuit (ASIC) |
| CN105337884A (en) * | 2015-09-25 | 2016-02-17 | 盛科网络（苏州）有限公司 | Method and device for achieving multistage message editing service control on the basis of logic port |
| CN105429841A (en) * | 2014-09-15 | 2016-03-23 | 中兴通讯股份有限公司 | NNI PING realization method and device |
-
2016
- 2016-10-19 CN CN201610910966.8A patent/CN106572085B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003056763A1 (en) * | 2001-12-21 | 2003-07-10 | Chip Engines | Reconfigurable data packet header processor |
| CN102970227A (en) * | 2012-11-12 | 2013-03-13 | 盛科网络（苏州）有限公司 | Method and device for achieving virtual extensible local area network (VXLAN) message transmitting in application specific integrated circuit (ASIC) |
| CN105429841A (en) * | 2014-09-15 | 2016-03-23 | 中兴通讯股份有限公司 | NNI PING realization method and device |
| CN105337884A (en) * | 2015-09-25 | 2016-02-17 | 盛科网络（苏州）有限公司 | Method and device for achieving multistage message editing service control on the basis of logic port |
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| CN106572085A (en) | 2017-04-19 |
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Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Patentee after: Suzhou Shengke Communication Co.,Ltd. Address before: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Patentee before: CENTEC NETWORKS (SU ZHOU) Co.,Ltd. |