CN106571916A - Decryption method, method, and circuit - Google Patents
Decryption method, method, and circuit Download PDFInfo
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- CN106571916A CN106571916A CN201510657731.8A CN201510657731A CN106571916A CN 106571916 A CN106571916 A CN 106571916A CN 201510657731 A CN201510657731 A CN 201510657731A CN 106571916 A CN106571916 A CN 106571916A
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Abstract
A decryption method comprises: receiving encrypted data, wherein the encrypted data is encrypted by an RSA public key; and performing at least one multiplication operation and at least one square operation according to a RSA private key and the encrypted data to obtain decrypted data; wherein performing a pseudo square operation on the basis of the encrypted data while the one of the at least one multiplication operation is performed, or performing a pseudo multiplication operation on the basis of the encrypted data while the one of the at least one square operation is performed.
Description
Technical field
This case is related to a kind of device, method and circuit.Specifically, this case be related to a kind of decryption device,
Method and circuit.
Background technology
RSA cryptographic algorithms are a kind of rivest, shamir, adelmans.Encryption device can be using RSA public keys to news
Breath is encrypted, and decrypts after message of the device after encryption is received, using RSA private keys to this
Message after encryption is decrypted.
However, when decryption device is decrypted, attacker can be by the related news for measuring decryption device
Number (such as voltage or power) learns that decryption device is made judging to decrypt the computing that device is carried out
RSA private keys.
Therefore, a kind of defensive decryption method for measuring attack is worked as and is suggested.
The content of the invention
To solve the above problems, an embodiment of this case is related to a kind of decryption method, including：Receive and add
Close data, wherein encrypted data are Jing RSA public key encryptions；And according to RSA private keys and encryption money
Material carries out at least multiplying and at least a square operation, to obtain decrypted data；Wherein, entering
While capable at least one of multiplying, at least one first pseudo- square of fortune is carried out according to encrypted data
Calculate, or while at least one of square operation is carried out, the first puppet is carried out according to encrypted data and is taken advantage of
Method computing.
Another embodiment of this case is related to a kind of decryption device, including communication module and decryption element.
Decryption element to：Encrypted data is received through communication module, wherein encrypted data is Jing RSA public keys
Encryption；And an at least multiplying and at least one square are carried out according to RSA private keys and encrypted data
Computing, to obtain decrypted data.When at least one of multiplying is carried out, according to encrypted data
The first pseudo- square operation is carried out, or when at least one of square operation is carried out, according to encrypted data
Carry out the first pseudo- multiplying.
Another embodiment of this case is related to a kind of decryption circuit, including squarer, multiplier, multiplexer
And buffer.Squarer carries out square operation to receives input numerical value to being input into numerical value, to produce
Raw squarer output.Multiplier to receives input numerical value and encrypted data, and to be input into numerical value with
And encrypted data carries out multiplying, to produce multiplier output.Multiplexer is defeated to receive squarer
Go out and multiplier output, and to according in the output squarer output of RSA private keys and multiplier output
One of, as multiplexer output.Buffer is configured to temporarily store multiplexer output, and it is defeated to provide multiplexer
Go out to squarer and multiplier, as new input numerical value.Square operation is while entering with multiplying
OK.
Through using an above-mentioned embodiment, decryption device can defend measurement to attack when computing is decrypted
Hit.
Description of the drawings
Fig. 1 is the schematic diagram of the decryption system according to depicted in the embodiment of this case one；
Fig. 2 is the flow chart of the decryption method according to depicted in the embodiment of this case one；
Fig. 3 is the schematic diagram of the decryption method according to depicted in the embodiment of this case one；
Fig. 4 is the schematic diagram of the decryption method according to depicted in another embodiment of this case；
Fig. 5 is the schematic diagram of the decryption method according to depicted in another embodiment of this case；
Fig. 6 is the schematic diagram of the decryption circuit according to depicted in the embodiment of this case one；And
Fig. 7 is the schematic diagram of the decryption circuit according to depicted in the embodiment of this case one.
Symbol description
10：Decryption system
20：Encryption device
100：Decryption device
110：Decryption element
112：Decryption circuit
114：Decryption circuit
120：Communication module
200：Decryption method
S1-S2：Step
2、4、6、8、22、24、26：Sequence
SQ、MT、SQ’、MT’、SQ"、MT"：Computing
a1、a2：Eigenvalue
MUX：Multiplexer
MTC：Multiplier
SQC：Squarer
REG：Buffer
CTL：Controller
N：Encrypted data
CS：Control signal
T1-T8、P1-P5、Q1-Q4：Period
Specific embodiment
Fig. 1 is the schematic diagram of the decryption system 10 according to depicted in the embodiment of this case one.Decryption system
10 include decryption device 100 and encryption device 20.Encryption device 20 to using RSA public keys to news
Encryption for information, to produce encrypted data N, decrypts device 100 to receive encrypted data N, and to it
It is decrypted.
Decryption device 100 includes decryption element 110 and the communication module 120 being electrically connected with each other.It is logical
News module 120 transmits encrypted data N to receive the encrypted data N from encryption device 20
To decryption element 110.Decryption element 110 to encrypted data N to be decrypted.
The decryption available processors of element 110 or other appropriate computing elements perform specific instruction or program institute
Realize, or available circuit is realized.In one embodiment, communication module 120 can be with wired or wireless
Communication element is realized.
In the lump with reference to Fig. 2, the decryption method 200 in Fig. 2 can be applicable to same or similar in Fig. 1
Shown decryption device 100.To carry out to decryption side by taking the decryption device 100 in Fig. 1 as an example below
Method 200 is described.
Step S1：Decryption element 110 receives adding from encryption device 20 through communication module 120
Close data N, encrypted data N is Jing RSA public key encryptions.
Step S2：Decryption element 110 is decrypted operation to encrypted data N.Decrypting element 110 is
According to the RSA private keys corresponding to aforementioned RSA public keys and encrypted data N, at least multiplication fortune is carried out
Calculate and an at least square operation, to be decrypted to encrypted data N, and obtain decrypted data.
For example, with reference to table one, when the numerical value of aforementioned RSA private keys is 123, its binary bit shape
Formula is 2 ' b1111011.Therefore, when being decrypted, sequentially carried out corresponding to each bit
Multiplying and/or square operation.By taking the sequence of operations 2 of Fig. 3 as an example, in period T1, decryption element
Part 110 carries out square operation SQ.In period T2, T3, due to a binary form left side for RSA private keys
Number second bit is 1, and decryption element 110 sequentially carries out multiplying MT and square operation SQ.
Period T8, because the left bit of number the 5th of the binary form of RSA private keys is 0, decryption element 110 enters
Row square operation MT.
| Binary form | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
| Multiplying | - | ˇ | ˇ | ˇ | - | ˇ | ˇ |
| Square operation | ˇ | ˇ | ˇ | ˇ | ˇ | ˇ | - |
Table one
In decryption oprerations, the number of times that aforementioned multiplying is carried out is corresponding to the two of RSA private keys and enters
Numerical value is 1 quantity in the form of position.For example, in Table 1, in addition to left several first bits, numerical value
Quantity for 1 bit is 5, therefore carries out 5 multiplyings.Additionally, aforementioned square operation is entered
Binary bit bit length (bit length) of the capable number of times corresponding to aforementioned RSA private keys.For example, it is aforementioned
The binary bit bit length of RSA private keys is 7 bits, and decryption element 110 need to perform 7-1=6 time square
Computing.
It should be noted that while multiplying is carried out, decryption element 110 is more according to encryption money
Material N carries out the first pseudo- square operation；While square operation is carried out, the more basis of element 110 is decrypted
Encrypted data N carries out the first pseudo- multiplying.Wherein, the first pseudo- square operation or the first pseudo- multiplication fortune
The operation result of calculation is not used to produce decrypted data.Due to when multiplying or square operation is carried out,
The corresponding first pseudo- square operation or the first pseudo- multiplying are carried out simultaneously, and attacker i.e. cannot be by amount
The related signal (such as power, electric current, voltage, temperature, frequency) of decryption device 100 is surveyed, is learnt
Operation and its corresponding RSA private keys that decryption device 100 is carried out when decryption.
In one embodiment, the number of times that the first pseudo- multiplying is carried out can be same as or less than carrying out before
State the number of times of square operation.Similarly, the number of times that the aforementioned first pseudo- square operation is carried out can be same as
Or less than carrying out the number of times of aforementioned multiplying.
Hereinafter an operation example is provided by collocation Fig. 3, in this operation example, the numerical value of RSA private keys is 123,
Its binary form is 2 ' b1111011.When decryption element 110 carries out square operation SQ, decryption
The corresponding waveform of the related signal of device 100 has eigenvalue (such as amplitude) a1, and in decryption element 110
When carrying out multiplying MT, the corresponding waveform for decrypting the related signal of device 100 has eigenvalue a2.
Additionally, in this operation example, while decryption element 110 sequentially performs sequence of operations 2,
The first puppet multiplying MT ' that decryption element 110 is sequentially performed in sequence of operations 4 is pseudo- with first flat
Square computing SQ ', so that each square operation SQ and the first puppet multiplying MT ' is while carry out,
And each multiplying MT and the first puppet square operation SQ ' is made while carrying out.Wherein, in decryption
When element 110 carries out the first puppet square operation SQ ', the corresponding ripple of the related signal of device 100 is decrypted
Shape has eigenvalue a1, and when decryption element 110 carries out the first puppet multiplying MT ', decryption
The corresponding waveform of the related signal of device 100 with eigenvalue a2.
Consequently, it is possible in decryption oprerations, even if attacker measures the related signal of decryption device 100,
Attacker is only capable of the sequence 6 for obtaining adding up sequence of operations 2 and the corresponding signal of sequence of operations 4, and difficult
To pick out RSA private keys from measurement.
Furthermore, in some embodiments of this case, carrying out aforesaid multiplying or aforesaid square
Before or after computing, it is pseudo- flat that decryption element 110 more can carry out at least one second according to encrypted data N
Square computing or at least one second pseudo- multiplying.Wherein, the second pseudo- square operation and the second pseudo- multiplication fortune
Invalid computing at last, to be inserted in original sequence of operations (such as the sequence of operations 2 in Fig. 3) before,
Among or afterwards, with mislead using measure attack attacker.
In one embodiment, carry out the second pseudo- multiplying twice, carry out twice between multiplying,
Or carry out between one time second pseudo- multiplying and multiplication operation, decryption element 110 is at least carried out
Square operation or the second pseudo- square operation.Consequently, it is possible to can avoid because of the pseudo- square of fortune of insertion second
Sequence of operations exception after calculation or the second pseudo- multiplying, and make attacker learn extraneous information.
Hereinafter an operation example is provided by collocation Fig. 4, in this operation example, the numerical value of RSA private keys is
123, its binary form is 2 ' b1111011.In decryption oprerations, decryption element 110 is sequentially held
Square operation SQ, multiplying MT in row sequence of operations 8, the second pseudo- square operation SQ " and the
Two puppet multiplying MT ".Wherein, the second pseudo- square operation SQ " and second pseudo- multiplying MT "
Operation result is not to produce decrypted data.Consequently, it is possible in decryption oprerations, even if attacker
The related signal for measuring decryption device 100 performs the fortune in sequence of operations 8 to learn decryption device 100
Calculate, attacker also cannot according to this pick out RSA private keys.
With reference to Fig. 5, decryption element 110 can carry out the pseudo- square operation SQ of insertion second " and the second puppet is taken advantage of
The sequence of operations 22 of method computing MT ".Wherein, while sequence of operations 22 are carried out, element is decrypted
110 can also carry out sequence of operations 24, pseudo- with the square operation SQ in sequence of operations 22 is carried out and second
While at least one of square operation SQ ", the corresponding first pseudo- multiplying MT' is carried out, and
Pseudo- multiplying MT at least one of " of multiplying MT and second in sequence of operations 22 is carried out
While, carry out the corresponding first pseudo- square operation SQ'.Consequently, it is possible in decryption oprerations, attack
The person of hitting is difficult to pick out RSA private keys from the sequence of operations 26 for measuring.
In an embodiment of the present invention, decrypting element 110 may include a decryption circuit (such as the solution of Fig. 6
Cipher telegram road 112), to carry out aforementioned decryption oprerations.As shown in fig. 6, decryption circuit 112 includes
Squarer SQC, multiplier MTC, multiplexer MUX and buffer REG.Squarer SQC's
The first input end of input and multiplier MTC is electrically connected with the outfan of buffer REG and adds
The source terminal of close data N.Second input of multiplier MTC receives encrypted data N.Squarer
The outfan of SQC and the outfan of multiplier MTC be electrically connected with the first of multiplexer MUX and
Second input.The control end of multiplexer MUX receives control signal CS, and multiplexer MUX's is defeated
Go out the input that end is electrically connected with buffer REG, wherein control signal CS corresponds to RSA private keys.
Squarer SQC carries out square operation to being input into numerical value, to produce squarer output, multiplier
MTC carries out multiplying to being input into numerical value and encrypted data N, to produce multiplier output, wherein
Input numerical value can be encrypted data N or the output for buffer REG.Multiplexer MUX is according to control
One of signal CS output squarer outputs and multiplier output, as multiplexer output.Buffer
REG receives and keeps in multiplexer output, and exports to squarer SQC and multiplier MTC, as
New input numerical value.
In the present embodiment, squarer SQC and multiplier MTC be and meanwhile carry out square operation and
Multiplying, so that attacker cannot learn decryption by the related signal for measuring decryption device 100
Operation and its corresponding RSA private keys that device 100 is carried out when decryption.
For example, referring concurrently to Fig. 3, in period T1, squarer SQC and multiplier MTC
Input numerical value is all N, therefore squarer SQC carries out square operation and exports N^2, and simultaneous processing
MTC carries out multiplying and exports N^2.Multiplexer MUX is according to the CS selections square of control signal
Device output is as the output of the first multiplexer.The temporary first multiplexer outputs of buffer REG, and secondary one
In wheel computing, there is provided the first multiplexer is exported to squarer SQC and multiplier MTC.
N^2 is all in the input numerical value of period T2, squarer SQC and multiplier MTC, therefore square
Device SQC carries out square operation and exports N^4, and simultaneous processing MTC carries out multiplying and defeated
Go out N^3.Multiplexer MUX selects multiplier output (i.e. N^3) as second according to control signal CS
Multiplexer is exported.The temporary second multiplexer outputs of buffer REG, and in secondary one wheel computing, there is provided
Second multiplexer is exported to squarer SQC and multiplier MTC.Remaining computing is by that analogy.
By aforesaid operations, you can make attacker that the related signal of device 100 cannot be decrypted by measurement,
Learn operation and its corresponding RSA private keys for decrypting that device 100 is carried out when decryption.
In one embodiment, decrypting circuit 112 more may include controller CTL (dotted line), controller
CTL is electrically connected with buffer REG, and to control buffer REG, whether to provide new multiplexer defeated
Go out to squarer SQC and multiplier MTC.
For example, in the first operating condition, when buffer REG receives new multiplexer and exports,
The controllable buffer REG of controller CTL preserve original multiplexer output, and provide original many
Work device is exported to squarer SQC and multiplier MTC.In addition, in the second operating condition, temporary
When storage REG receives a new multiplexer output, the controllable buffer REG of controller CTL are temporary
New multiplexer output is deposited, and new multiplexer is provided and exported to squarer SQC and multiplier MTC.
For example, referring concurrently to Fig. 5, in period Q1, squarer SQC and multiplier MTC
Input numerical value is all N, therefore squarer SQC outputs and multiplier MTC export N^2.Multiplexer
MUX selects squarer to be output as the output of the first multiplexer according to control signal CS.Controller CTL is controlled
The temporary first multiplexer outputs of buffer REG processed, and in secondary one wheel computing, there is provided the first multiplexer
Export to squarer SQC and multiplier MTC.
N^2 is all in the input numerical value of period Q2, squarer SQC and multiplier MTC, therefore square
Device SQC exports N^4, and simultaneous processing MTC output N^3.Multiplexer MUX is according to control
Signal CS selects multiplier output as the output of the second multiplexer.Controller CTL controls buffer REG
The output of the first multiplexer is preserved, and in secondary one wheel computing, there is provided the first multiplexer is exported to squarer
SQC and multiplier MTC.
N^2, squarer are all in the input numerical value of period Q3, squarer SQC and multiplier MTC
SQC exports N^4, multiplier MTC output N^3.Multiplexer MUX is according to the CS choosings of control signal
Squarer output is selected as the output of the 3rd multiplexer.Controller CTL control buffer REG preserve the
One multiplexer export, and secondary one wheel computing in, there is provided the first multiplexer export to squarer SQC with
Multiplier MTC.
N^2 is all in the input numerical value of period Q4, squarer SQC and multiplier MTC, therefore square
Device SQC exports N^4, and simultaneous processing MTC output N^3.Multiplexer MUX is according to control
Signal CS selects multiplier output (i.e. N^3) to export as the 4th multiplexer.Controller CTL is controlled
The temporary 4th multiplexer outputs of buffer REG, and in secondary one wheel computing, there is provided the 4th multiplexer is defeated
Go out to squarer SQC and multiplier MTC, as new input numerical value.
By aforesaid operations, you can make attacker that the related signal of device 100 cannot be decrypted by measurement,
Learn operation and its corresponding RSA private keys for decrypting that device 100 is carried out when decryption.
Fig. 7 is the schematic diagram of the decryption circuit 114 according to one embodiment of the invention.In the present embodiment,
Decryption circuit 114 includes multiplier MTC, multiplexer MUX, buffer REG and controller CTL.
The first input end of multiplexer MUX is electrically connected with the outfan and encrypted data N of buffer REG
Source terminal, second input of multiplexer MUX receives encrypted data N, the control of multiplexer MUX
End processed receives control signal CS, and the outfan of multiplexer MUX is electrically connected with the of multiplier MTC
One input.Second input of multiplier MTC be electrically connected with the outfan of buffer REG and
The source terminal of encrypted data N, the outfan of multiplier MTC is electrically connected with buffer REG.Control
Device CTL is electrically connected with buffer REG.
Multiplexer MUX according to RSA private keys (such as control signal CS) to export the input number for receiving
Value or encrypted data N.It can be encrypted data N or the output for buffer REG to be wherein input into numerical value.
Multiplier MTC carries out multiplying to export to input numerical value and multiplexer, to produce multiplier
Output.Buffer REG is to receive and keeps in multiplier output, and provides multiplier and export to multiplexing
Device MUX and multiplier MTC, as a new input numerical value.Controller CTL keeps in control
Whether device REG provides new multiplier exports to multiplexer MUX and multiplier MTC, wherein, control
The function of device CTL processed may be, for example, the controller CTL that Fig. 6 is.
For example, referring concurrently to Fig. 4, in period P1, multiplexer MUX and multiplier MTC
Input numerical value is all N.Multiplexer MUX selects input numerical value as multiplexer according to control signal CS
Output.Multiplier MTC output N^2 are exported as the first multiplier.Controller CTL controls are temporary
Device REG keeps raw value (for example, empty numerical value (NULL)), and in secondary one wheel computing (such as period
P2 raw value is provided in) to multiplexer MUX and multiplier MTC.
All it is still N in the input numerical value of period P2, multiplexer MUX and multiplier MTC.Multiplexer
MUX is exported according to control signal CS Choice encryptions data N as multiplexer.Multiplier MTC is defeated
Go out N^2 to export as the second multiplier.Controller CTL control buffer REG keep raw value,
And in secondary one wheel computing raw value is provided to multiplexer MUX and multiplier MTC.
Period P3 is similar with the operation in period P1, will not be described here.
In period P4, the input numerical value of multiplexer MUX and multiplier MTC is all still N.It is many
Work device MUX selects input numerical value to export as multiplexer according to control signal CS.Multiplier MTC
Output N^2 is exported as the 4th multiplier.Controller CTL control buffers REG the temporary 4th takes advantage of
Musical instruments used in a Buddhist or Taoist mass is exported, and the 4th multiplier of offer is exported to multiplexer MUX and multiplication in secondary one wheel computing
Device MTC.Remaining step is by that analogy.
By aforesaid operations, you can make attacker that the related signal of device 100 cannot be decrypted by measurement,
Learn operation and its corresponding RSA private keys for decrypting that device 100 is carried out when decryption.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any ripe
This those skilled in the art is practised, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations,
Therefore protection scope of the present invention is worked as and is defined depending on the appended claims person of defining.
Claims (10)
1. a kind of decryption method, including：
An encrypted data is received, wherein the encrypted data is the RSA public key encryptions of Jing mono-；And
An at least multiplying and at least one square fortune are carried out according to a RSA private keys and the encrypted data
Calculate, to obtain a decrypted data；
Wherein while at least an one of multiplying is carried out, according to the encrypted data one is carried out
First pseudo- square operation, or while at least an one of square operation is carried out, according to the encryption
Data carries out one first pseudo- multiplying.
2. decryption method according to claim 1, wherein carrying out the fortune of the first pseudo- square operation
Calculate result or carry out the operation result of the first pseudo- multiplying not to produce the decrypted data.
3. decryption method according to claim 1, further includes：
Carry out this at least one of multiplying or this at least before one of square operation or it
Afterwards, one second pseudo- square operation or one second pseudo- multiplying are carried out according to the encrypted data.
4. decryption method according to claim 3, wherein carrying out second pseudo- multiplication fortune twice
Calculation, the second pseudo- multiplying and the once multiplying between the multiplying or once twice
Between, carry out the square operation or the second pseudo- square operation.
5. it is a kind of to decrypt device, including：
One communication module；And
One decryption element, to：
Through the communication module, an encrypted data is received, the wherein encrypted data is the RSA public keys of Jing mono-
Encryption；And
An at least multiplying and at least one square fortune are carried out according to a RSA private keys and the encrypted data
Calculate, to obtain a decrypted data；
Wherein while at least an one of multiplying is carried out, according to the encrypted data one is carried out
First pseudo- square operation, or while at least an one of square operation is carried out, according to the encryption
Data carries out one first pseudo- multiplying.
6. decryption device according to claim 5, the wherein first pseudo- multiplying are carried out
A binary bit bit length of the number of times corresponding to the RSA private keys.
7. decryption device according to claim 6, the wherein first pseudo- multiplying are carried out
Number of times is same as or less than the number of times for carrying out the square operation.
8. decryption device according to claim 5, the wherein first pseudo- square operation are carried out
Number of times is same as or less than the number of times for carrying out the multiplying.
9. it is a kind of to decrypt circuit, including：
One squarer, to receive an input numerical value, and carries out a square operation to the input numerical value,
To produce squarer output；
One multiplier, to receive the input numerical value and an encrypted data, and to the input numerical value with
And the encrypted data carries out a multiplying, to produce multiplier output；
One multiplexer, to receive the squarer output and the multiplier output, and to according to one
RSA private keys export one of the squarer output and the multiplier output, used as multiplexer output；
And
One buffer, is configured to temporarily store multiplexer output, and provides the multiplexer and export to the squarer
With the multiplier, as a new input numerical value；
Wherein the square operation is while carrying out with the multiplying.
10. decryption circuit according to claim 9, further includes：
One controller, wherein under one first mode of operation, in the buffer a new multiplexing is received
When device is exported, the controller controls the buffer and preserves the multiplexer output, and it is defeated to provide the multiplexer
Go out to the squarer and the multiplier；And under one second mode of operation, in the buffer this is received
When new multiplexer is exported, the controller controls the buffer and keeps in the new multiplexer output, and carries
Export to the squarer and the multiplier for the new multiplexer.
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| CN201510657731.8A CN106571916B (en) | 2015-10-12 | 2015-10-12 | Decryption device, method and circuit |
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| CN201510657731.8A CN106571916B (en) | 2015-10-12 | 2015-10-12 | Decryption device, method and circuit |
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