CN106571291A - Pattern transfer method - Google Patents
Pattern transfer method Download PDFInfo
- Publication number
- CN106571291A CN106571291A CN201510648838.6A CN201510648838A CN106571291A CN 106571291 A CN106571291 A CN 106571291A CN 201510648838 A CN201510648838 A CN 201510648838A CN 106571291 A CN106571291 A CN 106571291A
- Authority
- CN
- China
- Prior art keywords
- power supply
- bias power
- substrate
- transfer method
- grid bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a pattern transfer method, which is used for transferring a characteristic pattern to a substrate. The method comprises the following steps: S1) forming a photoresist layer on the substrate, and transferring the characteristic pattern to the photoresist layer through the composition technology to form a photoresist pattern; S2) turning on an excitation power supply and a grid bias power supply in an etching chamber, wherein the grid bias power supply is a first grid bias power supply corresponding to plasma immersion ion implantation technology, carrying out plasma immersion ion implantation on the photoresist pattern, and then, turning off the first grid bias power supply; and S3) carrying out plasma etching on the substrate, on the surface of which the photoresist pattern is formed, in the etching chamber until the characteristic pattern is transferred to the substrate. The pattern transfer method can reduce line width roughness of each line of the photoresist pattern in situ, so that process is simplified to a great extent, process time is reduced and device cost is reduced; and besides, line width roughness of each line of the photoresist pattern can be further reduced, thereby facilitating accurately transferring the pattern to the substrate.
Description
Technical field
The invention belongs to field of manufacturing semiconductor devices, and in particular to a kind of graph transfer method.
Background technology
In field of manufacturing semiconductor devices, it is the cost of manufacture for reducing device, needs in certain face
Prepare device on long-pending substrate as much as possible, the characteristic size that this is accomplished by device is the smaller the better.
At present, photoetching process determines the minimum feature size of device, in order to by less characteristic size
Feature pattern is accurately transferred on substrate, and photoetching process needs face correspondence to reduce live width as far as possible
The challenge of roughness (LWR), so-called line width roughness refer to device lines relative ideal device
The deviation of lines, specifically, the shape of ideal component lines is generally straight line, and actual
The shape of upper device lines often be zigzag, in that way it is possible to device performance degeneration can be caused with
And yield is the problems such as reduce.
In order to reduce line width roughness, at present, the mode for adopting for：Increase carries out photoetching process
Etching system optical lenses numerical aperture, the imaging scape of etching system so, can be caused
It is deep, accordingly, it would be desirable to the thickness of thinning photoresist.But, due to thinner photoresist, which is resistance to
Plasma etching performance is poorer, accordingly, it would be desirable to one layer of formation is resistance between substrate and photoresist
The hard mask layer of plasma etching, generally amorphous carbon layer.
However, in actual applications using one layer of amorphous carbon of formation between substrate and photoresist layer
Can there is problems with layer：
First, need first to transmit to deposition chambers to form amorphous carbon layer from etching cavity by substrate,
Afterwards again auto-deposition device transmission to etching cavity to proceed etching technics, etching technics is also
Need to increase the step of etching the amorphous carbon, therefore, not only cause complex process, process time
It is very long, yield poorly；And the equipment cost of deposition chambers is also add, economic benefit is low.
Second, as amorphous carbon structure is loose porous, hardness is not relatively high, therefore, in etching
Easily sustain damage in technique, cause line width roughness still higher, there is impact device performance
Hidden danger.
The content of the invention
It is contemplated that at least solving one of technical problem present in prior art, it is proposed that one
Graph transfer method is planted, the line width roughness of the lines for reducing photoetching offset plate figure in situ is capable of achieving,
So, not only to a great extent Simplified flowsheet, shorten the process time, reduce deposition chambers
Equipment cost, increases economic efficiency；But also can further reduce the lines of photoetching offset plate figure
Line width roughness, so as to be conducive to being transferred on substrate exactly of figure.
One of to solve the above problems, the invention provides a kind of graph transfer method, for will
Feature pattern is transferred on substrate, is comprised the following steps：S1, forms photoetching over the substrate
Glue-line, is transferred to feature pattern on photoresist layer using patterning processes, forms photoetching offset plate figure；
S2, opens the excitation power supply and grid bias power supply of etching cavity, and the grid bias power supply is plasma
Corresponding first grid bias power supply of immersion ion injection technology, the photoetching offset plate figure is carried out etc. from
Daughter immersion ion injection technology, then closes first grid bias power supply.S3, in etch chamber
Interior is formed with the substrate of the photoetching offset plate figure and carries out plasma etch process to surface, directly
It is transferred on the substrate to the feature pattern.
Preferably, produced using inductive mode in step S2 and step S3
Raw plasma；Step S3 also includes：Switch the grid bias power supply for the etching work
Corresponding second grid bias power supply of skill is simultaneously opened.
Specifically, first grid bias power supply is high-pressure pulse direct current source or high voltage direct current
Source.
Preferably, if first grid bias power supply is high-pressure pulse direct current source, its parameter includes：
Voltage range is -1k～-100kV；Pulses range is 0～1kHz；Pulse duty factor scope is
10～90%；If first grid bias power supply is high-voltage DC power supply, its parameter includes：Voltage model
Enclose for -1k～-100kV.
Preferably, the process gas in step S2 is carbon elements, element silicon, bromine unit
At least one gas in element, protium, nitrogen and inert gas elements.
Preferably, the technological parameter of step S2 includes：The throughput scope of process gas is
10～200sccm；Process atmospheric pressures scope is 0.5～100mT；Process time scope is 0.5～30min.
Preferably, also include in step S1：Oxide layer is formed over the substrate；
The photoresist layer is formed in the oxide layer.
Preferably, also include in step S1：Silicon nitride layer is formed in the oxide layer；
The photoresist layer is formed on the silicon nitride layer.
Preferably, also include in step S1：Antireflection is formed on the silicon nitride layer
Layer；The photoresist layer is formed on the anti-reflecting layer.
Preferably, in step S3, the silicon nitride layer is transferred in the feature pattern
Afterwards, using plasma ashing mode removes the photoetching offset plate figure, then proceeds etching
Technique, until the feature pattern is transferred on the substrate.
The invention has the advantages that：
The graph transfer method that the present invention is provided, before step S3 performs etching technique, passes through
Step S2 carries out plasma immersion and ion implantation technique in etching cavity interior focusing photoresist figure,
By each exposed surface of ion implanted photoresist figure so that outside each of photoetching offset plate figure
Dew surface is uniformly modified, the hardening of photoetching offset plate figure after ion implanting, can as hard mask layer,
This needs to deposit hard mask layer in deposition chamber and be transferred to substrate mistake in figure with prior art
The step of needing extra increase to etch away the hard mask layer during journey is compared, and first, can be in etching
Within the chamber forms hard mask layer, also just realizes that the live width of the lines for reducing photoetching offset plate figure in situ is thick
Rugosity, so as to reduce the equipment cost of deposition chambers, increases economic efficiency；Second, can be with
The step of etching away the hard mask layer need not additionally be increased when figure is transferred to substrate process,
So as to Simplified flowsheet to a great extent, shorten the process time；3rd, photoetching offset plate figure hardening
The amorphous carbon layer of relatively existing deposition afterwards, hardness are higher, are not easily susceptible to damage in etching process,
It can thus be avoided producing impact to line width roughness；4th, due in ion implantation process
Middle photoresist temperature raises and causes its local softening and rearrange, and ion can grind, touch
The Roughen Edges of the lines of photoetching offset plate figure is hit and polishes off, such that it is able to further realize original position
Reduce the line width roughness of the lines of photoetching offset plate figure；5th, plasma immersion and ion implantation
Technique ion implanting efficiency high on three-dimensional, thus can well to photoetching offset plate figure
The contour shape of lines is modified.
Description of the drawings
Fig. 1 is the flow chart of graph transfer method provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram of step S2 shown in Fig. 1；And
Fig. 3 is the structure of the etching cavity for performing graph transfer method provided in an embodiment of the present invention
Schematic diagram.
Specific embodiment
To make those skilled in the art more fully understand technical scheme, with reference to
Accompanying drawing come to the present invention provide graph transfer method be described in detail.
Fig. 1 is the flow chart of graph transfer method provided in an embodiment of the present invention；Fig. 2 is Fig. 1
The schematic diagram of shown step S2.Fig. 1 and Fig. 2 is seen also, the embodiment of the present invention is provided
Graph transfer method, for feature pattern is transferred to substrate 100, so-called feature pattern
Refer to and prepare figure designed by semiconductor device.Specifically, the graph transfer method include with
Lower step：
Step S1, forms one layer of photoresist layer 104 on the substrate 100, will using patterning processes
Feature pattern is transferred on photoresist layer 104, forms photoetching offset plate figure.Specifically, composition work
Skill includes but is not limited to exposed and developed etc..
Step S2, open etching cavity excitation power supply and grid bias power supply, grid bias power supply for wait from
Corresponding first grid bias power supply of daughter immersion ion injection technology, photoetching offset plate figure is carried out etc. from
Daughter immersion ion injection technology, then closes the first grid bias power supply.Wherein, excitation power supply is used
Plasma is formed in the process gas being input in etching cavity is excited；First grid bias power supply is used
In back bias voltage is provided to substrate 100, to attract cation to move towards substrate 100, to realize
Plasma immersion and ion implantation technique is carried out to photoetching offset plate figure, as shown in Fig. 2 cation
105 each exposed surface that photoetching offset plate figure is injected from all directions.
Specifically, the first grid bias power supply is high-pressure pulse direct current source or high-voltage DC power supply.
More specifically, if the first grid bias power supply is high-pressure pulse direct current source, its parameter includes：Voltage
Scope is -1k～-100kV；Pulses range is 0～1kHz；Pulse duty factor scope is
10～90%；If the first grid bias power supply is high-voltage DC power supply, its parameter includes：Voltage range is
- 1k～-100kV.
Also, process gas in step s 2 be carbon elements (C), element silicon (Si),
Bromo element (Br), protium (H), nitrogen (N) and inert gas elements (He, Ne,
Ar, Kr, Xe) at least one gas, that is to say, that the ionic speciess of injection include
In carbon ion, silicon ion, bromide ion, hydrion, Nitrogen ion and various inert gas ions extremely
Few one kind.Preferably, process gas is argon (Ar).
The parameter of step S2 includes：The throughput scope of process gas is 10～200sccm；Work
Skill air pressure range is 0.5～100mT；Process time scope is 0.5～30min.
S3, surface is formed with etching cavity photoetching offset plate figure substrate 100 carry out etc. from
Daughter etching technics, until feature pattern is transferred on substrate 100.
Specifically, in the present embodiment, using inductive in step S2 and step S3
The plasma that produces of mode；In this case, step S3 also includes：Switching bias plasma
Source is corresponding second grid bias power supply of etching technics.Wherein, the second grid bias power supply is for substrate
100 provide back bias voltage, to attract cation to move towards substrate 100, so as to realize to substrate
100 perform etching.
Fig. 3 is the structure of the etching cavity for performing graph transfer method provided in an embodiment of the present invention
Schematic diagram.Fig. 3 is referred to, etching cavity includes reaction chamber 10, set in reaction chamber 10
It is equipped with for carrying the chuck 11 of substrate 100, thoughts is set above the roof of reaction chamber 10
Coil 12, induction coil 12 is answered to electrically connect with excitation power supply 14 through the first impedance matching box 13,
Wherein, excitation power supply 14 be radio-frequency power supply, its in step s 2 power bracket be 300～1500W；
In addition, chuck 11 is electrically connected with the first grid bias power supply 15 respectively by selecting switch 18, and
Electrically connect with the second grid bias power supply 16 through the second impedance matching box 17, wherein, the second bias
Power supply 16 is radio-frequency power supply.
In the case, in above-mentioned steps S2, selecting switch 18 and the first grid bias power supply are made
15 electrical connection, and with 16 disconnecting of the second grid bias power supply；In step s3, switching selection switch,
Which is electrically connected with the second grid bias power supply 16, and with 15 disconnecting of the first grid bias power supply.
Preferably, graph transfer method provided in an embodiment of the present invention, also includes in step sl：
Oxide layer 101 is formed on the upper surface of substrate 100；Silicon nitride is formed in the oxide layer 101
Layer 102；Anti-reflecting layer 103 is formed on silicon nitride layer 102, photoresist layer 104 is formed in anti-
On reflecting layer 103.
Specifically, substrate 100 is silicon substrate, using the method growth oxide layer 101 of thermal oxide
(that is, silicon oxide), its thickness range are 20～100A；Not only can by oxide layer 101
To 100 surface contamination of substrate when avoiding subsequently being formed on silicon nitride layer 102；But also can
To serve as cushion, to reduce the thermal stress produced between silicon nitride layer 102 and substrate 100.
The thickness range of silicon nitride layer 102 is 500～1500A, and silicon nitride layer 102 is mainly used in
As the stop-layer for chemically or mechanically polishing.Specifically, chemical gaseous phase depositing process can be adopted
Form the silicon nitride layer 102.
The thickness range of anti-reflecting layer 103 is 500～800A.Can be with by the anti-reflecting layer 103
The reflected light of photoresist bottom is reduced, specifically, can be using rotation semar technique (abbreviation spin coating)
Or chemical gaseous phase depositing process (abbreviation CVD) forms the anti-reflecting layer 103.
In addition, also including after step s 3：Using plasma ashing mode removes photoresist
Figure.Or, in step s3, after feature pattern is transferred to silicon nitride layer, using etc. from
Photoetching offset plate figure is removed by daughter ashing mode, then proceeds etching technics, until feature
Figure is transferred on substrate 100.
Although it should be noted that adopting inductance coupling in step S1 and step S2 in the application
Conjunction mode produces plasma, that is to say, that etching cavity is inductively coupled plasma chamber；
But, this is the invention is not limited in, in actual applications, the two can also adopt its other party
Formula produces plasma, for example, electron cyclotron resonace mode (ECR).
From the foregoing, it will be observed that graph transfer method provided in an embodiment of the present invention, is carved in step S3
Before etching technique, plasma leaching is carried out in etching cavity interior focusing photoresist figure by step S2
No ion implantation technology, by each exposed surface of ion implanted photoresist figure so that light
Each exposed surface of photoresist figure is uniformly modified, the photoetching offset plate figure hardening after ion implanting,
Can as hard mask layer, this need with prior art deposition chamber deposit hard mask layer and
The step of needing extra increase to etch away the hard mask layer when figure is transferred to substrate process is compared,
First, hard mask layer can be formed in etching cavity, reduction photoresist figure in situ is also just realized
The line width roughness of the lines of shape, so as to reduce the equipment cost of deposition chambers, improves economic effect
Benefit；Second, this can be etched away additionally need not increase when figure is transferred to substrate process
The step of hard mask layer, so as to Simplified flowsheet to a great extent, shorten the process time；3rd,
The amorphous carbon layer of relatively existing deposition after photoetching offset plate figure hardening, hardness are higher, in etching process
In be not easily susceptible to damage, it can thus be avoided on line width roughness produce impact；4th, by
Its local softening is caused in the photoresist temperature rising in ion implantation process and is rearranged, and
Ion can grind, collide and polish off the Roughen Edges of the lines of photoetching offset plate figure, so as to can
Further to realize the line width roughness of the lines for reducing photoetching offset plate figure in situ；5th, wait from
Daughter immersion ion injection technology ion implanting efficiency high on three-dimensional, thus can be fine
Ground is modified to the contour shape of the lines of photoetching offset plate figure.
It is understood that the principle that is intended to be merely illustrative of the present of embodiment of above and adopt
Illustrative embodiments, but the invention is not limited in this.It is general in the art
For logical technical staff, without departing from the spirit and substance in the present invention, can make
Various modifications and improvement, these modifications and improvement are also considered as protection scope of the present invention.
Claims (10)
1. a kind of graph transfer method, for feature pattern is transferred to substrate, its feature exists
In comprising the following steps：
S1, is formed photoresist layer over the substrate, is shifted feature pattern using patterning processes
To photoresist layer, photoetching offset plate figure is formed；
S2, open etching cavity excitation power supply and grid bias power supply, the grid bias power supply for wait from
Corresponding first grid bias power supply of daughter immersion ion injection technology, is carried out to the photoetching offset plate figure
Plasma immersion and ion implantation technique, then closes first grid bias power supply.
S3, surface is formed with etching cavity the photoetching offset plate figure substrate carry out etc. from
Daughter etching technics, until the feature pattern is transferred on the substrate.
2. graph transfer method according to claim 1, it is characterised in that in the step
The plasma produced using inductive mode in rapid S2 and step S3；
Step S3 also includes：Switch the grid bias power supply for the etching technics corresponding the
Two grid bias power supplies are simultaneously opened.
3. graph transfer method according to claim 1, it is characterised in that described first
Grid bias power supply is high-pressure pulse direct current source or high-voltage DC power supply.
4. graph transfer method according to claim 3, it is characterised in that if described
One grid bias power supply is high-pressure pulse direct current source, and its parameter includes：Voltage range is
- 1k～-100kV；Pulses range is 0～1kHz；Pulse duty factor scope is 10～90%；
If first grid bias power supply is high-voltage DC power supply, its parameter includes：Voltage range is
- 1k～-100kV.
5. graph transfer method according to claim 1, it is characterised in that in the step
Process gas in rapid S2 be carbon elements, element silicon, bromo element, protium, nitrogen and
At least one gas in inert gas elements.
6. graph transfer method according to claim 1, it is characterised in that the step
The technological parameter of S2 includes：The throughput scope of process gas is 10～200sccm；Process atmospheric pressures
Scope is 0.5～100mT；Process time scope is 0.5～30min.
7. graph transfer method according to claim 1, it is characterised in that in the step
Also include in rapid S1：Oxide layer is formed over the substrate；Formed in the oxide layer described
Photoresist layer.
8. graph transfer method according to claim 7, it is characterised in that in the step
Also include in rapid S1：Silicon nitride layer is formed in the oxide layer；The shape on the silicon nitride layer
Into the photoresist layer.
9. graph transfer method according to claim 8, it is characterised in that in the step
Also include in rapid S1：Anti-reflecting layer is formed on the silicon nitride layer；On the anti-reflecting layer
Form the photoresist layer.
10. graph transfer method according to claim 9, it is characterised in that described
In step S3, after the feature pattern is transferred to the silicon nitride layer, using plasma ash
Change mode removes the photoetching offset plate figure, then proceeds etching technics, until the feature
Figure is transferred on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510648838.6A CN106571291B (en) | 2015-10-09 | 2015-10-09 | A kind of graph transfer method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510648838.6A CN106571291B (en) | 2015-10-09 | 2015-10-09 | A kind of graph transfer method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106571291A true CN106571291A (en) | 2017-04-19 |
| CN106571291B CN106571291B (en) | 2019-10-29 |
Family
ID=58506065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510648838.6A Active CN106571291B (en) | 2015-10-09 | 2015-10-09 | A kind of graph transfer method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106571291B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090263751A1 (en) * | 2008-04-22 | 2009-10-22 | Swaminathan Sivakumar | Methods for double patterning photoresist |
| CN101752205A (en) * | 2008-12-01 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Method for shrinking line-shaped pattern character size |
| CN102136415A (en) * | 2010-01-27 | 2011-07-27 | 中芯国际集成电路制造(上海)有限公司 | Method for improving roughness of line edge of photoetching pattern in semiconductor process |
| CN103003914A (en) * | 2010-03-15 | 2013-03-27 | 瓦里安半导体设备公司 | Method and system for modifying substrate patterned features using ion implantation |
| CN103137564A (en) * | 2011-11-22 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for achieving expanding base region structure in bipolar-complementary metal oxide semiconductor (BiCMOS) device |
| CN103155099A (en) * | 2010-10-01 | 2013-06-12 | 瓦里安半导体设备公司 | Method and system for modifying photoresist using electromagnetic radiation and ion implantion |
| CN103681254A (en) * | 2013-11-29 | 2014-03-26 | 上海华力微电子有限公司 | Method for improving fineness of edges of photoresistor |
-
2015
- 2015-10-09 CN CN201510648838.6A patent/CN106571291B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090263751A1 (en) * | 2008-04-22 | 2009-10-22 | Swaminathan Sivakumar | Methods for double patterning photoresist |
| CN101752205A (en) * | 2008-12-01 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Method for shrinking line-shaped pattern character size |
| CN102136415A (en) * | 2010-01-27 | 2011-07-27 | 中芯国际集成电路制造(上海)有限公司 | Method for improving roughness of line edge of photoetching pattern in semiconductor process |
| CN103003914A (en) * | 2010-03-15 | 2013-03-27 | 瓦里安半导体设备公司 | Method and system for modifying substrate patterned features using ion implantation |
| CN103155099A (en) * | 2010-10-01 | 2013-06-12 | 瓦里安半导体设备公司 | Method and system for modifying photoresist using electromagnetic radiation and ion implantion |
| CN103137564A (en) * | 2011-11-22 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for achieving expanding base region structure in bipolar-complementary metal oxide semiconductor (BiCMOS) device |
| CN103681254A (en) * | 2013-11-29 | 2014-03-26 | 上海华力微电子有限公司 | Method for improving fineness of edges of photoresistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106571291B (en) | 2019-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102335247B1 (en) | Image reversal with ahm gap fill for multiple patterning | |
| US11410860B2 (en) | Process chamber for etching low k and other dielectric films | |
| CN105762073B (en) | Method and apparatus for anisotropy tungsten etch | |
| CN106067442B (en) | Cobalt etches deeply | |
| CN106067418B (en) | Etching processing method | |
| TWI692799B (en) | Cleaning method | |
| TWI621155B (en) | Method for increasing pattern density in self-aligned patterning schemes without using hard masks | |
| TW201932635A (en) | Highly etch selective amorphous carbon film | |
| TWI355031B (en) | Post deposition plasma treatment to increase tensi | |
| TWI296132B (en) | Method of etching high aspect ratio features | |
| TWI627724B (en) | Apparatus and methods for spacer deposition and selective removal in an advanced patterning process | |
| CN104900511B (en) | Plasma-etching method and plasma-etching apparatus | |
| CN107464747A (en) | Use ALE and selective deposition etching substrate | |
| KR20160094893A (en) | Method for increasing pattern density in self-aligned patterning integration schemes | |
| KR20160102356A (en) | Material processing to achieve sub-10nm patterning | |
| TWI610362B (en) | Methods of surface interface engineering | |
| KR20190030182A (en) | Selective oxide etching method for self-aligned multiple patterning | |
| CN106571291A (en) | Pattern transfer method | |
| TWI756367B (en) | Method of quasi-atomic layer etching of silicon nitride | |
| Pu | Plasma Etch Equipment | |
| TW202121504A (en) | Method and system for capping of cores for self-aligned multiple patterning | |
| US8431461B1 (en) | Silicon nitride dry trim without top pulldown | |
| CN102610512B (en) | Method for forming front metal dielectric layer | |
| CN102623329B (en) | Method for forming front metal dielectric layer | |
| CN105895519A (en) | Residue free systems and methods for isotropically etching silicon in tight spaces |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 100176 No. 8 Wenchang Avenue, Beijing economic and Technological Development Zone Applicant after: Beijing North China microelectronics equipment Co Ltd Address before: 100176 Beijing economic and Technological Development Zone, Wenchang Road, No. 8, No. Applicant before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |