CN106569961A - Access address continuity-based cache module and access method thereof - Google Patents
Access address continuity-based cache module and access method thereof Download PDFInfo
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- CN106569961A CN106569961A CN201610965369.5A CN201610965369A CN106569961A CN 106569961 A CN106569961 A CN 106569961A CN 201610965369 A CN201610965369 A CN 201610965369A CN 106569961 A CN106569961 A CN 106569961A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses an access address continuity-based cache module and an access method thereof. The cache module comprises a plurality of caches defined by taking continuity as a principle, an address judgment and data return unit, and an interface conversion unit, wherein the caches include a Dcache which caches non-continuous access data and a Ccache which caches continuous access data; the address judgment and data return unit executes operations of monitoring an access behavior, judging address continuity and outputting a result to the Dcache and the Ccache, and executes data return operation; and the interface conversion unit executes operations of conversion from a system bus to a flash memory interface, and prefetching command transmission and cancellation of the caches. According to the cache module and the access method, data needed by a CPU is put in the caches in advance mainly through an access continuity law, so that the access speed is increased and the SOC performance is improved.
Description
【Technical field】
The present invention relates to integrated circuit SOC(system on a chip) (SOC) architecture design technical field, and in particular to one kind is based on memory access
The successional cache modules in address and its access method.
【Background technology】
Storage wall is a significant challenge during development of computer, governs the lifting of computing power.In SOC systems
Memory access speed is an important indicator of evaluation calculation machine performance in system.
In order to tackle storage wall problem, it is technology that industry develops one, such as using the storage system of stratification, and using pre-
Take, infer, instructing the technologies such as scheduling, thread scheduling.The target of these technologies is：Using the speed advantage of caching, CPU directly reads
Data in write buffer, farthest avoid accessing the memorizer of low speed low level.But the premise of CPU direct read/writes caching is
Target data must be backed up in the buffer.Nearly all designed using hierarchal memory in existing high-performance computer system.
In performance test benchmark (testing tool), stream is mainly used to test the memory access performance of CPU.
According to the various factors such as speed of hit rate, the complexity realized and speed, cache the replacement policy of cache have with
Machine method, first in first out, least recently used method etc..These replacement policies are applied in different scenes, there is different emphasis.
What Cache (Cache) replacement policy was utilized is the locality rule of program, reduces CPU and directly accesses
The probability of slow memory.But very important is that program memory access also has very strong regularity.For example, from programmed instruction
For angle, the instruction storage generated after compiling has very strong seriality, also always connects when the data of bulk are as an object
Continuous is distributed in memory space, and the structure of circulation also causes memory access address to become organic to follow.
【The content of the invention】
It is contemplated that from the seriality and regular angle of CPU memory access, there is provided a kind of cache moulds of acceleration memory access
Block and its access method, effectively lift CPU memory access performances.The present invention is realized by technical scheme below：
One kind is based on the successional cache modules in memory access address, is arranged at SOC system bus to the road of flash memory
On footpath, it is characterised in that the cache modules include：
The some pieces of cache divided as principle with seriality, including the Dcache for caching discontinuous memory access data and
Cache the Ccache of continuous memory access data；
Address judges and data returning unit, performs memory access behavior monitoring and address seriality judges and exports result
The operation of Dcache and Ccache, while performing the operation that data are returned；
Interface conversion unit, the conversion of execution system bus to flash memory interfaces and the prefetched command of cache are sent out
The operation for going out and cancelling.
Used as specific technical scheme, the Ccache includes：Cache line structures, data pre-fetching module and cache
Line replacement circuits；The cache line structures include two part contents:Initial item and prefetch item, initial item is continuous for each
Former data of data, the temporarily providing room for prefetching item and prefetching part for continuous data；It is right that described data pre-fetching module is used for
Below continuation address is prefetched, and the data being prefetched to are stored in and prefetch in item；Described cache line replacement circuits are used to replace
Change prefetch in item interior and perhaps replace whole cache line.
Used as specific technical scheme, memory access address seriality includes：Address is from the ground for increasing, address subtracts, shifts certainly
The regular change in location.
A kind of above-mentioned access method based on the successional cache modules in memory access address, it is characterised in that include：
(1) when memory access behavior is produced, cache hits are compared to be carried out in Dcache and Ccache simultaneously, if in cache
Hit then enters step (2A), otherwise into step (2B)；
(2A) current address is compared with last address, judge whether it is continuous and by result output Dcache with
Ccache, continuously then enters step (2A1), otherwise into step (2A2)；
(2A1) judge in Ccache that whether effectively data, are, by Ccache returned datas and prefetch continuation address below
Data, otherwise wait for flash memory returned datas；During prefetching, discontinuous request is such as received, then interrupted current
Prefetch；
(2A2) by Dcache returned datas, while judging whether Ccache disables the cache line for being not filled by completing；
(2B) judge whether address is continuous, continuously then enter step (2B1), discontinuously then enter step (2B2)；
(2B1) Ccache decides whether in current continuous memory access write cache line according to current replacement policy；
(2B2) judge whether the replacement policy for meeting Dcache, be then from flash memory returned datas and by data
In inserting Dcache, otherwise from flash memory returned datas；
(3) step (2) acquired results are returned to into system bus.
Used as specific technical scheme, in the case that the interruption is currently prefetched, the initial item of Ccache has not been filled,
The replacement policy of Ccache is determined when initial item is not filled by completing, if disable current cache line.
Used as specific technical scheme, the current replacement policy of the Ccache includes：Item is prefetched in cache line
When unfilled, if the cache line are displaced into Ccache；When Ccache is full, new cache line how are replaced；
How subset in continuous data is treated.
The beneficial effects of the present invention is：Memorizer at a slow speed is compared, this cache structures can effectively accelerate memory access speed
Degree；No matter which kind of CPU architecture, this cache structures can be conveniently applied in various SOC；For most of program
Speech, contains the substantial amounts of access for repeating seriality or regularity in memory access, the present invention is stronger to the acceleration effect of continuous memory access；
All of continuous data need not be stored in cache, it is only necessary to be stored in several before continuous data, reduce cache big
It is little, reduce circuit cost.
【Description of the drawings】
Fig. 1 is the structure chart of the bus system with memory access of SOC provided in an embodiment of the present invention.
Fig. 2 is the cache line structure charts of Ccache in cache modules provided in an embodiment of the present invention.
Fig. 3 is the memory access flow chart under cache modular structures provided in an embodiment of the present invention.
【Specific embodiment】
Technical scheme and beneficial effect to be illustrated the application becomes apparent from understanding, below in conjunction with the accompanying drawings and concrete real
Apply example to be described in detail：
As shown in figure 1, the bus system of a SOC, including CPU, DMA, system bus, flash memory and cache
Module, cache modules are arranged on the path of CPU to flash memory, in cache modules comprising Dcache, one
Ccache, address judge and data returning unit and interface conversion unit.Dcache is used to cache discrete memory access data,
Ccache is used to caching the cache of continuous data, the seriality in Ccache for specifically recognizable sequence, such as address certainly
Increase, subtract certainly, displacement etc..
It is assumed that in foregoing circuit, the access time of flash memory is 3 clock cycle, and can not streamlined.
As shown in Fig. 2 the number of initial item is 3 in Ccache each cache line, the number for prefetching item is 3.
As shown in figure 3, when memory access behavior is produced, address is judged with data returning unit current address and last address
Relatively, judge whether continuous and result is exported into Dcache and Ccache.Current address is sent in Dcache and Ccache, such as exists
Dcache hits then return hiting data, and if hitting in Ccache hiting data is returned, while Ccache hits,
Ccache can be prefetched, that is, carry out prefetching for the 3rd continuation address next.
Conversely, in the case where all cache do not hit, if discontinuously, Dcache roots Ju currently replaces plan
Cache line are slightly replaced, now memory access result needs to be taken out from flash memory.If continuous, Ccache is according to ought
Front replacement policy decides whether in current continuous memory access write cache line.While Ccache hits, Ccache
Can be prefetched.During prefetching, discontinuous request is such as received, then interrupt currently prefetching.
In the case that interruption is prefetched, the initial item of Ccache has not been filled, and the replacement policy of Ccache is determined in starting
When item is not filled by completing, if disable current cache line.There are corresponding enabler flags in each cache item, do not have
It is filled or corresponding mark is had by the cache items of disable.These marks control the hit of Ccache and prefetch.
Wherein, the current replacement policy of Ccache includes：Cache line prefetch item it is unfilled when, if by this
Cache line displace Ccache；When Ccache is full, how to replace new cache line, can adopt conventional LRU,
FIFO waits strategy with random；How subset in continuous data is treated, if subset contains identical starting item, can not
As new continuous data, because the mechanism that prefetches of Ccache ensure that the memory access performance of subset is unaffected.
The present invention mainly by the continuity rule of memory access, the data that CPU needs is placed in advance in cache, is accelerated
Memory access speed, improves the performance of SOC.
Above-described embodiment is only the fully open and unrestricted present invention, every according to present invention innovation purport and without creation
Property the i.e. obtainable equivalence techniques feature replacement of work and increase and decrease, all should belong to the invention discloses scope.
Claims (6)
1. it is a kind of to be based on the successional cache modules in memory access address, SOC system bus is arranged to the path of flash memory
On, it is characterised in that the cache modules include：
The some pieces of cache divided as principle with seriality, including the Dcache and caching that cache discontinuous memory access data
The Ccache of continuous memory access data；
Address judges and data returning unit, performs memory access behavior monitoring and address seriality judges and result is exported into Dcache
With the operation of Ccache, while perform data return operation；
Interface conversion unit, execution system bus to the conversion of flash memory interfaces and the prefetched command of cache send with
The operation of calcellation.
2. it is according to claim 1 based on the successional cache modules in memory access address, it is characterised in that the Ccache
Including：Cache line structures, data pre-fetching module and cache line replacement circuits；The cacheline structures include two
Part content:Initial item and item is prefetched, initial item is former data of each continuous data, prefetches item and prefetches for continuous data
Partial temporarily providing room；Described data pre-fetching module is used to prefetch continuation address below, and the data being prefetched to are stored in
In prefetching item；Described cache line replacement circuits are used to replacing prefetch in item interior and perhaps replace whole cache line.
3. it is according to claim 1 based on the successional cache modules in memory access address, it is characterised in that the memory access ground
Location seriality includes：Address is from the regular change in address for increasing, address subtracts, shifts certainly.
4. the access method of the successional cache modules in memory access address is based on described in a kind of claim 3, it is characterised in that bag
Include：
(1) when memory access behavior is produced, cache hits are compared to be carried out in Dcache and Ccache simultaneously, if in cache hits
Step (2A) is then entered, otherwise into step (2B)；
(2A) current address is compared with last address, judges whether continuous and result is exported into Dcache and Ccache, even
It is continuous then enter step (2A1), otherwise into step (2A2)；
(2A1) judge in Ccache that whether effectively data, are, by Ccache returned datas and prefetch the number of continuation address below
According to otherwise waiting for flash memory returned datas；During prefetching, discontinuous request is such as received, then interrupt currently prefetching；
(2A2) by Dcache returned datas, while judging whether Ccache disables the cache line for being not filled by completing；
(2B) judge whether address is continuous, continuously then enter step (2B1), discontinuously then enter step (2B2)；
(2B1) Ccache decides whether in current continuous memory access write cache line according to current replacement policy；
(2B2) judge whether the replacement policy for meeting Dcache, inserted from flash memory returned datas and by data
In Dcache, otherwise from flash memory returned datas；
(3) step (2) acquired results are returned to into system bus.
5. access method according to claim 4, it is characterised in that in the case that the interruption is currently prefetched, Ccache
Initial item do not filled, the replacement policy of Ccache is determined when initial item is not filled by completing, if disable is current
cache line。
6. the access method according to claim 4 or 5, it is characterised in that the current replacement policy of the Ccache includes：
Cache line prefetch item it is unfilled when, if the cache line are displaced into Ccache；When Ccache is full, how
Replace new cache line；How subset in continuous data is treated.
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| CN201610965369.5A CN106569961B (en) | 2016-10-31 | 2016-10-31 | Cache module based on memory access continuity and memory access method thereof |
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| CN201610965369.5A CN106569961B (en) | 2016-10-31 | 2016-10-31 | Cache module based on memory access continuity and memory access method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112256599A (en) * | 2019-07-22 | 2021-01-22 | 华为技术有限公司 | Data prefetching method and device and storage device |
| WO2021184141A1 (en) * | 2020-03-15 | 2021-09-23 | Micron Technology, Inc. | Pre-load techniques for improved sequential read |
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| WO2021184141A1 (en) * | 2020-03-15 | 2021-09-23 | Micron Technology, Inc. | Pre-load techniques for improved sequential read |
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| CN106569961B (en) | 2023-09-05 |
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