CN106569533B - Adaptive reference circuit with wide voltage withstanding range, chip and communication terminal - Google Patents

Adaptive reference circuit with wide voltage withstanding range, chip and communication terminal Download PDF

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CN106569533B
CN106569533B CN201610517824.5A CN201610517824A CN106569533B CN 106569533 B CN106569533 B CN 106569533B CN 201610517824 A CN201610517824 A CN 201610517824A CN 106569533 B CN106569533 B CN 106569533B
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李艳丽
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Vanchip Tianjin Electronic Technology Co Ltd
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Abstract

The invention discloses a wide voltage withstanding range self-adaptive reference circuit, a chip and a communication terminal. The self-adaptive reference circuit comprises a biasing circuit, a reference voltage generating circuit, a dynamic voltage divider control circuit and a dynamic voltage divider; the bias circuit provides bias current for the reference voltage generating circuit; the reference voltage generating circuit generates reference voltage by using a resistor according to the bias current; the dynamic voltage divider control circuit is connected with the dynamic voltage divider and provides bias voltage for the dynamic voltage divider; the dynamic voltage divider is arranged between the PMOS tube and the NMOS tube of the bias circuit; the bias voltage changes along with the change of the power supply voltage, so that the voltage born by the dynamic voltage divider changes, and the transistor in the error amplifier is ensured to work in a nominal voltage range.

Description

Adaptive reference circuit with wide voltage withstanding range, chip and communication terminal
Technical Field
The invention relates to a self-adaptive reference circuit with a wide voltage withstanding range, and also relates to an integrated circuit chip adopting the self-adaptive reference circuit and a corresponding communication terminal, belonging to the technical field of integrated circuits.
Background
With the continuous development of integrated circuit technology, the corresponding chip size is smaller and smaller, and the voltage withstanding grade is lower and lower. However, in the power supply system of the existing communication terminal, the power supply voltage is mostly maintained in a wide range, which presents a great challenge for applying to the low-voltage process device in the high-voltage environment. The low-voltage process device is directly connected to a high-voltage environment, so that the problems of device breakdown, burning and the like are easily caused, and the normal operation of an integrated circuit chip and a corresponding communication terminal is seriously influenced.
The reference voltage generating circuit is an important unit module in an integrated circuit chip and is widely applied to analog and hybrid circuits. Whether the output of the reference voltage generating circuit is stable is one of the key factors related to the working accuracy of each functional module. The reference voltage generating circuit is generally directly connected with a power supply voltage, and with the rise of the power supply voltage, the voltage difference of the transistor end exceeds the voltage withstanding value of the process nominal of the transistor end, so that the device is in danger of burning. Therefore, it is necessary to operate each device below the nominal breakdown voltage by proper design.
In chinese patent application No. 201510564335.0, a self-biased bandgap reference circuit with a wide input voltage range and a high precision output is disclosed. The reference circuit comprises a self-bias unit connected to a power supply, the self-bias unit comprises a mirror image unit and a following unit, a first power supply input end and a second power supply input end of the mirror image unit are respectively connected to the power supply, and a first output end and a second output end of the mirror image unit are respectively connected to the following unit and are used for generating two paths of current value signals with the same size and outputting the current value signals to the following unit; the first input end and the second input end of the following unit are respectively connected to the first output end and the second output end of the mirror image unit, the third input end of the following unit is connected to the drain electrode of the first P-type MOS tube and the drain electrode of the first N-type MOS tube, the fourth input end of the following unit is connected to the drain electrode of the second P-type MOS tube and the drain electrode of the second N-type MOS tube, and the grounding end of the following unit is grounded. The self-bias structure in the technical scheme can effectively reduce the voltage difference of the bias point under the high power voltage, improve the matching precision and further improve the precision of the output reference voltage.
Disclosure of Invention
The invention provides an adaptive reference circuit with a wide voltage withstanding range.
Another technical problem to be solved by the present invention is to provide an integrated circuit chip using the adaptive reference circuit and a corresponding communication terminal.
In order to achieve the purpose, the invention adopts the following technical scheme:
according to a first aspect of the embodiments of the present invention, there is provided an adaptive reference circuit with a wide withstand voltage range, including a bias circuit and a reference voltage generating circuit, and further including a dynamic voltage divider control circuit and a dynamic voltage divider;
the bias circuit provides bias current for the reference voltage generating circuit; the reference voltage generating circuit generates reference voltage by using a resistor according to the bias current;
the dynamic voltage divider control circuit is connected with the dynamic voltage divider and provides bias voltage for the dynamic voltage divider; the dynamic voltage divider is arranged between a PMOS tube and an NMOS tube of the bias circuit;
the bias voltage changes along with the change of the power supply voltage, so that the voltage born by the dynamic voltage divider changes, and the transistor in the error amplifier is ensured to work in a nominal voltage range.
Preferably, the system also comprises a starting circuit; one end of the starting circuit is connected with a power supply voltage, the other end of the starting circuit is grounded, and one end of the starting circuit is connected with a drain electrode of a PMOS (P-channel metal oxide semiconductor) tube of the biasing circuit.
Preferably, the system also comprises a PTAT current source; the PTAT current source is connected between the bias circuit and ground for providing a reference current for the bias circuit.
Preferably, the dynamic voltage divider control circuit is implemented by connecting a plurality of MOS tubes with a resistor in series.
Preferably, the dynamic voltage divider is implemented by connecting a resistor and an MOS tube in parallel.
Preferably, under the condition that the power supply voltage is lower, the resistance parameter value of the dynamic voltage divider is determined by the on-resistance of the MOS tube; in the case of a high supply voltage, the value of the resistance parameter of the dynamic voltage divider is determined by the resistance.
Preferably, the bias circuit mirrors a current provided by the PTAT current source to the reference voltage generating circuit by a mirror multiple as the bias current.
Preferably, the maximum withstand voltage value of the adaptive reference circuit is determined by the product of the resistance parameter value of the dynamic voltage divider and the mirror multiple of the current provided by the PTAT current source.
According to a second aspect of the embodiments of the present invention, an integrated circuit chip is provided, in which the above adaptive reference circuit is included.
According to a third aspect of the embodiments of the present invention, there is provided a communication terminal including the above adaptive reference circuit therein.
Compared with the prior art, the self-adaptive reference circuit provided by the invention can automatically adjust the voltage division value of the dynamic voltage divider along with the change of the power supply voltage, thereby ensuring that each transistor works in the nominal voltage range required by the process. And the quiescent current of the adaptive reference circuit does not change along with the change of the power supply voltage.
Drawings
Fig. 1 is a circuit schematic diagram of an adaptive reference circuit provided in embodiment 1 of the present invention;
fig. 2 is a circuit schematic diagram of an adaptive reference circuit provided in embodiment 2 of the present invention;
fig. 3 is a block diagram of a communication terminal shown in accordance with an example embodiment.
Detailed Description
The technical contents of the invention are described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, an adaptive reference circuit provided in embodiment 1 of the present invention includes a start-up circuit 101, a dynamic divider control circuit 102, a PTAT current source 103, dynamic dividers 201A, 201B, and 201C, a bias circuit 104, and a reference voltage generation circuit 105. One end of the start-up circuit 101 is connected to the power supply voltage VDD, the other end is grounded, and the other end is connected to the drain of the PMOS transistor in the bias circuit 104. The dynamic voltage divider control circuit 102 has one terminal connected to the power supply voltage VDD and the other terminal connected to ground for controlling the actual resistance values of the dynamic voltage dividers 201A, 201B and 201C. One end of the dynamic voltage divider 201A, 201B is connected to the drain of the PMOS transistor (M3, M4) in the bias circuit 104, and the other end is connected to the drain of the NMOS transistor (M5, M6) in the bias circuit 104. The reference voltage generation circuit 105 is formed by connecting a dynamic voltage divider 201C, a resistor R3, and a diode D3 in series, and has one end connected to a bias current source in the bias circuit 104 and the other end grounded. In the reference voltage generation circuit 105, the resistor R3 functions to generate the reference voltage Vref. One end of the dynamic voltage divider 201C is connected to the other dynamic voltage divider 201B, the other end is connected to a resistor R3 for generating a reference voltage Vref, and the other end is connected to a PMOS transistor M7.
Fig. 2 is a circuit schematic diagram of embodiment 2 of the adaptive reference circuit provided by the present invention. In embodiment 2, the start-up circuit 101, the dynamic voltage divider control circuit 102, the PTAT current source 103, the dynamic voltage dividers 201A, 201B, and 201C, the bias circuit 104, the reference voltage generating circuit 105, and the like are also included, and the overall connection mode and the operation principle are substantially the same as those of embodiment 1, and thus, detailed description thereof is omitted here.
In embodiment 2, the start-up circuit 101 is composed of two PMOS transistors M1 and M2 and a resistor R1, wherein the source of the PMOS transistor M1 is connected to the power supply voltage VDD, the gate thereof is connected to the gates of the PMOS transistors M3, M4 and M7 in the bias circuit 104, and the drain thereof is connected to the resistor R1 and the gate of the PMOS transistor M2. The source of the PMOS transistor M2 is also connected to the power supply voltage VDD, and the drain is connected to the drain of the PMOS transistor M3. The PTAT current source 103 is composed of diodes D1, D2 and a resistor R2, and is used to provide a reference current for the bias circuit 104. The negative ends of the diodes D1 and D2 are connected to ground, the positive end of D1 is connected to the source of the NMOS transistor M5 in the bias circuit 104, the positive end of D2 is connected to one end of a resistor R2, and the other end of the resistor R2 is connected to the source of the NMOS transistor M6 in the bias circuit 104.
In embodiment 2 shown in fig. 2, the bias circuit 104 is mainly composed of PMOS transistors M3, M4, and M7, and NMOS transistors M5, M6. The gate and the drain of the NMOS transistor M5 are connected to the gate of the NMOS transistor M6, and are connected to one end of the dynamic voltage divider 201A. The drain of the PMOS transistor M3 is connected to the other end of the dynamic voltage divider 201A, the drain of the NMOS transistor M6 is connected to one end of the dynamic voltage divider 201B, and the drain and gate of the PMOS transistor M4 are connected to the other end of the dynamic voltage divider 201B together with the gates of the PMOS transistors M3 and M7. The source of the PMOS transistor M3, the source of M4, and the source of M7 are connected together to the power supply voltage VDD, and the drain of M7 is connected to one end of the dynamic voltage divider 201C in the reference voltage generation circuit 104. In the reference voltage generating circuit 105, one end of the resistor R3 is connected to the positive terminal of the diode D3, the other end is connected to one end of the dynamic voltage divider 201C, and the negative terminal of the diode D3 is connected to ground.
In embodiment 2 shown in fig. 2, the dynamic voltage divider control circuit 102 is implemented by connecting a plurality of MOS transistors (M8-M12) in series with a resistor R3. The dynamic voltage dividers 201A, 201B and 201C are also implemented with resistors (R4, R5, R6) in parallel with corresponding NMOS transistors (N1, N2, N3). In the dynamic voltage dividers 201A, 201B, and 201C, the respective MOS transistor gate voltages are provided by the dynamic voltage divider control circuit 102 via pin 302. The dynamic voltage divider control circuit 102 also samples the drain voltages of the PMOS transistors M3, M4 of the bias circuit 104, which follow the supply voltage VDD, via pin 301. In the dynamic voltage divider control circuit 102, one end of a resistor R3 is connected to a power supply voltage VDD, the other end is connected to the source of a PMOS transistor M8, the gates of the PMOS transistor M8 and an NMOS transistor M9 are connected to the drains and gates of the PMOS transistor M3 and the NMOS transistor M4, the gate of an NMOS transistor M10 is connected to the source and to the source of an NMOS transistor M9, the gate of the NMOS transistor M11 is connected to the source and to the source of an NMOS transistor M10, and the gate of the NMOS transistor M12 is connected to the source and to the source of an NMOS transistor M11. The NMOS transistors M10, M11, and M12 are used to divide the power voltage VDD, so as to ensure that all transistors in the dynamic voltage divider control circuit 102 operate within the rated voltage range.
Compared with the existing reference voltage generating circuit, the invention has the remarkable characteristic that the dynamic voltage dividers 201A, 201B and 201C which can be automatically adjusted under different power supply voltages and the corresponding dynamic voltage divider control circuit 102 are added. One terminal of the dynamic voltage divider control circuit 102 is connected to the power voltage and the other terminal is connected to the ground, so as to control the actual resistance values of the dynamic voltage dividers 201A, 201B, and 201C. This actual resistance value varies with variations in the power supply voltage, as will be described in more detail later. One end of the dynamic voltage divider 201A, 201B is connected to the drains of PMOS transistors M3, M4 in the bias circuit 104, and the other end is connected to the drains of NMOS transistors M5, M6 in the bias circuit 104, which is used to bear the voltage drop of the power voltage VDD applied to the PTAT current source 103 and the bias circuit 104. The bias circuit 104 is used to provide a bias current to the reference voltage generating circuit 105. In the reference voltage generation circuit 105, one end of the dynamic voltage divider 201C is connected to the PTAT current source 103, and the other end is connected to a resistor R3 that generates the reference voltage Vref.
The bias voltage provided by the dynamic voltage divider control circuit 102 to the dynamic voltage divider varies with the supply voltage when the reference voltage generation circuit 105 starts operating. The dynamic voltage dividers 201A and 201B in the bias circuit 104 are connected in series between the PMOS transistor and the NMOS transistor of the bias circuit, and the dynamic voltage divider 201C in the reference voltage generating circuit 105 is connected in series between the PTAT current source 103 and the resistor R3 for generating a voltage drop. As the supply voltage VDD increases, the voltage carried by the dynamic voltage dividers 201A, 201B, and 201C increases, thereby ensuring that the voltage difference between the respective ports of all transistors in the PTAT current source 103, the bias circuit 104, and the reference voltage generating circuit 105 is maintained within the nominal voltage range of their process requirements. The detailed description is made below by way of specific calculation examples.
Referring to the schematic circuit diagram of embodiment 2 shown in fig. 2, in embodiment 2, the emitter junction areas of diodes D1 and D2 in PTAT current source 103 are set to be different, and assuming that the emitter junction area ratio of D1 to D2 is 1: N, the currents flowing through diodes D1 and D2 are equal to:
Figure GDA0001219854170000051
wherein, VTkT/q is proportional to temperature. It can be seen from this that IPTATIs a positive temperature coefficient current.
As mentioned above, the PTAT current source 103 supplies the bias current to the reference voltage generating circuit 105 through the bias circuit 104. The bias circuit 104 mirrors the current provided by the PTAT current source 103 to the reference voltage generating circuit 105 by a mirror multiple. Assuming that the mirror multiples of the PMOS transistors M3, M4, and M7 are 1: M, the reference voltage can be expressed as:
VrBf＝M×IPTAT×R3+VBE3(2)
combining equation (1) and equation (2), one can obtain:
Figure GDA0001219854170000061
wherein, VBEHas a negative temperature coefficient.
Therefore, through a reasonable current mirror multiple M, resistors R2 and R3, an emitting junction area ratio of 1: the reference voltage which does not change along with the temperature can be obtained by the parameter value of N.
Assuming that a stable reference voltage has been obtained by reasonable values, the output current of the PTAT current source 103 is a fixed value at this time. It is understood that the currents in the two branches of the bias circuit 104 are fixed and do not change with the change of the power supply voltage. At this time, the drain voltage of the PMOS transistor M3 (i.e. the voltage at the pin 301) with the drain connected to the gate varies linearly with the power voltage, and the voltage at the pin 301 can be expressed as:
V301＝VDD-Vsg(M3)(4)
here, Vsg (M3) is the voltage difference between the source and the gate of the PMOS transistor M3. Since the PMOS transistor M3 operates in the saturation region, the current-voltage relationship can be expressed as:
Figure GDA0001219854170000062
wherein up is hole mobility, Cox is gate oxide capacitance per unit area, and Vtp is the turn-on voltage of the PMOS transistor.
Due to the current IPTATIs a fixed value, therefore, the voltage difference between the source and the gate of the PMOS transistor M3 is Vsg(M3)Is a fixed value and does not change with changes in the power supply voltage.
In the dynamic voltage divider control circuit 102, the voltage difference between the source and the gate of the PMOS transistor M8 is:
Vsg(M8)＝VDD-I101R3-V301(6)
when the PMOS transistor M8 operates in the saturation region, the voltage difference between the source and the gate can be expressed as:
Figure GDA0001219854170000071
combining equation (4), equation (6) and equation (7) yields:
Figure GDA0001219854170000072
it can be seen from equation (8) that the quiescent current of the dynamic voltage divider of the present invention does not change with the change of the power supply voltage, and can be controlled to a very small value in practice.
Under the condition that the power supply voltage is low, the voltage at the pin 301 is low, and since the MOS transistors M10, M11, and M12 which have a voltage division function bear a part of the voltage, at this time, the gate voltages of the NMOS transistors N1, N2, and N3 are high, the corresponding on-resistances are small, the NMOS transistors N1, N2, and N3 in the dynamic voltage divider have a main voltage division function, and at this time, the voltage division of the PMOS transistors M3 and M4 and the voltage division of the NMOS transistors M5 and M6 in the bias circuit are small, so that each transistor in the bias circuit can normally operate in a saturation region.
Under the condition that the power supply voltage is higher, the voltage at the pin 301 is increased, and the voltage at the pin 302 is decreased, so that the on-resistances of the NMOS transistors N1, N2 and N3 are larger, and are respectively connected in parallel with R4, R5 and R6 for voltage division. As the supply voltage continues to rise, the voltage at the pin 302 further decreases, and the on-resistances of N1, N2, and N3 are much greater than the respective parallel resistances R4, R5, and R6. At this time, the resistors R4, R5, and R6 function as main voltage division. The use of the resistors R4, R5, and R6 also prevents the problem that the reference voltage generating circuit 105 cannot operate normally due to the excessive on-resistances of N1, N2, and N3.
Next, the process of taking values of the resistors R4 and R5 will be described.
Assuming a maximum supply voltage, resistors R4 and R5 play a dominant role, and R4-R5-R, the voltage taken by the dynamic voltage divider in the bias circuit can be expressed as:
V201＝IPTAT*R (9)
assuming that the divided voltage value of the dynamic voltage divider in the bias circuit is zero, the maximum power supply voltage value VDD1 that can be borne by the path formed by the bias circuit and the PTAT current source is:
VDD1＝|Vtp|+Vtn+IPTATR2+VBE2(10)
the portion of the voltage of the power supply voltage exceeding VDD1 is assumed by the dynamic voltage divider in the bias circuit, i.e., the voltage sustained by the dynamic voltage divider in the bias circuit must satisfy equation (11):
V201≥VDDmax-|Vtp|+Vtn+IPTATR2+VBE2(11)
wherein Vtn is the starting voltage of the PMOS tube.
Combining equation (9) and equation (11), we can find that the resistance R must satisfy the constraint of equation (12):
R≥(VDDmax-|Vtp|-Vtn-IPTATR2-VBE2)/IPTAT(12)
assuming that the divided voltage value of the dynamic voltage divider in the reference voltage generating circuit 105 is zero, the maximum voltage VDD2 that the reference voltage generating circuit can bear is:
VDD2＝Vd3+MIPTATR3+VBE3(13)
wherein Vds is the voltage difference between the source and the drain of the PMOS transistor M7.
The portion of the voltage of the power supply voltage exceeding VDD2 is assumed by the dynamic voltage divider of the reference voltage generation circuit 105, i.e. the voltage taken by the dynamic voltage divider of the reference voltage generation circuit 105 must satisfy equation (14):
V201C≥VDDmax-Vds-MIPTATR3-VBE3(14)
assuming that the resistance R6 is much larger than the on-resistance of the NMOS transistor N3 at the maximum supply voltage, the voltage assumed by the dynamic voltage divider of the reference voltage generation circuit 105 can be expressed as:
V201C＝MIPTAT*R6(15)
combining equation (14) and equation (15), it can be seen that the resistance R6 must satisfy the constraint of equation (16):
R6≥(VDDmax-Vds-NIPTATR3-VBE3)/MIPTAT(16)
as can be seen from the equations (12) and (16), as long as the current value of the PTAT current source 103 and the mirror image multiple M are given, the maximum withstand voltage value that the adaptive reference circuit provided by the present invention can withstand can be adjusted by changing the values of R and R3. Specifically, the maximum withstand voltage of the adaptive reference circuit is determined by the product of the resistance parameter value of the dynamic voltage divider and the mirror multiple of the current supplied by the PTAT current source.
In summary, the adaptive reference circuit provided by the present invention can automatically adjust the divided voltage value of the dynamic voltage divider along with the change of the power voltage, thereby ensuring that each transistor works in the nominal voltage range required by its process. And the quiescent current of the adaptive reference circuit does not change along with the change of the power supply voltage.
The adaptive reference circuit with a wide withstand voltage range shown in the above embodiments may be used in an integrated circuit chip (e.g., a power management type chip) to implement a supply function of a power supply voltage. The specific structure of the adaptive reference circuit in the integrated circuit chip is not described in detail herein.
In addition, the adaptive reference circuit can also be used in a communication terminal as an important component of a power management circuit. Fig. 3 is a block diagram of a communication terminal shown in accordance with an example embodiment. The communication terminal herein refers to a computer device that can be used in a mobile environment and supports multiple communication systems, such as GSM, EDGE, TD _ SCDMA, TDD _ LTE, FDD _ LTE, and the like, and includes, but is not limited to, a mobile phone, a notebook computer, a tablet computer, a vehicle-mounted computer, and the like. Referring to fig. 3, the communication terminal may include one or more of the following components: processing components, memory, power components, multimedia components, audio components, input/output (I/O) interfaces, sensor components, and communication components. In these components, a power management circuit including the above adaptive reference circuit is employed.
The processing components typically control the overall operation of the device, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing components may include one or more processors to execute instructions to perform all or a portion of the steps of the above-described methods. Further, the processing component can include one or more modules that facilitate interaction between the processing component and other components. For example, the processing component may include a multimedia module to facilitate interaction between the multimedia component and the processing component.
The memory is configured to store various types of data to support operations on the communication terminal. Examples of such data include instructions for any application or method operating on the communication terminal, contact data, phonebook data, messages, pictures, videos, etc. The memory may be implemented by any type or combination of volatile or non-volatile storage devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
The power components provide power to the various components of the communication terminal. The power components may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the communication terminal.
The multimedia component includes a screen providing an output interface between the communication terminal and the user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the communication terminal is in an operation mode, such as a photographing mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The audio component is configured to output and/or input an audio signal. For example, the audio component includes a Microphone (MIC) configured to receive an external audio signal when the communication terminal is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal may further be stored in a memory or transmitted via a communication component. In some embodiments, the audio assembly further comprises a speaker for outputting audio signals.
The I/O interface provides an interface between the processing component and a peripheral interface module, which may be a keyboard, click wheel, button, etc. These buttons include, but are not limited to: a home button, a volume button, a start button, and a lock button.
The sensor assembly includes one or more sensors for providing various aspects of status assessment for the communication terminal. For example, the sensor assembly may detect the open/closed state of the communication terminal, the relative positioning of components, such as the display and keypad of the communication terminal, the sensor assembly may also detect a change in the position of the communication terminal or a component of the communication terminal, the presence or absence of user contact with the communication terminal, the orientation or acceleration/deceleration of the communication terminal and a change in the temperature of the communication terminal. The sensor assembly may include a proximity sensor configured to detect the presence of a nearby object in the absence of any physical contact. The sensor assembly may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component is configured to facilitate wired or wireless communication between the communication terminal and other devices. The communication terminal may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
The adaptive reference circuit, the chip and the communication terminal provided by the invention are explained in detail above. Any obvious modifications to the invention, which would occur to those skilled in the art, without departing from the true spirit of the invention, would constitute a violation of the patent rights of the invention and would carry a corresponding legal responsibility.

Claims (8)

1. A self-adaptive reference circuit with wide voltage withstanding range comprises a bias circuit and a reference voltage generating circuit, and is characterized by also comprising a dynamic voltage divider control circuit and a dynamic voltage divider;
the dynamic voltage divider is arranged between a PMOS tube and an NMOS tube of the bias circuit; the bias circuit provides bias current for the reference voltage generating circuit; the reference voltage generating circuit generates reference voltage by using a resistor according to the bias current;
the dynamic voltage divider control circuit is connected with the dynamic voltage divider and provides bias voltage for the dynamic voltage divider, and the bias voltage changes along with the change of the power supply voltage;
the dynamic voltage divider is realized by connecting a resistor and an MOS (metal oxide semiconductor) tube in parallel; under the condition that the power supply voltage is low, the resistance parameter value of the dynamic voltage divider is determined by the on-resistance of the MOS tube; in the case of a high supply voltage, the value of the resistance parameter of the dynamic voltage divider is determined by the resistance, and the voltage assumed increases as the supply voltage increases, thereby ensuring that the transistors in the error amplifier operate within a nominal voltage range.
2. The adaptive reference circuit of claim 1, further comprising a start-up circuit; one end of the starting circuit is connected with a power supply voltage, the other end of the starting circuit is grounded, and one end of the starting circuit is connected with a drain electrode of a PMOS (P-channel metal oxide semiconductor) tube of the biasing circuit.
3. The adaptive reference circuit of claim 1, further comprising a PTAT current source; the PTAT current source is connected between the bias circuit and ground for providing a reference current for the bias circuit.
4. An adaptive reference circuit according to any one of claims 1 to 3, wherein:
the dynamic voltage divider control circuit is realized by connecting a plurality of MOS tubes with a resistor in series.
5. An adaptive reference circuit according to any one of claims 1 to 3, wherein:
the bias circuit mirrors the current provided by the PTAT current source to the reference voltage generating circuit according to the mirror image multiple, and the current is used as the bias current.
6. The adaptive reference circuit of claim 5, wherein:
the maximum withstand voltage value of the adaptive reference circuit is determined by the product of the resistance parameter value of the dynamic voltage divider and the mirror multiple of the current provided by the PTAT current source.
7. An integrated circuit chip, wherein the adaptive reference circuit of any one of claims 1 to 6 is included in the integrated circuit chip.
8. A communication terminal, characterized in that the communication terminal comprises the adaptive reference circuit of any one of claims 1-6.
CN201610517824.5A 2016-06-30 2016-06-30 Adaptive reference circuit with wide voltage withstanding range, chip and communication terminal Active CN106569533B (en)

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