CN106560989B - For driving the method and corresponding equipment of controlled resonant converter - Google Patents
For driving the method and corresponding equipment of controlled resonant converter Download PDFInfo
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Abstract
This disclosure relates to for driving the method, corresponding equipment and computer program product of controlled resonant converter.Controlled resonant converter includes: primary switching circuit, at least with armature winding and for drive armature winding primary full-bridge switch grade and with the resonant inductor of primary windings connected in series；Secondary resonant circuits have the secondary windings for being magnetically coupled to armature winding and the resonant capacitor in parallel for being electrically connected to secondary windings；Secondary commutation grade, parallel connection are electrically connected to resonant capacitor；And drive module.Drive module is configured for: the signal for indicating to step up the voltage of portion's switch half-bridge or lower switches half bridge measurement is received in input；The presence of negative voltage is detected in the signal；At each circulation, the control signal for being used to control the switch of the upper switches half-bridge or lower switches half-bridge to activate in next switch cycles is translated into the time in advance, which decreases up in each circulation meets the condition that negative voltage is not present in the signal.
Description
Technical field
This disclosure relates to controlled resonant converter.More particularly, this disclosure relates to for driving the technology of full-bridge controlled resonant converter.
Background technique
The power distribution of server and data centre sphere is undergoing continuous evolution.The continuous hair of these electronic equipments
The maximization of the efficiency for the voltage changer for needing to power to it is opened up, to minimize power required for delivering equal-wattage,
To limit the heat dissipation that they are installed in environment therein and to limit the power that corresponding cooling equipment uses.
There are various potential distribution systems, are powered as line voltage and are converted into down to required for processor
The various voltage levels of voltage VCPU.Currently, line voltage is transformed into the first voltage distributed on main power bus, so
It is transformed into the lower second voltage (usually 12V) distributed on centre bus afterwards, and is finally transformed into for locating
Manage the voltage VCPU of the power supply of device.For the efficiency of the system of optimized processor upstream, the voltage of main power bus is 48V.
However, some applications need direct transformation of the voltage from Vin=48V to Vout=1.2V, without by being used for 12V
The intermediate conversion of bus, for supplying CPU and DDR (double data rate) memory.
Other application needs the direct transformation between Vin=54V and Vout=12V instead.
Summary of the invention
In the scene previously provided, therefore feel to need a kind of for driving the technology of full-bridge controlled resonant converter, general
Realize the improvement of efficiency and the reduction to electromagnetic interference.
This can reversely be realized by preventing from electric current occur in the equipment for driving full-bridge resonance potential converter.
Particularly, by preventing the connection of the diode in the transistor as primary side switch, since there is no by crystalline substance
Loss caused by diode in body pipe and obtain being efficiently modified for efficiency.
The purpose of one or more embodiments is to meet requirements above.
One or more embodiments realize object above due to the method with the characteristic provided in appended claims.
Method described herein for driving controlled resonant converter, controlled resonant converter include:
Primary switching circuit, at least has armature winding and primary full-bridge switch grade, and primary full-bridge switch grade is configured to use
In drive above-mentioned armature winding and with the resonant inductor of primary windings connected in series,
There is secondary resonant circuits the secondary windings for being magnetically coupled to armature winding and parallel connection to be electrically connected to secondary windings
Resonant capacitor,
Secondary commutation grade, parallel connection are electrically connected to resonant capacitor, and
Drive module is configured for:
The signal for indicating to step up the voltage of portion's switch half-bridge or lower switches half bridge measurement is received in input,
Negative voltage is detected in the signal for indicating to step up the voltage for stating upper switches half-bridge or lower switches half bridge measurement
In the presence of,
At each circulation, it will be used to control the upper switches half-bridge to be activated in next switch cycles or lower part opened
The control signal for closing the switch of half-bridge translates the time in advance, and the translation time is reduced in each circulation, until meet indicate across
The condition of negative voltage is not present in the signal of the voltage of above-mentioned upper switches half-bridge or lower switches half bridge measurement.
One or more embodiments can be related to corresponding equipment and computer program product, computer program product can
It is loaded into the memory of at least one computer equipment and including for when product is run at least one computer
The software code partition of the step of Shi Zhihang above method.As used herein, for such computer program product
Reference be understood to be equal to comprising coordinating realization according to the method for the present invention for controlling computer system
The reference of the computer readable device of instruction.The present invention, which can use mould, to be emphasized to the reference intention of " at least one computer equipment "
Block and/or distributed form are realized.
Claim forms the component part of the description of one or more embodiments provided herein.
Detailed description of the invention
One or more embodiments only are described as non-limiting example referring now to the drawings, in the accompanying drawings:
Fig. 1 shows the example of controlled resonant converter；
Fig. 2 shows the timing diagrams of the main signal flowed in converter；
Fig. 3 shows the equivalent circuit of the primary side with highlighted parasitic capacitance；
Fig. 4,5 and 6 show three possible situations of the selection according to delay Tshift；
Fig. 7 illustrates how to realize the equilibrium condition of Fig. 6；
Fig. 8 shows the timing diagram of the main signal flowed in converter；
Fig. 9 indicates being able to achieve for drive module；
Figure 10 shows the variation of the voltage threshold when identifying under-voltage；And
Figure 11,12 and 13 show the timing diagram for being shown to illustrate how to determine the value of delay Tshift.
Specific embodiment
Illustrate one or more details in being described below, it is desirable to provide to the depth as exemplary various embodiments
Understand.Can without one or more of these specific details or use other methods, composition, material etc.
To obtain these embodiments.In other cases, without indicating or describing known structure, material or operation, Yi Mianmo in detail
Paste some aspects of embodiment.
The reference of " embodiment " or " one embodiment " is intended to indicate that in the context of this description and is described about the example
Specific configuration, structure or characteristic is included at least one embodiment.Therefore, it can reside at the one of this description
Or the phrases such as " in embodiment " or " in one embodiment " of many places are not necessarily referring to same example.In addition,
In one or more embodiments, specific configuration, structure or characteristic can be combined in any suitable manner.
Appended drawing reference used herein is simple to facilitating and providing, therefore do not define protection scope or example
Range.
Scope of the present application is full-bridge controlled resonant converter, and schematic diagram indicates in Fig. 1.
In Fig. 1, switch M1-M2-M3-M4-M5-M6 is realized via transistor.For example, proposing and illustrating in the accompanying drawings
Embodiment in, be used in the MOSFET (metal oxide semiconductor field effect transistor that uses of on/off (on/off) or switching mode
Pipe) it is switched to realize.
In the following description, in the range of transistor works in the operating area that it shows as switch, term " is opened
Pass " and " transistor " indistinguishably use.
MOS transistor M1-M2-M3-M4 forms full-bridge converter: M2 and M4 is referred to as " high-pressure side power transistor ", and
M1 and M3 is referred to as " low side power transistor ".
In such converter, the control of pairs of the MOS transistor M1-M2 and M3-M4 of primary side is driven to believe
Number translated time Tshift=Tres, wherein Tres is the typical resonance time (referring to fig. 2) of network Lres-Cres.
Since component Lres and Cres have intrinsic process spread, so in general, translation time Tshift is selected as greatly
In time Tresmax (Tshift > Tresmax), wherein Tresmax is in the process spread for considering component Cres and Lres
The maximum resonance period obtained in the case where worst condition.
Indicate that the signal obtained on node PHX and PHY, node PHX and PHY are hereafter referred to collectively as " node in Fig. 2
PHASE ", and the electric current in inductor Lres and therefore flowed in movable MOS transistor is indicated in Fig. 2.
As illustrated in Figure 2, it is seen then that low side transistor M1 and M3 connection (PHX and PHY at low level,
Corresponding to 0V) or high side transistor M2 and M4 be turned on the stage of (PHX and PHY at high level, correspond to Vin), electricity
Flow value that is constant and being very little.These values are indicated with Istop.
On the contrary, i.e. node PHX corresponds to Vin (PHX=Vin) simultaneously in high level in the case where diagonal transistor is connected
And node PHY corresponds to 0V (PHY=0V) (i.e. when transistor M2 is connected with M3) or node PHY in high electricity in low level
It is flat, correspond to Vin (PHY=Vin) and node PHX is in low level, corresponds to 0V (PHX=0V) (i.e. as transistor M3 and M1
When connection), electric current one of linearly increasing and in primary side switch M5 or M6 in switch M5 and the M6 closure of primary side is disconnected
Sinusoidal waveform is presented due to the resonance of network Lres-Cres when opening.
It should be noted that the value of translation time Tshift is arranged bigger, the absolute value for stopping electric current Istop is bigger.
In this analysis, in addition it should be considered that pairs of MOS transistor M1-M2 and M3-M4 must never connect simultaneously
Passing to prevents from establishing direct circuit paths between Vin and ground connection, so as to cause the destruction to MOS transistor itself.
It in other words, must useful dead time (DEAD in a half-bridge (top is to M1-M2 or lower part to M3-M4)
TIME) the time indicated, between the disconnection of high-pressure side power transistor and the connection of low side power transistor in the past, instead
?.
During period DEAD TIME, the secondary resonance of previously finding resonance is generated, the drain electrode of MOS transistor is related to
Parasitic capacitance Coss and inductor Lres between source terminal: this aspect indicates in Fig. 3.
Particularly, the high side transistor M2 of upper half-bridge is driven by signal PWMX, and low side transistor M1 is by no
Signal PWMX_neg is determined to drive.Equally, the high side transistor M4 of lower half-bridge is driven by signal PWMY, and low-pressure side is brilliant
Body pipe M3 is driven by negative acknowledge character (NAK) PWMY_neg.
The parasitic capacitance Coss_HB of half-bridge is twice of the parasitic capacitance of each individual MOS transistor, i.e. Coss_HB
=2Coss_MOS.
This resonance has the characteristic time Tres_oss depending on inductance Lres and capacitor Coss, has and depends on
The time Tres of resonant network Lres-Cres different values.
Particularly, dead time DEAD TIME can be calculated according to the parasitic capacitance of half-bridge:
At this point, considering transition of the voltage from low level (0V) to high level (Vin) at such as node PHX.It is special
Not, converter is in low side transistor M1 disconnection and the high side transistor M2 after the time equal to DEAD TIME
In the case where connection.
In this case, the resonance of network Lres-Coss makes due to flowing before the disconnection of low side transistor M1
The energy crossing electric current Istop therein and being stored in inductor Lres can be passed in capacitor Coss, so as to cause section
Voltage on point PHX can increase before high side transistor M2 connection.
This energy stored in inductor Lres is all in the time of a quarter as characteristic time Tres_oss
Inside it is delivered to capacitor Coss.
If dead time DEAD TIME is set to less than a quarter (the DEAD TIME of characteristic time Tres_oss
< 1/4Tres_oss), then only between inductor Lres and capacitor Coss positive energy exchange a part.
Therefore, in these situations (DEAD TIME < 1/4Tres_oss), node PHX at the end of period DEAD TIME
On voltage value achieved due to entire energy exchange rather than maximum value possible, but will depend on when resonance starts
It is stored in the lower value of the initial value of the energy in inductor Lres.
As previously mentioned, the above primary power value depends on the intensity of electric current Istop and therefore actually depends on
In the length of fixed translation time Tshift.In fact, translation time Tshift is longer according to what is be already mentioned above before, electricity
The value for flowing Istop is bigger.
Therefore, the behavior of the value based on translation time Tshift, converter can be there are three different situations.
A) the first situation (illustrating in Fig. 4), wherein time Tshift is short.Knot of the node PHX in dead time DEAD TIME
The voltage that beam reaches is less than supply voltage Vin, and the curve of PHX, as represented by Fig. 4, interior joint PHX is in dead zone
In closed high side transistor M2, moment reaches voltage Vin at the end of time DEAD TIME.Due to symmetry, this line
When to also appear in phase decelerating transition of the PHX from Vin to 0V, wherein high side transistor M2 is disconnected first, and in dead time
Low side transistor M1 is connected after DEAD TIME.
B) the second situation is indicated in Fig. 5, wherein time Tshift is very long.Node PHX is dead time DEAD TIME's
At the end of the voltage that reaches be higher than voltage Vin, but since the diode of high side transistor M2 enters conducting and
It is clamped at lower value, this value is higher than supply voltage Vin approximation 0.7V until high side transistor M2 itself is connected, this will
Voltage brings back to downwards value Vin.In complementary transition, the diode of voltage that node PHX reaches due to low side transistor M1
- 0.7V is clamped at into the fact that conducting.
C) last third situation indicates that wherein time Tshift accurately has value appropriate in Fig. 6, so that dead
The end of area time DEAD TIME, the voltage that node PHX reaches just are equal to voltage Vin.As this condition as a result, brilliant
There is no diode to enter conducting in body pipe, and in the range of the dram-source voltage of transistor is zero, MOS transistor
In the case that connection appears in perfect ZVS (zero voltage switch), and flowed in the MOS transistor of primary side in the connection stage
Dynamic electric current is a part of Istop and therefore in very small range, and the connection of MOS transistor appears in ZCS (zero current
Switch) in the case where.
Third situation c) indicates the optimal cases for minimizing the loss due to caused by switch and therefore causes efficiency
Improvement.
The potential idea of solution described herein is: reaching the item for the third situation c) for describing and illustrating in Fig. 6
Part switchs to realize under the conditions of ZVS and quasi- ZCS.In order to obtain this as a result, can be according to following instruction come more than being arranged
The parameter of description.
Particularly, the value of the time DEAD TIME and Tshift of following rule is abided by selection:
DEAD TIME < 1/4Tres_oss_min, wherein Tres_oss_min is in view of component Coss and Lres
The minimum possible value of secondary resonance in the case where extension；And
Tshift > > Tres_max, wherein Tres_max is off line the case where considering the process spread of both parts
The maximum possible harmonic period of the main resonance of network Lres-Cres.
By above-mentioned setting (Tshift>>Tres_max and DEAD TIME<1/4Tres_oss_min), become
In the case that parallel operation is initially in similar to illustrating in Fig. 5, but by monitoring the low of the voltage signal measured at node PHX
To the overvoltage or under-voltage when high or high to Low transition (referring to Fig. 7 a and 7b), it is possible to be subtracted using this information by circulation
The value of small time Tshift, until the equilibrium condition illustrated in Fig. 6 is actually satisfied.
Particularly, the reason of the analog circuit required for simplifying, it is more convenient that (it indicates section to monitoring signals PHX
Voltage on point PHX) failing edge (FE) at the end of under-voltage and by circulation reduce time Tshift until reaching ZVS
With quasi- ZCS condition.
In this description, situation mentioned above will be analyzed, but is also possible to realize for analyzing signal PHASE certainly
The circuit system appropriate of the rising edge (RE) of (it indicates the voltage on node PHASE), to eliminate higher than voltage Vin's
Overvoltage.Therefore, even if the first situation is described below, however two modifications of protection are intended to.
Particularly, if Tshift_nom is the time rating of initial setting up, in each circulation of PWM, monitoring signals
The under-voltage of PHASE, and time Tshift is reduced to the very small amount for being referred to as δ tshift, until reaching value Tshift_
Targ, i.e. optimum value, so that reaching ZVS and quasi- ZCS condition.
In the following, will be described as obtaining this condition and the mechanism implemented.
Adaptive ZVS module based on the content previously told about is following module: it passes through in high-pressure side power crystal
Monitoring indicates that the under-voltage of the signal of the voltage on node PHX to generate the reduction of time Tshift by circulation after pipe M2 is disconnected
To realize quasi- ZCS and ZVS condition, wherein the diode of the MOS transistor in full-bridge M1-M2-M3-M4 does not enter into conducting simultaneously
And simultaneously MOS transistor turn on the substantially dram-source voltage of 0V in the case where occur.
Diagram is for controlling the pairs of MOS crystal to form the full-bridge of primary side by means of driver appropriate in Fig. 8
The low voltage logic signal PWMX and PWMY and corresponding signal PHASE, PHX and PHY of pipe M1-M2 and M3-M4, are arrived in 0V
Variation is between Vin to reach previously described equilibrium condition, wherein not forming under-voltage during switch.
Particularly, the operating point that quasi- ZCS and ZVS condition wherein has not yet been reached is indicated in Fig. 8.
In view of the signal indicated in Fig. 8, idea is, by signal PWMY from by time rating Tshift_nom (as previously
It is arranged with referring to) fixed its rated value PWMY_nom (indicated by the solid line) is rigidly transitioned into value Tshift_targ and (uses dotted line
Indicate), it is to reach (to use for eliminating under-voltage peak value (being surrounded with solid line) and eliminating overvoltage peak value due to symmetrical
Dotted line surround) value.
In order to obtain this condition, since time Tshift_nom, in each circulation, under-voltage is monitored, and will letter
Number PWMY lead δ tshift in time, until reaching the value, so that eliminating under-voltage.At this point, being obtained by construction
ZVS and quasi- ZCS condition were obtained, and the diode of MOS transistor does not enter into conducting.
It is shown in Fig. 9 in each circulation so that calculated value δ tshift and phase (is represented by dashed line) in reconstruction signal PWMY
For the advanced drive module of rated signal (indicated by the solid line).
The module illustrated in Fig. 9 receives signal PHX in input.This signal is filtered initially through clamp circuit 10,
In the range of Vin and therefore PHX also can achieve very high value (such as 76V), clamp circuit 10 removes its noise simultaneously
And by its clamper between the voltage value that can be used by down stream low pressure circuit.
Then, the quick comparator 12 with high-gain and low offset supplies the crosspoint about signal PHX and 0V level
Information.This quick design of comparator 12 has non-equilibrium input stage to have slightly positive thresholding, will compensate their own
Delay and its statistics offset, even if these values are very low.
Information (on the crosspoint of signal PHX and 0 level) at output from comparator 12 is in input together with block
14 output is sent to AND logic gate 16, and supply has already appeared the information of the event of the failing edge of signal PWMX.
Therefore, under these conditions, there are under-voltages in the desired region of signal PHX.Under-voltage illustrates the fact that
Must by signal PWMY advance value δ tshift, the signal will correspond to when starting PWMY_nom and by circulation will by when
Between on made it possible to meet the signal PWMY_targ of previously mentioned quasi- ZCS and ZVS condition until reaching in advance.
For generation time δ tshift, the output of AND logic gate 16 is sent to the input of digital block 18, generates not
With two time windows of duration.
As long as the output of AND gate 16 switches to value " 1 " from value " 0 ", first window T1 is begun to, and persistent switch IT1
The time t1 of closure.
- the second window T2 generation time t2 < < t1, switch IT2 is closed during t2.
In the case where under-voltage is not presented in signal PHX, switch T1 is not closed, and in the decline relative to signal PWMX
After the fixed delay of (FE), switch IT2 closing time t2 again.
Later, in each circulation for the signal PWM for wherein intercepting under-voltage, by being greater than filling in the previous cycle
The electric current I of electric current discharges to capacitor C.If not intercepting any under-voltage, replace only by small value to electricity
Hold C charging.This mechanism makes it possible to obtain the amphicheirality of done correction.
In the starting of circuit, capacitor C is precharged to some thresholding identified with Vstart, this thresholding is in circuit
It needs also to be used in the case where resetting suddenly during operation
The variation of thresholding Vth_int during the circulation for intercepting under-voltage is shown in Figure 10.In step (n-1), variation
V1 is, then in step (n), to increase the variation V2 generated due to δ due to under-voltage, finally obtains new thresholding Vth_
int(n+1)。
In the case where not having under-voltage on signal PHASE, there is no variation V1, and there is only the thresholdings due to caused by δ
Increase V2.
In each circulation of signal PWM, comparator COMPrise 22 is by the thresholding Vth_ at the output from buffer 20
Int is compared with the slope 22a with constant-slope, and slope 22a is since the rising edge (RE) of signal PWMX, and in signal
It is reset at the failing edge (FE) of PWMX.
When thresholding intersects with slope, the output OUT_RISE of comparator COMPrise 22 undergoes transition: this condition exists
Occur after the delay of rising edge (RE) relative to the signal PWMX identified by module 22b, depends at this time by thresholding
The value that the initial value and its slope on Vth_int and slope reach.
Equally, for the thresholding Vth_int at each circulation also compared with slope, the slope is same with previous Slope Facies but exists
Start and replace to be reset at the rising edge (RE) of signal PWMX at the time of failing edge (FE) of signal PWMX: pass through
This of comparator COMPfall24 realization is relatively made so that exporting OUT_FALL after the delay for being equal to previous delay
It is switched to " 0 " from " 1 ", but the delay applies since the failing edge (FE) of signal PWMX.
Signal OUT_RISE and OUT_FALL is delivered to logic module 26, logic mould together with signal PWMX and PWMY_nom
Function described in the execution hereafter of block 26.
After the rising edge (RE) of signal PWMX, PWMY_OUT is output it from " 0 " and is switched to " 1 ", to execute
Logic OR between PWMY_nom and OUT_RISE；
After the failing edge (FE) of signal PWMX, PWMY_OUT is output it from " 1 " and is switched to " 0 ", to execute
Logic OR between PWMY_nom and OUT_FALL.
Therefore, it is necessary to the initial value appropriate on initial threshold Vstart appropriate and slope is selected with accurate mode
And slope, so that event OUT_RISE and OUT_FALL are respectively relative to the upper of signal PWMX when the operation of system starts
It rises along (RE) and occurs about after the delay of the failing edge of signal PWMX (FE), wherein this delay is greater than in application level
It is intended to the maximum rated time Tshift_nom of covering.
With reference to Figure 11, in this way, the evolution of converter is obtained, so that when starting, the signal of ZVS logic module
PWMY_OUT is consistent with PWMY_nom, but the mode of the value due to selection time Tshift_nom, will generate on node PHX
Under-voltage SM1, in each circulation, thresholding Vth_int will reduce and some point signal PWMY_nom rising edge (RE)
To occur event OUT_RISE and OUT_FALL respectively before with failing edge (FE), this causes advanced relative to signal PWMY_nom
Signal PWMY_OUT (referring to Figure 12).
By using signal PWMY_OUT, non-signal PWMY_nom is as the driver for switch mos transistor
Control signal, it is obvious that signal PWMY_OUT is relative to the advanced for the reason of explain before of signal PWMY_nom
Determine the reduction of under-voltage and overvoltage peak value (referring to the comparison between Figure 11 and Figure 12).
However, this will continue growing circulation until not re-forming under-voltage peak value wherein in advance.Under this condition, door
Limit Vth_int only increases small value δ, and no longer reduces, and therefore in subsequent cycle, signal PWMY_OUT will be slightly delayed,
And it is no longer advanced.
This will continue, the under-voltage of the very little until obtaining signal PHX, as shown in figure 13.
In this regard, situation inverts again, and signal PWMY_OUT will be advanced again.In fact, being up to balance strip
Part, wherein signal PWMY_OUT translates (referring to Figure 13) around the value Tshift_target for ensuring ZVS and quasi- ZCS condition,
(these parameters are the switches for discharging capacitor C and charging to the analog parameter of drive module of the middle shake depending on converter
Closure the value of time t1 and t2, the value of capacitor C itself, be charged and discharged the value of electric current I, the slope on slope, comparator
Delay and offset of COMPrise and COMPfall etc.), and wherein the under-voltage under the conditions of this according to shake in zero condition
(so that the diode in transistor does not enter into conducting) is vibrated between insignificant under-voltage condition.
It is therefore important that calibrating all these parameters to obtain suitable small shake.
Certainly, without departing from the principle of the present invention, the details of construction and embodiment can be about herein only
Content as example description and explanation greatly changes, without therefore deviateing model of the invention defined in appended claims
It encloses.
Claims (19)
1. a kind of method for driving controlled resonant converter, the controlled resonant converter include:
Primary switching circuit at least has armature winding and is configured for driving the primary full-bridge switch of the armature winding
Grade (M1, M2, M3, M4) and the resonant inductor (Lres) with the primary windings connected in series,
There is secondary resonant circuits the secondary windings for being magnetically coupled to the armature winding and parallel connection to be electrically connected to the secondary
The resonant capacitor (Cres) of winding,
Secondary commutation grade, parallel connection are electrically connected to the resonant capacitor (Cres), and
Drive module is configured for:
The section indicated between the switch of upper switches half-bridge (M1, M2) or lower switches half-bridge (M3, M4) is received in input
The signal (PHX, PHY) of the voltage measured at point,
It is indicating to survey at the node between the upper switches half-bridge (M1, M2) or the switch of lower switches half-bridge (M3, M4)
The presence of measurement negative voltage in the signal (PHX, PHY) of the voltage of amount,
At each circulation, will be used for control will next switch cycles activate the lower switches half-bridge (M3, M4) or on
Translation time (Tshift) in advance of the control signal (PWMY_OUT, PWMX_OUT) of the switch of portion's switch half-bridge (M1, M2), it is described
Translate time (Tshift) and in each circulation reduce (δ tshift), until satisfaction expression the upper switches half-bridge (M1,
M2 it is not deposited in the signal (PHX, PHY) of the voltage) or at the node between the switch of lower switches half-bridge (M3, M4) measured
In the condition of negative voltage.
2. according to the method described in claim 1, wherein meeting in expression in the upper switches half-bridge (M1, M2) or lower part
Negative voltage is not present in the signal (PHX, PHY) of the voltage measured at node between the switch of switch half-bridge (M3, M4)
Condition circulation after circulation in, will be used to control the lower switches half-bridge (M3, M4) or upper switches half-bridge (M1,
M2 the control signal (PWMY_OUT, PWMX_OUT) of switch) postpones small amount (δ), is indicating on described until detecting
The signal of the voltage measured at node between the switch of portion's switch half-bridge (M1, M2) or lower switches half-bridge (M3, M4)
There are new negative voltages in (PHX, PHY).
3. according to claim 1 or method as claimed in claim 2, wherein the translation time is initially selected as being longer than by institute
State the longest harmonic period (Tres_max) for the network that resonant inductor and the resonant capacitor (Lres, Cres) are formed.
4. according to claim or method as claimed in claim 2, wherein obtaining the primary full-bridge switch via transistor
The high side switch (M2, M4) and low-side switch (M1, M3) of grade.
5. according to the method described in claim 4, wherein the transistor is MOSFET.
6. according to the method described in claim 5, wherein the upper switches half-bridge (M1, M2) or lower switches half-bridge (M3,
M4 in), between the disconnection of the high side switch (M2, M4) and the connection of corresponding low-side switch (M1, M3), and it is on the contrary
, dead time (DEAD TIME) disappearance is to prevent building for the Direct Current path between ground connection and supply voltage (Vin)
It is vertical,
Wherein during the dead time (DEAD TIME), secondary resonance is generated, the secondary resonance is related to described
Parasitic capacitance (Coss) and the resonant inductor between the drain electrode and source terminal of MOSFET (M1, M2, M3, M4)
(Lres),
And wherein the method, which is imagined, configures the drive module to select:
The dead time (DEAD TIME) <1/4Tres_oss_min, wherein Tres_oss_min is to be related to the parasitic electricity
Hold the minimum value of the secondary resonance of (Coss) and the resonant inductor (Lres)；And
Translation time (Tshift) > > Tres_max, wherein Tres_max is by the resonant inductor and the resonance
The longest harmonic period of the main resonance for the network that capacitor is formed.
7. a kind of controlled resonant converter, comprising:
Primary switching circuit at least has armature winding and is configured for driving the primary full-bridge switch of the armature winding
Grade (M1, M2, M3, M4) and the resonant inductor (Lres) with the primary windings connected in series,
There is secondary resonant circuits the secondary windings for being magnetically coupled to the armature winding and parallel connection to be electrically connected to the secondary
The resonant capacitor (Cres) of winding,
Secondary commutation grade, parallel connection are electrically connected to the resonant capacitor (Cres), and
Drive module, be configured for controlling independently of one another upper switches half-bridge (M1, M2) and lower switches half-bridge (M3,
M4) to realize according to the method for claim 1.
8. converter according to claim 7, wherein the upper switches half-bridge (M1, M2) and the lower switches half-bridge
(M3, M4) is obtained via MOSFET.
9. a kind of computer readable storage medium, the computer-readable recording medium storage has computer program, the calculating
Machine program executes the calculating equipment according to claim 1 to any one of 6 in the processor execution by calculating equipment
The method.
10. a kind of controlled resonant converter, comprising:
Primary switching circuit at least has armature winding and is configured for driving the primary full-bridge switch grade of the armature winding
And the resonant inductor with the primary windings connected in series, the full-bridge switch grade include upper switches half-bridge and lower switches half
Bridge；
Secondary resonant circuits, have the secondary windings for being magnetically coupled to the armature winding and parallel connection be electrically connected to it is described it is secondary around
The resonant capacitor of group；
Secondary commutation grade, parallel connection are electrically connected to the resonant capacitor；And
Drive module is configured for:
Receive the voltage for indicating to measure at the node between the switch of the upper switches half-bridge or the lower switches half-bridge
Signal,
In the voltage for indicating to measure at the node between the switch of the upper switches half-bridge or the lower switches half-bridge
The presence of negative voltage is measured in the signal,
It is in application to each switch cycles of the control signal of the switch of the lower switches half-bridge or the upper switches half-bridge
Place, will be used for control will next switch cycles activate the lower switches half-bridge or upper switches half-bridge switch described in
Control signal translates the time in advance, and the translation time reduces in each circulation, is indicating until meeting in the upper switches
The condition of negative voltage is not present in the signal of the voltage measured at node between the switch of half-bridge or lower switches half-bridge.
11. controlled resonant converter according to claim 10, wherein meet indicate the upper switches half-bridge or under
The switch of condition in the signal of the voltage measured at node between the switch of portion's switch half-bridge there is no negative voltage follows
In switch cycles after ring, the control signal for being used to control the switch of the lower switches half-bridge or upper switches half-bridge is prolonged
Amount small late is indicating to survey at the node between the upper switches half-bridge or the switch of lower switches half-bridge until detecting
There are new negative voltages in the signal of the voltage of amount.
12. controlled resonant converter according to claim 10, wherein the translation time is initially selected as being longer than by described
The longest harmonic period of the main resonance for the network that resonant inductor and the resonant capacitor are formed.
13. controlled resonant converter according to claim 10, wherein the upper switches half-bridge and the lower switches half-bridge
Each of high side switch and each of the upper switches half-bridge and the lower switches half-bridge low-pressure side
Switch is transistor.
14. controlled resonant converter according to claim 13, wherein the transistor is MOSFET.
15. controlled resonant converter according to claim 14,
Wherein in the upper switches half-bridge or lower switches half-bridge, in the disconnection and corresponding low-pressure side of the high side switch
Between the connection of switch, and vice versa, and dead time DEAD TIME disappears to prevent between ground connection and supply voltage
The foundation in Direct Current path,
Wherein during the dead time, secondary resonance is generated, the secondary resonance is related to the leakage in the power MOSFET
Parasitic capacitance and the resonant inductor between pole and source terminal, and
Wherein the drive module is configured as selecting:
The dead time DEAD TIME <1/4Tres_oss_min, wherein Tres_oss_min be related to the parasitic capacitance and
The minimum value of the secondary resonance of the resonant inductor；And
The translation time is represented as Tshift, and Tshift > > Tres_max, wherein Tres_max is by the resonant inductance
The longest harmonic period of the main resonance for the network that device and the resonant capacitor are formed.
16. a kind of method for controlling controlled resonant converter, comprising:
Receiving phase signal, the phase signal indicate the upper switches half-bridge circuit and lower switches half of the controlled resonant converter
The voltage in one phase node in bridge circuit, in the upper switches half-bridge circuit and the lower switches half-bridge circuit
Each include high side switch and low-side switch；
The high side switch is provided for each of the upper switches half-bridge circuit and the lower switches half-bridge circuit
Shutdown and the low-side switch connection between dead time；
The low-side switch is provided for each of the upper switches half-bridge circuit and the lower switches half-bridge circuit
Shutdown and the high side switch connection between dead time；
During the dead time, under-voltage or overvoltage, the under-voltage or overvoltage are detected in the phase signal
Derived from secondary resonance, the secondary resonance due to the switch of the controlled resonant converter parasitic capacitance and resonance inductance component and send out
It is raw；
Time-shifting is provided between first control signal and second control signal, the first control signal is applied to described
One switch in upper switches half-bridge circuit and the lower switches half-bridge circuit, the second control signal are applied to
Another switch in the upper switches half-bridge circuit and the lower switches half-bridge circuit, the time-shifting have just
Beginning nominal value；And
Reduce the value of the time-shifting since the initial nominal values, and in the first control signal and described second
Described value is reduced by increment value during controlling each circulation of signal, until the under-voltage or mistake in the phase signal
Voltage is zero.
17. according to the method for claim 16, wherein providing the dead time includes providing to be less than Tres_oss_min
1/4 dead time, wherein Tres_oss_min is since the parasitic capacitance of the switch and the resonant inductance component are led
The minimum value of the secondary resonance of cause.
18. according to the method for claim 16, wherein providing the time-shifting includes providing to have than longest resonance week
The time-shifting of phase long initial nominal values, the longest harmonic period by the controlled resonant converter the resonant inductance
Component and resonance capacitive element determine.
19. according to the method for claim 16, wherein detecting under-voltage or overvoltage in the phase signal includes detection
The under-voltage of the failing edge of the phase signal in the phase node of the upper switches half-bridge, the under-voltage with
It is generated during the associated dead time of the first control signal for being applied to the upper switches half-bridge circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT102015000057306 | 2015-10-01 | ||
| ITUB2015A004121A ITUB20154121A1 (en) | 2015-10-01 | 2015-10-01 | PROCEDURE FOR THE DRIVING OF A RESONANT CONVERTER, ITS RELATIVE DEVICE AND IT PRODUCT |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106560989A CN106560989A (en) | 2017-04-12 |
| CN106560989B true CN106560989B (en) | 2019-07-16 |
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