CN106560798B - Memory access method and device and computer system - Google Patents
Memory access method and device and computer system Download PDFInfo
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- CN106560798B CN106560798B CN201510639399.2A CN201510639399A CN106560798B CN 106560798 B CN106560798 B CN 106560798B CN 201510639399 A CN201510639399 A CN 201510639399A CN 106560798 B CN106560798 B CN 106560798B
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Abstract
The embodiment of the invention provides a memory access method, a memory access device and a computer system, wherein the method comprises the following steps: acquiring a virtual address included in a first memory access request, and inquiring a physical address corresponding to the virtual address from a page table cache TLB; acquiring a first flag bit and a second flag bit preset for a physical page corresponding to the physical address in a page table entry PTE of the TLB, wherein the first flag bit is used for indicating whether a Cache of a processor includes the physical page, and the second flag bit is used for indicating the position of the physical page in a memory; and if the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, reading the physical page from the memory according to the second flag bit. The embodiment of the invention can improve the memory access efficiency and the performance of the processor.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a memory access method, a memory access device and a computer system.
Background
The Cache (english: Cache) is located between a Central Processing Unit (CPU) and a Memory, and mainly aims to solve the problem that the operation speed of the CPU is not matched with the read-write speed of the Memory. At present, a CPU generally adopts a three-level Cache structure, including a first-level Cache L1 Cache, a second-level Cache L2 Cache and a third-level Cache L3 Cache. Based on the above-mentioned multi-level Cache, the specific process of the CPU executing the memory data read operation in the prior art is as follows: when a Core of the CPU sends a data reading request, data is searched layer by layer, namely data is searched according to the sequence of the L1 Cache, the L2 Cache and the L3Cache, and if the data cannot be found, the data is searched in the memory until the data is found.
In the above lookup process, it is usually required to hit through multiple lookups, for example, data to be read is stored in a memory, so that data must be looked up in the memory only when the internal caches (i.e., L1 Cache, L2 Cache, and L3Cache) of the CPU are not hit, which causes a long lookup delay, resulting in a low access efficiency of the memory and affects performance of the processor.
Disclosure of Invention
The embodiment of the invention provides a memory access method, a memory access device and a computer system, which can improve the memory access efficiency and the performance of a processor.
A first aspect of an embodiment of the present invention provides a memory access method, including:
acquiring a virtual address included in a first memory access request, and inquiring a physical address corresponding to the virtual address from a page table cache TLB;
acquiring a first flag bit and a second flag bit preset for a physical page corresponding to the physical address in a page table entry PTE of the TLB, wherein the first flag bit is used for indicating whether a Cache of a processor includes the physical page, and the second flag bit is used for indicating the position of the physical page in a memory;
and if the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, reading the physical page from the memory according to the second flag bit.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the reading the physical page from the memory according to the second flag bit includes:
reading the physical page from the Cache of the memory according to the physical address;
and if the Cache of the memory does not comprise the physical page, reading the physical page from the memory according to the second zone bit.
With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the method further includes:
and if the indication state of the first flag bit is that the Cache of the processor comprises the physical page, reading the physical page from the Cache of the processor according to the physical address.
With reference to the first aspect or the first possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, before the obtaining the virtual address included in the first memory access request, the method further includes:
acquiring the virtual address included in a second memory access request, and inquiring the physical address corresponding to the virtual address from the TLB;
setting a first flag bit in the PTE aiming at the physical page corresponding to the physical address, and initializing the indication state of the first flag bit to the state that the physical page is not included in the Cache of the processor;
reading the physical page from the memory according to the physical address, copying the physical page from the memory to a Cache of the processor, and recording identification information of the processor in the physical page included by the Cache of the memory;
and modifying the indication state of the first flag bit to the state that the Cache of the processor comprises the physical page, and setting a second flag bit in the PTE aiming at the physical page, wherein the second flag bit is used for indicating the position of the physical page in the memory.
With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the method further includes:
when the TLB is replaced or the Cache of the memory is replaced, modifying the indication state of the first flag bit in the PTE to the state that the Cache of the processor does not include the physical page;
removing the identification information of the processor from the physical page included in the Cache of the memory according to the second zone bit;
and clearing the indication information of the second flag bit in the PTE.
With reference to the first aspect, in a fifth possible implementation manner of the first aspect, the memory includes Stacked dynamic random access memory Stacked DRAMs.
A second aspect of the present invention provides a memory access device, including:
the query module is used for acquiring a virtual address included in the first memory access request and querying a physical address corresponding to the virtual address from the page table cache TLB;
an obtaining module, configured to obtain a first flag bit and a second flag bit preset for a physical page corresponding to the physical address in a page table entry PTE of the TLB, where the first flag bit is used to indicate whether a Cache of a processor includes the physical page, and the second flag bit is used to indicate a position of the physical page in a memory;
and the reading module is used for reading the physical page from the memory according to the second flag bit when the indication state of the first flag bit is that the physical page is not included in the Cache of the processor.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the specific manner in which the reading module reads the physical page from the memory according to the second flag bit is as follows:
reading the physical page from the Cache of the memory according to the physical address;
and if the Cache of the memory does not comprise the physical page, reading the physical page from the memory according to the second zone bit.
With reference to the second aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the reading module is further configured to read the physical page from a Cache of the processor according to the physical address when the indication state of the first flag bit is that the physical page is included in the Cache of the processor.
With reference to the second aspect or the first possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the query module is further configured to, before obtaining a virtual address included in the first memory access request, obtain the virtual address included in the second memory access request, and query the TLB for the physical address corresponding to the virtual address;
wherein the apparatus further comprises:
a setting module, configured to set a first flag bit in the PTE for the physical page corresponding to the physical address, and initialize an indication state of the first flag bit to a state that the physical page is not included in a Cache of the processor;
the copying module is used for reading the physical page from the memory according to the physical address and copying the physical page from the memory to a Cache of the processor;
the recording module is used for recording the identification information of the processor in the physical page included by the Cache of the memory;
the setting module is further configured to modify an indication state of the first flag bit to indicate that the Cache of the processor includes the physical page, and set a second flag bit in the PTE for the physical page, where the second flag bit is used to indicate a position of the physical page in the memory.
With reference to the third possible implementation manner of the second aspect, in a fourth possible implementation manner of the second aspect, the setting module is further configured to modify, when the TLB is replaced or the Cache of the memory is replaced, an indication state of the first flag bit in the PTE to be that the Cache of the processor does not include the physical page;
wherein the apparatus further comprises:
and the clearing module is used for clearing the identification information of the processor from the physical page included by the Cache of the memory according to the second flag bit and clearing the indication information of the second flag bit in the PTE.
With reference to the second aspect, in a fifth possible implementation manner of the second aspect, the memory includes Stacked dynamic random access memory Stacked DRAMs.
A third aspect of an embodiment of the present invention provides a computer system, including a memory and any one of the above-described apparatuses.
The embodiment of the invention can acquire the virtual address included in the first memory access request, query the physical address corresponding to the virtual address from the page table Cache TLB, and acquire the first flag bit and the second flag bit preset for the physical page corresponding to the physical address in the page table entry PTE of the TLB, where the first flag bit is used to indicate whether the Cache of the processor includes the physical page, and the second flag bit is used to indicate the position of the physical page in the memory, and if the indication state of the first flag bit is that the Cache of the processor does not include the physical page, the physical page is read from the memory according to the second flag bit, so that the memory access efficiency can be improved, and the performance of the processor can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a computer system according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a memory access method according to a first embodiment of the present invention;
fig. 3 is a schematic flowchart of a memory access method according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a memory access device according to a first embodiment of the present invention;
fig. 5 is a schematic structural diagram of a memory access device according to a second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a memory access method, a memory access device and a computer system, which can improve the memory access efficiency and the performance of a processor. The following are detailed below.
The execution main body of the memory access method provided by the invention can be a CPU Core in a CPU containing a Multi-level Cache, and can also be a hardware device with a data read/write function in the CPU containing the Multi-level Cache.
Fig. 1 is a schematic structural diagram of a computer system according to an embodiment of the present invention. The computer system comprises a CPU Core, a CPU Cache and a Memory (English). Taking a four-core CPU as an example, each CPU has three levels of caches, where the three levels of caches include a first Level Cache (english: Level 1Cache, abbreviation: L1 Cache), a second Level Cache (english: Level 2Cache, abbreviation: L2 Cache), and a third Level Cache (english: Level 3Cache, abbreviation: L3Cache), where the L1 Cache includes an Instruction Cache I-Cache (english: Instruction-Cache), a Data Cache D-Cache (english: Data-Cache), and the priority levels when the CPU accesses the third Level Cache are: l1 Cache > L2 Cache > L3 Cache.
For a computer system with N-level caches, the level of the first-level Cache is the highest, the level of the N-level Cache is the lowest, and the Cache level from the first-level Cache to the N-level Cache is decreased progressively.
Further, the computer system may further include a page table cache (TLB), and the TLB specifically includes: the Instruction page table caches an I-TLB (Instruction-TLB), and the Data page table caches a D-TLB (Data-TLB).
Specifically, an L1 Cache adopts a high-speed small-capacity Cache, an L2 Cache adopts a Cache with medium speed and large capacity, an L3Cache adopts a low-speed large-capacity Cache, an L1 Cache and an L2 Cache are private caches of each CPU Core, and an L3Cache is a shared Cache of a plurality of CPU cores. The private cache is private to one CPU Core, and the shared cache is shared by a plurality of CPU cores.
Referring to fig. 2, a first embodiment of a memory access method according to the present invention is shown in a flowchart. The memory access method described in this embodiment includes the following steps:
s101, obtaining a virtual address included in the first memory access request, and inquiring a physical address corresponding to the virtual address from a page table cache TLB.
The modern operating system provides an abstraction of Memory management, that is, a Virtual Memory (english: Virtual Memory) technology, a program runs in a Virtual Address Space (english: Virtual Address Space), a process uses an Address in the Virtual Memory, when the process needs to acquire data corresponding to a certain Physical Address (PA), the process firstly sends out a Virtual Address, and the operating system assists a Memory management Unit (english: Memory Manager Unit, abbreviation: MMU) to map the Virtual Address to obtain a Physical Address. The physical address is the address placed on the addressing bus. And if the address is read, the circuit puts the data in the physical memory of the corresponding address into the data bus for transmission according to the value of each bit of the address. If it is a write, the circuit puts the contents of the data bus into the physical memory of the corresponding address based on the value of each bit of the address. Physical memory is addressed in units of 8-bit bytes (English).
Among them, most of the current systems using the virtual memory use a mechanism called paging, that is, the virtual address space is divided into units called pages, and the corresponding physical address space is also divided into units called Page frames, the sizes of the pages and the Page frames must be the same, the mapping of the virtual address and the physical address is performed in units of pages, the mapping relationship of the virtual address and the physical address is stored in a Page Table, the Page Table is generally stored in the memory, wherein the part of the Page Table which is frequently used recently is stored in the TLB of the CPU Core, the TLB is a small MMU, the cache of the virtual addressing is used for improving the translation speed of the virtual address to the physical address, wherein each line stores a block composed of a single Page Table Entry (abbreviated as PTE), one PTE includes a mapping relationship between a virtual address and a physical address, and if there is no TLB, each time data is read, the memory needs to be accessed, that is, a page table in the memory is queried to obtain a physical address corresponding to the virtual address, and then the data (that is, a physical page corresponding to the physical address) is read from the memory according to the physical address.
The working principle of the TLB is as follows: when the CPU makes a read request for data, the CPU searches the TLB according to the first 20 bits of the virtual address, the TLB stores the mapping relation between the first 20 bits of the virtual address and the page frame number, if the virtual address is matched, the page frame number (the page frame number can be understood as a page table item) can be quickly found, and the final physical address is obtained through the offset combination of the page frame number and the 12 bits behind the virtual address. If the virtual address is not matched in the TLB, the TLB missing occurs, a page table entry needs to be inquired in a page table, and if the virtual address is not matched in the page table, the content to be read is not in the memory, and the content needs to be read in a disk. In the paging mechanism, the data in the TLB and the data association of the page table are not maintained by the processor, but by the operating system OS, and the flushing of the TLB is accomplished by loading the CR3 register in the processor. If the MMU finds a miss in the TLB, it replaces a PTE in the TLB with the found page table entry after a conventional page table walk.
The physical pages are real memory, corresponding to virtual memory, and for a 32-bit CPU, the size of each physical page is 4 KB.
Specifically, when an execution mechanism (e.g., a CPU Core) of the CPU receives a first memory access request sent by a program for reading data, the CPU Core first obtains a virtual address included therein, and then searches a page table matching the virtual address from the TLB, if a required page table is stored in the TLB, the page table is called a TLB Hit (english: TLB Hit), and then the CPU Core obtains a physical address included in the required page table in the TLB.
Further, if the CPU Core does not find a page table matching the virtual address in the TLB, a TLB Miss (English: TLB Miss) occurs, and the CPU Core looks up the page table in the memory to obtain the physical address corresponding to the virtual address.
Note that the CPU Core may include a TLB, but the TLB is not limited to be provided in the CPU Core.
S102, a first flag bit and a second flag bit preset for a physical page corresponding to the physical address in a page table entry PTE of the TLB are acquired, the first flag bit is used for indicating whether a Cache of a processor includes the physical page, and the second flag bit is used for indicating the position of the physical page in a memory.
The processor (for example, CPU) may include a multi-level cache, the CPU cache is an intermediate medium existing for connecting the CPU and the memory more quickly, and is a temporary storage between the CPU and the memory, and the capacity of the temporary storage is much smaller than the memory, but the exchange speed is much faster than the memory, the data in the cache is a small part of the memory, but the small part is to be accessed by the CPU in a short time, and when the CPU calls a large amount of data, the memory can be avoided from being directly called from the cache, thereby accelerating the reading speed. Generally, a CPU may be divided into three levels of caches, including L1, L2, and L3 caches).
Specifically, the CPU Core may extend (1+ n) bits (english: bit) in each PTE, where 1 bit (denoted as a first flag bit) is used to indicate whether a physical page corresponding to the physical address exists in the Cache of the processor, the other n bits (denoted as second flag bits) are used to indicate a position of the physical page corresponding to the physical address in the memory, and the (1+ n) bits may be all initialized to Null or 0, that is, when the first flag bit is Null or 0, it indicates that the physical page corresponding to the physical address does not exist in the Cache of the processor, and when the first flag bit is 1, it indicates that the physical page corresponding to the physical address exists in the Cache of the processor.
Further, the CPU Core acquires the first flag bit and the second flag bit, which are set in advance for the physical page, from the PTE.
The data in the memory is written into a large matrix by using bits as a unit, each Cell is called a Cell, and the Cell can be accurately positioned to a certain Cell as long as a row and a column are specified, which is the basic principle of memory addressing, and such an array is called a Bank of the memory (in the invention, the array refers to a logic Bank)Bank), the value of N is determined according to the number N of the memory banks, and the corresponding relation is as follows: 2nN, for example, if the number N of banks is 256, then N is 8, so that 9 bits are extended in each PTE, where 1 bit is used to indicate whether the physical page corresponding to the physical address exists in the Cache of the processor, and the other 8 bits are used to indicate the location of the physical page corresponding to the physical address in the memory (i.e., Bank ID).
The memory in the invention can be a Stacked dynamic random access memory Stacked DRAM.
S103, if the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, reading the physical page from the memory according to the second flag bit.
Specifically, if the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, the CPU Core may directly read the physical page from the corresponding Bank of the memory according to the second flag bit, thereby directly skipping a link of querying the physical page according to the physical address from the Cache of the processor, eliminating a delay caused by querying in the Cache of the processor, and increasing a speed of reading the memory data.
In some possible embodiments, if the indication state of the first flag bit is that the physical page is included in the Cache of the processor, the CPU Core may read the physical page from the Cache of the processor according to the physical address, and assuming that the Cache of the processor has N levels, the CPU Core sequentially searches according to the level of the N-level Cache from high to low, and a process of searching whether an i (i is greater than or equal to 1 and less than or equal to N) level Cache hits may be: and searching a plurality of bits in the middle of the virtual address in the i-level Cache to select a group of tags (English: Tag) of Cache lines (English: Cache Line), wherein the Tag can be an upper bit of a physical address, then comparing the upper bit of the physical address obtained by the TLB with the selected group of tags, if the Tag of a certain group of Cache Line can be matched with the upper bit of the physical address, the i-level Cache is hit, and if not, the i-level Cache is not hit.
The embodiment of the invention can acquire the virtual address included in the first memory access request, query the physical address corresponding to the virtual address from the page table Cache TLB, and acquire the first flag bit and the second flag bit preset for the physical page corresponding to the physical address in the page table entry PTE of the TLB, where the first flag bit is used to indicate whether the Cache of the processor includes the physical page, and the second flag bit is used to indicate the position of the physical page in the memory, and if the indication state of the first flag bit is that the Cache of the processor does not include the physical page, the physical page is read from the memory according to the second flag bit, so that the memory access efficiency can be improved, and the performance of the processor can be improved.
Referring to fig. 3, a second embodiment of a memory access method according to the present invention is shown in a flowchart. The memory access method described in this embodiment includes the following steps:
s201, obtaining a virtual address included in the second memory access request, and querying a physical address corresponding to the virtual address from a page table cache TLB.
The modern operating system provides an abstraction of Memory management, that is, a Virtual Memory (Virtual Memory) technology, a program runs in a Virtual Address Space (Virtual Address Space), a process uses an Address in the Virtual Memory, when the process needs to acquire data corresponding to a certain physical Address, the process first sends out the Virtual Address, and the operating system assists a Memory Management Unit (MMU) to map the Virtual Address to obtain the physical Address.
Most of the current systems using virtual memory use a mechanism called paging, i.e. the virtual address space is divided into units called pages, and the corresponding physical address space is also divided into units called Page frames, the sizes of the pages and the Page frames must be the same, the mapping of the virtual address and the physical address is performed in units of pages, the mapping relationship is stored in Page tables (which are generally stored in memory), wherein the part of Page tables which are frequently used recently is stored in the TLB of the CPU Core, the TLB is a small virtual addressing cache memory which is used to improve the speed of converting the virtual address into the physical address, wherein each row stores a block composed of a single Page Table Entry (abbreviated as PTE), and a PTE contains a mapping relationship between the virtual address and the physical address, if there is no TLB, the memory needs to be accessed each time the data is read, that is, the page table in the memory is queried to obtain the physical address corresponding to the virtual address, and then the data (that is, the physical page corresponding to the physical address) is read from the memory according to the physical address.
The physical pages are real memory, corresponding to virtual memory, and for a 32-bit CPU, the size of each physical page is 4 KB.
Specifically, when an execution mechanism (e.g., CPU Core) of the CPU receives a second memory access request sent by a program for reading data, the CPU Core first obtains a virtual address included therein, and then searches a page table matching the virtual address from the TLB, if a required page table is stored in the TLB, the page table is called a TLB Hit (english: TLB Hit), and then the CPU Core obtains a physical address included in the required page table in the TLB.
Further, if the CPU Core does not find a page table matching the virtual address in the TLB, a TLB Miss (English: TLB Miss) occurs, and the CPU Core looks up the page table in the memory to obtain the physical address corresponding to the virtual address.
S202, aiming at the physical page corresponding to the physical address, setting a first flag bit in a page table entry PTE of the TLB, and initializing the indication state of the first flag bit to the state that the physical page is not included in the Cache of the processor.
The CPU Core may extend (1+ n) bits in each PTE, where 1 bit (marked as a first flag bit) is used to indicate whether a physical page corresponding to the physical address exists in a Cache of the processor, the other n bits (marked as a second flag bit) are used to indicate a position of the physical page corresponding to the physical address in the memory, the (1+ n) bits may all be initialized to Null or 0, that is, when the first flag bit is Null or 0, the physical page corresponding to the physical address is indicated not in the Cache of the processor, and when the first flag bit is 1, the physical page corresponding to the physical address is indicated in the Cache of the processor.
Further, data in the memory is written into a large matrix by using bits as a unit, each Cell is called a Cell, and can be accurately positioned to a certain Cell as long as rows and columns are specified, which is a basic principle of memory addressing, such an array is called a Bank (a logic Bank in the invention) of the memory, a value of N is specifically determined according to the number N of the memory Bank, and a corresponding relation is as follows: 2nN, for example, if the number N of banks is 256, then N is 8, so that 9 bits are extended in each PTE, where 1 bit is used to indicate whether the physical page corresponding to the physical address exists in the Cache of the processor, and the other 8 bits are used to indicate the location of the physical page corresponding to the physical address in the memory (i.e., Bank ID).
Specifically, when the CPU is reset or powered on, the (1+ n) bits may all be initialized to Null or 0, and therefore, the indication states of the first flag bits of the physical page corresponding to any one physical address at this time are all the physical pages corresponding to any one physical address that are not included in the Cache of the processor.
The memory in the invention can be a Stacked dynamic random access memory Stacked DRAM.
S203, reading the physical page from the memory according to the physical address, copying the physical page from the memory to a Cache of the processor, and recording the identification information of the processor in the physical page included by the Cache of the memory.
Specifically, since the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, the CPU Core directly reads the physical page from the memory according to the physical address, obtains the location (i.e., Bank ID) of the physical page in the memory, copies the physical page to the Cache of the processor, and records the identification information of the processor in the physical page included in the Cache of the memory, so as to indicate whether the physical page is used by multiple CPU cores or multiple processes at the same time.
The identification information of the processor may specifically be CPU IDs that are automatically generated by the CPU cores and do not overlap with each other, for example, in a quad-Core CPU (including Core 0, Core 1, Core2, and Core 3), the CPU IDs may be respectively represented as 00, 01, 10, and 11, and the specific representation mode of the CPU ID is not limited in the embodiment of the present invention.
S204, modifying the indication state of the first flag bit to be that the Cache of the processor comprises the physical page, and setting a second flag bit in the PTE aiming at the physical page, wherein the second flag bit is used for indicating the position of the physical page in the memory.
In a specific implementation, after the CPU Core copies the physical page into the Cache of the processor, the CPU Core may modify the indication state of the first flag bit to include the physical page in the Cache of the processor by setting 1 bit corresponding to the first flag bit to 1, and meanwhile, set a second flag bit (i.e., N bits) in a corresponding PTE for the physical page, where for example, if the number N of the memory banks is 64, then N is 6, that is, at this time, 6 bits represent the position of the physical page in the memory, assuming that the Bank ID of the physical page in the memory acquired by the CPUCore is 33, then the second flag bit may be 100001, and at this time, (1+6) bits extended in the PTE may be 1100001 or 1000011.
S205, the virtual address included in the first memory access request is obtained, and the physical address corresponding to the virtual address is inquired from the TLB.
S206, acquiring a first flag bit and a second flag bit which are set for a physical page corresponding to the physical address in the PTE.
S207, if the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, reading the physical page from the memory according to the second flag bit.
S208, if the indication state of the first flag bit is that the physical page is included in the Cache of the processor, reading the physical page from the Cache of the processor according to the physical address.
Specifically, when a program accesses the physical page corresponding to the physical address again, the CPU Core first obtains a first flag bit and a second flag bit set for the physical page from the PTE corresponding to the physical address, at this time, if the indication state of the first flag bit is that the physical page is included in the Cache of the processor, the CPU Core reads the physical page from the Cache of the processor according to the physical address, if 1 bit corresponding to the first flag bit is reset to Null or 0 during the period, the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, and the CPU Core reads the physical page from the memory according to the second flag bit (i.e., Bank ID), for example, the second flag bit is 100001, and the CPU Core directly reads the physical page from the Bank with Bank ID of 33 in the memory.
In some possible implementations, when the TLB is replaced or the Cache of the memory is replaced (i.e., the physical page is replaced by another physical page), the CPU Core may modify the indication state of the first flag bit in the PTE in such a way that 1 bit corresponding to the first flag bit is Null or 0, that is, the physical page is not included in the Cache of the processor, when the CPU Core determines that the processor identification information in the physical page included in the Cache of the memory also includes CPU IDs of other CPUs, informing corresponding CPU Core according to CPU ID to set 1 bit corresponding to the first flag bit and n bits corresponding to the second flag bit included in corresponding PTE in TLB stored by each to Null or 0, and meanwhile, according to the second zone bit, the identification information of the processor is cleared from the physical page included by the Cache of the memory, and finally, the indication information of the second zone bit in the PTE is cleared (namely n bits are set to Null or 0).
The embodiment of the present invention can obtain a virtual address included in a second memory access request, query a physical address corresponding to the virtual address from a page table Cache TLB, set a first flag bit in a page table entry PTE of the TLB for a physical page corresponding to the physical address, initialize an indication state of the first flag bit to a state that the physical page is not included in a Cache of a processor, further read the physical page from the memory according to the physical address, copy the physical page from the memory to the Cache of the processor, record identification information of the processor in the physical page included in the Cache of the memory, modify the indication state of the first flag bit to indicate that the Cache of the processor includes the physical page, and set a second flag bit in the PTE for the physical page, where the second flag bit is used to indicate a position of the physical page in the memory; the virtual address included in the first memory access request is acquired, the physical address corresponding to the virtual address is queried from the TLB, and a first flag bit and a second flag bit set in the PTE for a physical page corresponding to the physical address are acquired, where the second flag bit is used to indicate a position of the physical page in a memory, and if the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, the physical page is read from the memory according to the second flag bit, otherwise, the physical page is read from the Cache of the processor according to the physical address, so that the memory access efficiency can be improved, and the performance of the processor is improved.
Fig. 4 is a schematic structural diagram of a memory access device according to a first embodiment of the present invention. The memory access device described in this embodiment includes: a query module 401, an acquisition module 402 and a reading module 403, wherein:
the querying module 401 is configured to obtain a virtual address included in the first memory access request, and query a physical address corresponding to the virtual address from the page table cache TLB.
Specifically, when an execution mechanism of the CPU (e.g., a CPU Core) receives a first memory access request sent by a program for reading data, the query module 401 first obtains a virtual address included therein, and then searches the TLB for a page table matching the virtual address, if the TLB stores a required page table, it is called TLB Hit (english: TLB Hit), and then the query module 401 obtains a physical address included in the required page table in the TLB.
Further, if the query module 401 does not find a page table matching the virtual address in the TLB, a TLB Miss (english: TLB Miss) occurs, and the query module 401 queries from the page table of the memory to obtain a physical address corresponding to the virtual address.
Note that the CPU Core may include a TLB, but the TLB is not limited to be provided in the CPU Core.
An obtaining module 402, configured to obtain a first flag bit and a second flag bit preset for a physical page corresponding to the physical address in a page table entry PTE of the TLB, where the first flag bit is used to indicate whether a Cache of a processor includes the physical page, and the second flag bit is used to indicate a location of the physical page in a memory.
The processor (for example, CPU) may include a multi-level cache, the CPU cache is an intermediate medium existing for connecting the CPU and the memory more quickly, and is a temporary storage between the CPU and the memory, and the capacity of the temporary storage is much smaller than the memory, but the exchange speed is much faster than the memory, the data in the cache is a small part of the memory, but the small part is to be accessed by the CPU in a short time, and when the CPU calls a large amount of data, the memory can be avoided from being directly called from the cache, thereby accelerating the reading speed. Generally, a CPU may be divided into three levels of caches, including L1, L2, and L3 caches).
Specifically, the CPU Core may extend (1+ n) bits in each PTE, where 1 bit (denoted as a first flag bit) is used to indicate whether a physical page corresponding to the physical address exists in the Cache of the processor, the other n bits (denoted as a second flag bit) are used to indicate the position of the physical page corresponding to the physical address in the memory, and all of the (1+ n) bits may be initialized to be Null or 0, that is, when the first flag bit is Null or 0, it indicates that the physical page corresponding to the physical address does not exist in the Cache of the processor, and when the first flag bit is 1, it indicates that the physical page corresponding to the physical address exists in the Cache of the processor.
Further, the obtaining module 402 obtains the first flag bit and the second flag bit that are set in advance for the physical page from the PTE.
Data in the memory is written into a large matrix by using bits as a unit, each Cell is called a Cell, a certain Cell can be accurately positioned as long as a row and a column are specified, which is a basic principle of memory addressing, such an array is called a Bank (a logic Bank in the invention) of the memory, a value of N is specifically determined according to the number N of the memory Bank, and a corresponding relation is as follows: 2nN, e.g. the number N of banks 256, then N8, thus extending 9 bits in each PTE, which is now itThe middle 1 bit is used to indicate whether the physical page corresponding to the physical address exists in the Cache of the processor, and the other 8 bits are used to indicate the position (i.e. Bank ID) of the physical page corresponding to the physical address in the memory.
The memory in the invention can be a Stacked dynamic random access memory Stacked DRAM.
A reading module 403, configured to read the physical page from the memory according to the second flag bit when the indication state of the first flag bit is that the physical page is not included in the Cache of the processor.
Specifically, if the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, the reading module 403 may directly read the physical page from the corresponding Bank of the memory according to the second flag bit, thereby directly skipping a link of querying the physical page according to the physical address from the Cache of the processor, eliminating a delay caused by querying the Cache of the processor by the reading module 403, and improving the speed of reading the memory data.
In some possible embodiments, if the indication state of the first flag bit is that the physical page is included in the Cache of the processor, the reading module 403 may read the physical page from the Cache of the processor according to the physical address, and assuming that the Cache of the processor has N levels, the reading module 403 sequentially searches according to the level of the N levels of the Cache from high to low, and a process of searching whether an i (i is greater than or equal to 1 and less than or equal to N) level Cache hits may be: and searching a plurality of bits in the middle of the virtual address in the i-level Cache to select a group of tags (English: Tag) of Cache lines (English: Cache Line), wherein the Tag can be a high-order bit of a physical address, then comparing the high-order bit of the physical address obtained by the TLB with the selected group of tags, if the Tag of a certain group of Cache Line can be matched with the high-order bit of the physical address, the i-level Cache is hit, and otherwise, the i-level Cache is not hit.
The embodiment of the invention can acquire the virtual address included in the first memory access request, query the physical address corresponding to the virtual address from the page table Cache TLB, and acquire the first flag bit and the second flag bit preset for the physical page corresponding to the physical address in the page table entry PTE of the TLB, where the first flag bit is used to indicate whether the Cache of the processor includes the physical page, and the second flag bit is used to indicate the position of the physical page in the memory, and if the indication state of the first flag bit is that the Cache of the processor does not include the physical page, the physical page is read from the memory according to the second flag bit, so that the memory access efficiency can be improved, and the performance of the processor can be improved.
Fig. 5 is a schematic structural diagram of a memory access device according to a second embodiment of the present invention. The memory access device described in this embodiment includes: a query module 501, a setting module 502, a copy module 503, a recording module 504, an obtaining module 505, a reading module 506 and a clearing module 507, wherein:
the querying module 501 is configured to obtain a virtual address included in the second memory access request, and query a physical address corresponding to the virtual address from the page table cache TLB.
Specifically, when an execution mechanism of the CPU (e.g., a CPU Core) receives a second memory access request sent by a program for reading data, the query module 501 first obtains a virtual address included in the second memory access request, and then searches the TLB for a page table matching the virtual address, if the TLB stores a required page table, it is called a TLB Hit (english: TLB Hit), and then the query module 501 obtains a physical address included in the required page table in the TLB.
Further, if the query module 501 does not find a page table matching the virtual address in the TLB, a TLB Miss (english: TLB Miss) occurs, and the query module 501 queries from the page table of the memory to obtain a physical address corresponding to the virtual address.
A setting module 502, configured to set a first flag bit in a page table entry PTE of the TLB for a physical page corresponding to the physical address, and initialize an indication state of the first flag bit to a state that the physical page is not included in a Cache of the processor.
The setting module 502 may extend (1+ n) bits in each PTE, where 1 bit (denoted as a first flag bit) is used to indicate whether a physical page corresponding to the physical address exists in a Cache of the processor, the other n bits (denoted as a second flag bit) are used to indicate a position of the physical page corresponding to the physical address in the memory, the setting module 502 may initialize all the (1+ n) bits to be Null (english: Null) or 0, that is, when the first flag bit is Null or 0, it indicates that the physical page corresponding to the physical address is not in the Cache of the processor, and when the first flag bit is 1, it indicates that the physical page corresponding to the physical address is in the Cache of the processor.
Further, data in the memory is written into a large matrix by using bits as a unit, each Cell is called a Cell, and can be accurately positioned to a certain Cell as long as rows and columns are specified, which is a basic principle of memory addressing, such an array is called a Bank (a logic Bank in the invention) of the memory, a value of N is specifically determined according to the number N of the memory Bank, and a corresponding relation is as follows: 2nN, for example, if the number N of banks is 256, then N is 8, so that 9 bits are extended in each PTE, where 1 bit is used to indicate whether the physical page corresponding to the physical address exists in the Cache of the processor, and the other 8 bits are used to indicate the location of the physical page corresponding to the physical address in the memory (i.e., Bank ID).
Specifically, when the CPU is reset or powered on, the setting module 502 may initialize all the (1+ n) bits to Null or 0, so that the indication states of the first flag bit of the physical page corresponding to any one physical address are all the physical pages corresponding to any one physical address that are not included in the Cache of the processor.
The memory in the invention can be a Stacked dynamic random access memory Stacked DRAM.
A copying module 503, configured to read the physical page from the memory according to the physical address, and copy the physical page from the memory to a Cache of the processor.
A recording module 504, configured to record the identification information of the processor in the physical page included in the Cache of the memory.
Specifically, if the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, the copy module 503 directly reads the physical page from the memory according to the physical address, obtains the location (i.e., Bank ID) of the physical page in the memory, and copies the physical page to the Cache of the processor at the same time, and the record module 504 records the identification information of the processor in the physical page included in the Cache of the memory, so as to indicate whether the physical page is used by multiple CPU cores or multiple processes at the same time.
The identification information of the processor may specifically be CPU IDs that are automatically generated by the CPU cores and do not overlap with each other, for example, in a quad-Core CPU (including Core 0, Core 1, Core2, and Core 3), the CPU IDs may be respectively represented as 00, 01, 10, and 11, and the specific representation mode of the CPU ID is not limited in the embodiment of the present invention.
The setting module 502 is further configured to modify the indication state of the first flag bit to be that the Cache of the processor includes the physical page, and set a second flag bit in the PTE for the physical page, where the second flag bit is used to indicate a position of the physical page in the memory.
In a specific implementation, after the copying module 503 copies the physical page into a Cache of a processor, the setting module 502 may modify the indication state of the first flag bit to include the physical page in the Cache of the processor by setting 1 bit corresponding to the first flag bit to 1, and simultaneously the setting module 502 sets a second flag bit (N bits) in a corresponding PTE for the physical page, where for example, if the number N of the memory Bank is 64, N is 6, that is, at this time, 6 bits represent the position of the physical page in the memory, and assuming that the Bank ID of the physical page in the memory acquired by the CPU Core is 33, the setting module 502 may set the second flag bit to 100001, and at this time, (1+6) bits extended in the PTE may be 1100001 or 1000011.
The query module 501 is further configured to obtain the virtual address included in the first memory access request, and query a physical address corresponding to the virtual address from the TLB.
An obtaining module 505, configured to obtain a first flag bit and a second flag bit that are set in the PTE for the physical page corresponding to the physical address, where the first flag bit is used to indicate whether a Cache of a processor includes the physical page, and the second flag bit is used to indicate a location of the physical page in a memory.
A reading module 506, configured to read the physical page from the memory according to the second flag bit when the indication state of the first flag bit is that the physical page is not included in the Cache of the processor.
In some possible embodiments, the specific way for the reading module 506 to read the physical page from the memory according to the second flag bit is as follows:
and reading the physical page from the Cache of the memory according to the physical address.
And if the Cache of the memory does not comprise the physical page, reading the physical page from the memory according to the second zone bit.
The reading module 506 is further configured to, when the indication state of the first flag bit is that the physical page is included in the Cache of the processor, read the physical page from the Cache of the processor according to the physical address.
In some possible embodiments, the setting module 502 is further configured to modify an indication state of the first flag bit in the PTE to be that the processor Cache does not include the physical page when the TLB is replaced or the memory Cache is replaced.
The device further comprises: and an erasing module 507, configured to erase, according to the second flag, the identification information of the processor from the physical page included in the Cache of the memory, and erase the indication information of the second flag in the PTE.
Specifically, when the program accesses the physical page corresponding to the physical address again, the obtaining module 505 first obtains a first flag bit and a second flag bit set for the physical page from the PTE corresponding to the physical address, at this time, if the indication state of the first flag bit is that the physical page is included in the Cache of the processor, the reading module 506 reads the physical page from the Cache of the processor according to the physical address, if 1 bit corresponding to the first flag bit is reset to Null or 0 during the period, then the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, the reading module 506 reads the physical page from the memory according to the second flag bit (i.e. Bank ID), for example, the second flag bit is 100001, and the reading module 506 directly reads the physical page from the Bank with Bank ID of 33 in the memory.
In some possible implementations, when the TLB is replaced or the Cache of the memory is replaced (i.e., the physical page is replaced by another physical page), the setting module 502 may modify the indication state of the first flag bit in the PTE to be that the processor Cache does not include the physical page by setting 1 bit corresponding to the first flag bit to Null or 0, when it is determined that the processor identification information in the physical page included in the Cache of the memory also includes the CPU IDs of other CPU cores, the clearing module 507 notifies the corresponding CPU Core according to the CPU ID to set 1 bit corresponding to the first flag bit and n bits corresponding to the second flag bit included in the corresponding PTE in the TLB that are stored in each of the modules to Null or 0, meanwhile, the clear module 507 clears the identification information of the processor from the physical page included in the Cache of the memory according to the second flag bit, and finally clears the indication information of the second flag bit in the PTE (i.e., n bits are Null or 0).
The embodiment of the present invention can obtain a virtual address included in a second memory access request, query a physical address corresponding to the virtual address from a page table Cache TLB, set a first flag bit in a page table entry PTE of the TLB for a physical page corresponding to the physical address, initialize an indication state of the first flag bit to a state that the physical page is not included in a Cache of a processor, further read the physical page from the memory according to the physical address, copy the physical page from the memory to the Cache of the processor, record identification information of the processor in the physical page included in the Cache of the memory, modify the indication state of the first flag bit to indicate that the Cache of the processor includes the physical page, and set a second flag bit in the PTE for the physical page, where the second flag bit is used to indicate a position of the physical page in the memory; the virtual address included in the first memory access request is acquired, the physical address corresponding to the virtual address is queried from the TLB, and a first flag bit and a second flag bit set in the PTE for a physical page corresponding to the physical address are acquired, where the second flag bit is used to indicate a position of the physical page in a memory, and if the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, the physical page is read from the memory according to the second flag bit, otherwise, the physical page is read from the Cache of the processor according to the physical address, so that the memory access efficiency can be improved, and the performance of the processor is improved.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The foregoing detailed description is directed to a memory access method, apparatus, and computer system provided in the embodiments of the present invention, and specific examples are used herein to explain the principles and implementations of the present invention, and the descriptions of the foregoing embodiments are only used to help understand the method and its core ideas of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (14)
1. A memory access method, comprising:
acquiring a virtual address included in a first memory access request, and inquiring a physical address corresponding to the virtual address from a page table cache TLB;
acquiring a first flag bit and a second flag bit preset for a physical page corresponding to the physical address in a page table entry PTE of the TLB, wherein the first flag bit is used for indicating whether a Cache of a processor includes the physical page, and the second flag bit is used for indicating the position of the physical page in a memory;
if the indication state of the first flag bit is that the physical page is not included in the Cache of the processor, reading the physical page from the memory according to the second flag bit;
before the obtaining the virtual address included in the first memory access request, the method further includes:
acquiring the virtual address included in a second memory access request, and inquiring the physical address corresponding to the virtual address from the TLB; setting a first flag bit in the PTE aiming at the physical page corresponding to the physical address, and initializing the indication state of the first flag bit to the state that the physical page is not included in the Cache of the processor;
reading the physical page from the memory according to the physical address, copying the physical page from the memory to a Cache of the processor, and recording identification information of the processor in the physical page included by the Cache of the memory;
and modifying the indication state of the first flag bit to the state that the Cache of the processor comprises the physical page, and setting a second flag bit in the PTE aiming at the physical page, wherein the second flag bit is used for indicating the position of the physical page in the memory.
2. The method of claim 1, wherein reading the physical page from the memory according to the second flag bit comprises:
reading the physical page from the Cache of the memory according to the physical address;
and if the Cache of the memory does not comprise the physical page, reading the physical page from the memory according to the second zone bit.
3. The method of claim 1, further comprising:
and if the indication state of the first flag bit is that the Cache of the processor comprises the physical page, reading the physical page from the Cache of the processor according to the physical address.
4. The method of claim 2, further comprising:
and if the indication state of the first flag bit is that the Cache of the processor comprises the physical page, reading the physical page from the Cache of the processor according to the physical address.
5. The method of any one of claims 1 to 4, further comprising:
when the TLB is replaced or the Cache of the memory is replaced, modifying the indication state of the first flag bit in the PTE to the state that the Cache of the processor does not include the physical page;
removing the identification information of the processor from the physical page included in the Cache of the memory according to the second zone bit;
and clearing the indication information of the second flag bit in the PTE.
6. The method of claim 1,
the memory comprises Stacked dynamic random access memory Stacked DRAM.
7. A memory access device, comprising:
the query module is used for acquiring a virtual address included in the first memory access request and querying a physical address corresponding to the virtual address from the page table cache TLB;
an obtaining module, configured to obtain a first flag bit and a second flag bit preset for a physical page corresponding to the physical address in a page table entry PTE of the TLB, where the first flag bit is used to indicate whether a Cache of a processor includes the physical page, and the second flag bit is used to indicate a position of the physical page in a memory;
a reading module, configured to read the physical page from the memory according to the second flag bit when the indication state of the first flag bit is that the physical page is not included in the Cache of the processor;
the query module is further configured to, before obtaining a virtual address included in the first memory access request, obtain the virtual address included in the second memory access request, and query the physical address corresponding to the virtual address from the TLB;
wherein the apparatus further comprises: a setting module, configured to set a first flag bit in the PTE for the physical page corresponding to the physical address, and initialize an indication state of the first flag bit to a state that the physical page is not included in a Cache of the processor;
the copying module is used for reading the physical page from the memory according to the physical address and copying the physical page from the memory to a Cache of the processor;
the recording module is used for recording the identification information of the processor in the physical page included by the Cache of the memory;
the setting module is further configured to modify an indication state of the first flag bit to indicate that the Cache of the processor includes the physical page, and set a second flag bit in the PTE for the physical page, where the second flag bit is used to indicate a position of the physical page in the memory.
8. The apparatus of claim 7, wherein the reading module reads the physical page from the memory according to the second flag bit in a specific manner:
reading the physical page from the Cache of the memory according to the physical address;
and if the Cache of the memory does not comprise the physical page, reading the physical page from the memory according to the second zone bit.
9. The apparatus of claim 7,
the reading module is further configured to read the physical page from the Cache of the processor according to the physical address when the indication state of the first flag bit indicates that the Cache of the processor includes the physical page.
10. The apparatus of claim 8,
the reading module is further configured to read the physical page from the Cache of the processor according to the physical address when the indication state of the first flag bit indicates that the Cache of the processor includes the physical page.
11. The apparatus according to any one of claims 7 to 10,
the setting module is further configured to modify an indication state of the first flag bit in the PTE to indicate that the Cache of the processor does not include the physical page when the TLB is replaced or the Cache of the memory is replaced;
wherein the apparatus further comprises:
and the clearing module is used for clearing the identification information of the processor from the physical page included by the Cache of the memory according to the second flag bit and clearing the indication information of the second flag bit in the PTE.
12. The apparatus of claim 7,
the memory comprises Stacked dynamic random access memory Stacked DRAM.
13. A computer system comprising a memory and an apparatus as claimed in any one of claims 7 to 12.
14. A computer-readable storage medium storing a computer program for instructing associated hardware to perform the method of any one of claims 1 to 6.
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| CN112148665B (en) | 2019-06-28 | 2024-01-09 | 深圳市中兴微电子技术有限公司 | Cache allocation method and device |
| CN112463544B (en) * | 2020-12-17 | 2023-05-02 | 深圳软牛科技有限公司 | Program running monitoring method, device, equipment and storage medium |
| CN115119520A (en) * | 2021-01-20 | 2022-09-27 | 阿里巴巴集团控股有限公司 | Core-aware cache system and method for multi-core processor |
| CN113836053A (en) * | 2021-09-07 | 2021-12-24 | 上海砹芯科技有限公司 | Information acquisition method and device and electronic equipment |
| CN114116540B (en) * | 2022-01-26 | 2022-04-12 | 广东省新一代通信与网络创新研究院 | Method and system for improving buffer performance of processor page table |
| CN115080464B (en) * | 2022-06-24 | 2023-07-07 | 海光信息技术股份有限公司 | Data processing method and data processing device |
| CN116339916B (en) * | 2023-03-17 | 2023-11-10 | 摩尔线程智能科技(北京)有限责任公司 | Memory virtualization method and device, electronic equipment and storage medium |
| CN116644006B (en) * | 2023-07-27 | 2023-11-03 | 浪潮电子信息产业股份有限公司 | Memory page management method, system, device, equipment and computer medium |
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