CN106549650B - A kind of implementation method of the high order FIR filter based on FPGA - Google Patents
A kind of implementation method of the high order FIR filter based on FPGA Download PDFInfo
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- CN106549650B CN106549650B CN201611113213.0A CN201611113213A CN106549650B CN 106549650 B CN106549650 B CN 106549650B CN 201611113213 A CN201611113213 A CN 201611113213A CN 106549650 B CN106549650 B CN 106549650B
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- H03H2017/0081—Theoretical filter design of FIR filters
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Abstract
The invention proposes a kind of implementation methods of high order FIR filter based on FPGA, and more technical problems is occupied to logic unit in FPGA for solving high order FIR filter in existing high order FIR multiphase filtering implementation method.Implementation method includes: to select the parameter of ptototype filter；Prototype filter h (n)；Poly phase is carried out to ptototype filter h (n), obtains multiphase filter；Module division is carried out to each multiphase filter；By the storage of multiphase filter coefficient into module ROM；The coefficient of multiphase filter in read module ROM；The read-write of the module RAM controlled by system clock is enabled, write address controls signal and read address controls signal, is cached and is read to input data；Multiply-add operation is carried out to multiphase filter coefficient and input data using multiply-accumulate module and exports operation result.The present invention is few to the occupancy of logic unit in FPGA, is simple and efficient, it is easy to accomplish.
Description
Technical field
The invention belongs to digital signal processing technique fields, are related to a kind of method of Large N FIR digital filter, specifically relate to
And a kind of implementation method of the high order FIR filter based on FPGA, the signal filtering that can be used in digital channelizing.
Background technique
Good digital channelizer can effectively promote the flexibility and extensibility of satellite repeater, complete communication chain
Signal exchange in road between each sub-channels, while system error bit ability is dramatically improved, thus become broadband satellite and move
The urgent need in dynamic communications applications field.However each sub-channel signal be highly susceptible in transmission process noise and other
The interference of sub-channel signal, this will lead to entire communication system performance and sharply deteriorates, and how effective filter out noise and with outer dry
The signal for disturbing and farthest restoring each communications sub-channel, be broadband satellite mobile communication field important subject it
One.
The most frequently used implementation method of digital filter has endless impulse response filter IIR and the filter of limited long impulse response
Two kinds of wave device FIR, wherein FIR filter is made of limited tap coefficient, can be had while amplitude characteristic arbitrarily designs
Accurate, stringent linear phase, ensure that the stability of system.When flatness and cut-off speed of the system for filter are wanted
In the case where asking relatively high, the order of FIR filter can also be got higher therewith, high order FIR filter in each communication system all
It has a wide range of applications.
On-site programmable gate array FPGA, it is further sent out on the basis of the programming devices such as PAL, GAL or CPLD
The product of exhibition, as one of field specific integrated circuit (ASIC) semi-custom circuit, it had both had the high logic of gate array
Density and high reliability, and the user-programmable characteristic with codified logical device, so that high order FIR filter is able to reality
It is existing.
Currently based on FPGA high order FIR filter implementation there are mainly three types of: FIR based on distributed algorithm filtering
Base in FIR filter and time domain on device, frequency domain based on Fast Fourier Transform (FFT) (Fast Fourier transform, FFT)
In the FIR filter of multiplier architecture, wherein for thousand the ranks even FIR filter of ten thousand ranks, based on distributed algorithm
The fpga logic resource of FIR filter consumption is huge.FIR filter based on Fast Fourier Transform (FFT) can effectively drop
The use of low fpga logic resource, but data processing delay is too big, reduces the overall performance of system.Multiplication is based in time domain
The FIR filter of device structure is cached using register pair input signal, completes filtering by multiplying and add operation
Process ensure that generating date.Such as Sun Chonglei, Wang great Qing are on Electonic Sci.&Tech./Nov.15,2012
The article that the entitled high order FIR decimation filter based on FPGA effectively realizes structure has been delivered, a kind of improved base is disclosed
In the FIR filter of multiplier architecture, it combines high order FIR filter and multiphase filter structure, using time-sharing multiplex skill
Art, by improving FPGA working clock frequency, to the filtering number after down-sampled and per the sum of products behaviour in FIR filter all the way
Making one multiplier of multiplexing both ensure that data real time high-speed compared with traditional FIR filter based on multiplier architecture
Processing, and take full advantage of the multiplier unit in FPGA.But this method still occupies during completing multiphase filtering
A large amount of logic unit.
Summary of the invention
It is an object of the invention to overcome the problems of the above-mentioned prior art, a kind of high-order based on FPGA is proposed
The implementation method of FIR filter is cached and is read to input data using RAM resource in FPGA in conjunction with multiphase filter structure
It takes, filter coefficient is controlled using system clock and input data does multiply-accumulate operation, and operation result is exported, is being guaranteed
While system data is handled in real time, high order FIR filter is effectively reduced to the occupancy of logic unit in FPGA.
To achieve the above object, the technical solution adopted by the present invention includes the following steps:
1. a kind of implementation method of the high order FIR filter based on FPGA, it is characterised in that the following steps are included:
(1), ptototype filter parameter is selected；
(2), order is designed using frequency domain sample method and Hamming window function method according to the ptototype filter parameter selected
For the ptototype filter h (n) of N, wherein N > 500, realizes step are as follows:
(2a) carries out sampling site using frequency spectrum function of the frequency domain sample method to root raised cosine filter, obtains frequency domain sampling point；
(2b) carries out inverse Fourier transform to frequency domain sampling point, obtains time domain samples；
(2c) intercepts time domain samples using Hamming window function method, obtains ptototype filter h (n)；
(3), poly phase is carried out to ptototype filter h (n), obtains the multiphase filter that M order is N/M, wherein 2≤
M < N；
(4), module division is carried out to obtained each multiphase filter, obtains filter coefficient module ROM, data buffer storage
With the multiply-accumulate module of read module RAM and DSP48E1；
(5), by the coefficient of multiphase filter, mode is stored in the module ROM in FPGA in order；
(6), the multiphase filter by system clock cycle being stored in ROM module in read step (5) is
Number；
(7), RAM module is controlled by system clock control module, input data is cached and is read, realize step
Are as follows:
(7a) by system clock control module, the read-write for obtaining RAM module enables wen, write address control signal waddr
Signal raddr is controlled with read address；
(7b) enables wen by obtained read-write and write address controls signal waddr, and input data is cached to module RAM
In；
(7c) enables wen by obtained read-write and read address controls signal raddr, the input to being buffered in module RAM
Data are read out；
(8), the input data that will be read in the coefficient of the multiphase filter read in step (6) and step (7c), input
Operation is carried out in the multiply-accumulate module of DSP48E1 into FPGA, and operation result is exported.
Compared with the prior art, the invention has the following advantages:
The present invention using by system clock due to controlling to obtain during caching input signal and reading
Module RAM read-write is enabled, write address control signal and read address control signal, the RAM resource in FPGA is written and read
Operation is guaranteeing system number compared with the method that input signal is cached and read using logic unit in the prior art
While processing when factually, the occupancy of logic unit in FPGA is significantly reduced, is simple and efficient, it is easy to accomplish.
Detailed description of the invention
Fig. 1 is implementation process block diagram of the invention；
Fig. 2 is the realization block diagram of multiphase filter of the invention.
Specific embodiment
Below in conjunction with drawings and examples, the present invention is described in further detail.
Referring to Figures 1 and 2, the present invention the following steps are included:
Step 1, ptototype filter parameter is selected.
The parameter of ptototype filter is mainly according to speech signal processing system, image-signal processing system and digital channelizing
The performance requirement of device system selects, and the present embodiment selects ptototype filter to join according to the performance requirement of digital channelizer system
Number, the performance requirement of digital channelizer system are as follows:
(1) bandwidth chahnel is 160MHz, is divided into 64 sub-channels；
(2) effective bandwidth is 120MHz, including 48 sub-channels in the channel；
(3) subchannel bandwidth is 2.5MHz；
(4) protection interval is 327KHz between subchannel；
The ptototype filter parameter of selection is as shown in table 1:
1 ptototype filter parameter of table
| Bandwidth | Protection interval | Line amplitude jitter in passband | Stopband attenuation |
| 2.5MHz | 327KHz | < 0.5dB | < -40dB |
Step 2, according to the ptototype filter parameter selected in step 1, using frequency domain sample method and Hamming window function method, if
The ptototype filter h (n) that order is N is counted, wherein N > 500, realizes step are as follows:
(2a) carries out sampling site using frequency spectrum function of the frequency domain sample method to root raised cosine filter, obtains frequency domain sampling point, root
The frequency spectrum function expression formula of raised cosine filter are as follows:
Wherein, TsFor symbol period, α is the roll-off factor of root raised cosine filter.
(2b) carries out inverse Fourier transform to frequency domain sampling point, obtains time domain samples, inverse Fourier transform expression formula are as follows:
(2c) intercepts time domain samples using Hamming window function method, obtains ptototype filter h (n), Hamming window function
Expression formula are as follows:
W (m)=0.54-0.46 × cos (2 × π × m/ (N-1)) (2-3)
Wherein, m is independent variable, and 0≤m≤N-1.
The order N=1600 of the present embodiment Central Plains mode filter h (n), symbol period Ts=(1/2.5M) s, root raised cosine
Roll-off factor α=0.13 of filter.
Step 3, poly phase is carried out to ptototype filter h (n), the multiphase filter that M order is N/M is obtained, wherein 2
≤ M < N.Realize that steps are as follows:
The system function of (3a) to ptototype filter h (n)It is deformed:
Wherein, L=N/M；
(3b) uses Ek(zM) in the system function of deformed ptototype filter h (n)
Equivalent substitution is carried out, the poly phase form of the system function of ptototype filter h (n) is obtained:
Wherein, k is independent variable, and 0≤k≤M-1；
(3c) analyzes the poly phase form of the system function of ptototype filter h (n), and having obtained M order is L
Multiphase filter, expression formula are as follows:
hk(n)=h (nM+k) (3-3)
The number M=64 of multiphase filter, the order L=25 of each multiphase filter in the present embodiment.
Step 4, module division is carried out to obtained each multiphase filter, it is slow obtains filter coefficient module ROM, data
It deposits and the multiply-accumulate module of read module RAM and DSP48E1.
The realization process of multiphase filter is as shown in Figure 2.
Step 5, by the coefficient of multiphase filter, mode is stored in the module ROM in FPGA in order.
Step 6, the multiphase filter by system clock cycle being stored in ROM module in read step 5 is
Number.
Step 7, by system clock control module RAM, input data is cached and is read, realize step are as follows:
(7a) is controlled by system clock, and the read-write for obtaining module RAM enables wen, write address control signal waddr and reading
Address control signal raddr.
It is controlled by system clock, obtains the write address control signal waddr of module RAM, be by system clock to first
The signal waddr that initial value is 0 carries out what mould N/M incremental count was realized, i.e., whenever system clock pulse arrives, waddr is incremented by 1,
When waddr be equal to N/M-1, then next system clock pulse arrive when, waddr is reset to 0, is looped back and forth like this；
It is controlled by system clock, obtains the read address control signal raddr of module RAM, be by system clock to first
Initial value be current write address signal raddr carry out mould N/M countdown realize, i.e., whenever system clock pulse arrive,
Raddr successively decreases 1, when raddr is equal to 0, then when next system clock pulse arrives, raddr is reset to N/M-1, so
It moves in circles.
(7b) controls signal waddr by write address and is modified to write address when reading and writing enabled wen is 1, then will be defeated
Enter data din to be sequentially written in module RAM according to the write address after change.
(7c) controls signal raddr by read address and is modified to read address when reading and writing enabled wen is 0, then will delay
There are the data in module RAM to sequential read out in register dout according to the read address after change.
Step 8, the input data that will be read in the coefficient of the multiphase filter read in step 6 and step (7c), input
Operation is carried out in the multiply-accumulate module of DSP48E1 into FPGA, and operation result is exported.
The implementation method combination multiphase filter structure of high order FIR filter proposed by the present invention based on FPGA uses
RAM resource in FPGA is cached and is read to input data, controls filter coefficient with system clock and input data is done
Multiply-accumulate operation, and operation result is exported.While guaranteeing that system data is handled in real time, high-order is effectively reduced
Occupancy of the FIR filter to logic unit in FPGA.
Claims (9)
1. a kind of implementation method of the high order FIR filter based on FPGA, it is characterised in that the following steps are included:
(1), ptototype filter parameter is selected；
(2), according to the ptototype filter parameter selected, using frequency domain sample method and Hamming window function method, designing order is N's
Ptototype filter h (n), wherein N > 500, realizes step are as follows:
(2a) carries out sampling site using frequency spectrum function of the frequency domain sample method to root raised cosine filter, obtains frequency domain sampling point；
(2b) carries out inverse Fourier transform to frequency domain sampling point, obtains time domain samples；
(2c) intercepts time domain samples using Hamming window function method, obtains ptototype filter h (n)；
(3), poly phase is carried out to ptototype filter h (n), the multiphase filter that M order is N/M is obtained, wherein 2≤M <
N；
(4), module division is carried out to obtained each multiphase filter, obtains filter coefficient module ROM, data buffer storage and reading
Modulus block RAM and the multiply-accumulate module of DSP48E1；
(5), by the coefficient of multiphase filter, mode is stored in the module ROM in FPGA in order；
(6), the coefficient of the multiphase filter in ROM module by system clock cycle is stored in read step (5)；
(7), RAM module is controlled by system clock control module, input data is cached and is read, realize step are as follows:
(7a) by system clock control module, the read-write for obtaining RAM module enables wen, write address control signal waddr and reading
Address control signal raddr；
(7b) enables wen by obtained read-write and write address controls signal waddr, and input data is cached in module RAM；
(7c) enables wen by obtained read-write and read address controls signal raddr, to the input data being buffered in module RAM
It is read out；
(8), the input data that will be read in the coefficient of the multiphase filter read in step (6) and step (7c), is input to
Operation is carried out in the multiply-accumulate module of DSP48E1 in FPGA, and operation result is exported.
2. the implementation method of the high order FIR filter according to claim 1 based on FPGA, it is characterised in that: step (1)
Described in ptototype filter parameter, including line amplitude jitter and stopband attenuation in bandwidth, protection interval, passband.
3. the implementation method of the high order FIR filter according to claim 1 based on FPGA, it is characterised in that: step
The frequency spectrum function of root raised cosine filter described in (2a), expression formula are as follows:
Wherein, TsFor symbol period, α is the roll-off factor of root raised cosine filter.
4. the implementation method of the high order FIR filter according to claim 1 based on FPGA, it is characterised in that: step
Inverse Fourier transform described in (2b), expression formula are as follows:
5. the implementation method of the high order FIR filter according to claim 1 based on FPGA, it is characterised in that: step (2)
Described in Hamming window function, expression formula are as follows:
W (m)=0.54-0.46 × cos (2 × π × m/ (N-1))
Wherein, m is independent variable, and 0≤m≤N-1, N are the order of ptototype filter h (n).
6. the implementation method of the high order FIR filter according to claim 1 based on FPGA, it is characterised in that: step (3)
Described in ptototype filter h (n) carry out poly phase, realize step are as follows:
The system function of (3a) to ptototype filter h (n)It is deformed:
Wherein, L=N/M；
(3b) uses Ek(zM) in the system function of deformed ptototype filter h (n)Carry out etc.
Valence replacement, obtains the poly phase form of the system function of ptototype filter h (n):
Wherein, k is independent variable, and 0≤k≤M-1；
(3c) analyzes the poly phase form of h (n) system function of ptototype filter, and having obtained M order is the more of L
Phase filter, expression formula are as follows:
hk(n)=h (nM+k).
7. the implementation method of the high order FIR filter according to claim 1 based on FPGA, it is characterised in that: step
It is controlled described in (7a) by system clock, obtains the write address control signal waddr of module RAM, be to pass through system clock
The signal waddr for being 0 to initial value carries out what mould N/M incremental count was realized；Described is controlled by system clock, obtains module
The read address of RAM controls signal raddr, is to carry out mould to the signal raddr that initial value is current write address by system clock
What N/M countdown was realized.
8. the implementation method of the high order FIR filter according to claim 1 based on FPGA, it is characterised in that: step
Input data is cached in module RAM described in (7b), process is to pass through write address control when reading and writing enabled wen is 1
Signal waddr processed is modified write address, then input data is sequentially written in module RAM according to the write address after change
In.
9. the implementation method of the high order FIR filter according to claim 1 based on FPGA, it is characterised in that: step
The input data being buffered in module RAM is read out described in (7c), process is to lead to when reading and writing enabled wen is 0
It crosses read address control signal raddr to be modified read address, then the data in module RAM will be buffered according to the reading after change
Address is sequential read out.
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| CN107508575B (en) * | 2017-08-11 | 2021-02-26 | 西安电子科技大学 | Analog finite impulse response filter |
| CN108777569A (en) * | 2018-05-23 | 2018-11-09 | 成都玖锦科技有限公司 | Arbitrary time-delay method based on multiphase filter |
| CN108900177B (en) * | 2018-06-14 | 2022-08-02 | 福建星海通信科技有限公司 | Method for filtering data by FIR filter |
| CN108964635B (en) * | 2018-06-15 | 2022-07-29 | 西安空间无线电技术研究所 | Anti-irradiation high-order high-speed parametric reconstruction FIR filter design method and system |
| CN110233606A (en) * | 2019-05-28 | 2019-09-13 | 北京星网锐捷网络技术有限公司 | Multi tate Transform Filtering and device |
| CN110957995B (en) * | 2019-10-25 | 2023-06-30 | 四川汇源光通信有限公司 | IIR filtering system of distributed fault monitoring device and design method thereof |
| CN111525910A (en) * | 2020-04-28 | 2020-08-11 | 上海工程技术大学 | Filter device for high-speed signal transmission equipment |
| CN112968688B (en) * | 2021-02-10 | 2023-03-28 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Method for realizing digital filter with selectable pass band |
| CN112596087B (en) * | 2021-03-04 | 2022-04-08 | 长沙海格北斗信息技术有限公司 | FIR digital filtering method for satellite navigation, navigation chip and receiver |
| CN115102524B (en) * | 2022-07-07 | 2023-08-08 | 武汉市聚芯微电子有限责任公司 | Filter |
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