CN106537785B - Fractional N-type phase-locked loop circuit - Google Patents

Abstract

Provide a kind of fractional N-type phase-locked loop (PLL) circuit (104,600,800).PLL circuit (104,600,800) generates spread spectrum clock (SSC), inhibits phase interpolator non-linear using averaging.PLL circuit (600,800) includes the fractional divider (606,806) filtered with mixing finite impulse response (FIR) (FIR).Further it is provided that the small-sized and low power divider for mixing FIR fractional N-types PLL circuit (600,800).

Description

Fractional N-type phase-locked loop circuit

Technical field

The embodiment of the present invention is related to the field of electronic circuit, and in particular to a kind of score for frequency-spreading clock generator Divide type fractional N-type phase-locked loop.

Background technology

Spread spectrum clock (Spread Spectrum Clock, SSC) signal is used for electronic building brick, in favor of inhibiting electromagnetism dry It disturbs.SSC signals clock with different frequency according to desired modulation shape function (such as sine wave, triangular wave etc.), it is preceding Different frequency is stated usually to vibrate between min/max.SSC signals can be by according to scheduled modulating frequency and modulation angle Clock signal frequency caused by phase-locked loop circuit (Phase Locked Loop, PLL) is modulated and is generated.Integral Delta modulation device (sigma-delta modulator) type fractional N-type phase-locked loop (fractional-N PLL) can be used to produce Raw SSC signals；However, the quantizing noise of integral triangle modulator, which can export phase-locked loop, causes shake (jitter).

Invention content

Embodiment describes the technology using fractional N-type phase-locked loop (PLL).Some embodiments description is used for spread spectrum clock (SSC) the fraction division type fractional N-type phase-locked loop (PLL) of generator, is inhibited using phase average technology in phase It is non-linear to plug in device.Some embodiments are based on that there is mixing finite impulse response (FIR) (finite impulse response, FIR) to filter The fractional divider of wave describes fractional N-type phase-locked loop.Some embodiments are described for mixing finite impulse response (FIR) fractional N-type The small-sized and low power divider of phase-locked loop.

Description of the drawings

In appended accompanying drawing by example but it is unrestricted in a manner of illustrate the embodiment of the present invention, in the drawings, phase Identical element is referred to reference numeral.

Fig. 1 is to show frequency-spreading clock generator circuit according to one embodiment of the invention.

Fig. 2A is to be shown to generate " mmd_clk " and delayed clock " mmd_clk_d " signal according to one embodiment of the invention Multi-modulus frequency divider schematic diagram.

Fig. 2 B are the sequence diagram that multi-modulus frequency divider and phase interpolator are shown according to one embodiment of the invention.

Fig. 3 A are the component that integral triangle modulator fractional N-type phase-locked loop is shown according to one embodiment of the invention.

Fig. 3 B are the waveform that phase average technology is shown according to one embodiment of the invention.

Fig. 4 A and Fig. 4 B are to be shown to inhibit phase interpolator using phase average operation according to one embodiment of the invention Nonlinear circuit.

Fig. 5 is to show spread spectrum clock (SSC) generator circuitry according to one embodiment of the invention.

Fig. 6 A to Fig. 6 C are to show that the mixing to be filtered to quantizing noise is limited according to one embodiment of the invention Impulse response filter component.

Fig. 7 A are the frequency divider control logic shown according to one embodiment of the invention for fractional divider.

Fig. 7 B and Fig. 7 C are to show used finite impulse response (FIR) leggy score point according to one embodiment of the invention The function of frequency device.

Fig. 8 A to Fig. 8 D are to show finite impulse response (FIR) feedback divider circuit according to one embodiment of the invention.

Fig. 9 is the frequency divider control logic of frequency divider of being flashed according to one embodiment of the invention.

Figure 10 is to show the device comprising the logic using the SSC signals generated according to one embodiment of the invention or be System.

Specific implementation mode

This document describes the fractional dividers and fractional N-type phase-locked loop (PLL) for spread spectrum clock (SSC) generator Devices, systems, and methods.Hereinafter, detail is elaborated to provide the comprehensive understanding to embodiment.However, this field It will be recognized that herein buy book technology can be put into practice in the case of no following one or more details, Or it is put into practice using other methods, component, material etc..In other cases, known structure, material are not shown or described in detail Material or operation, to avoid fuzzy some aspects.

In certain embodiments of the present invention, integral triangle modulation type fractional N-type phase-locked loop can be used to generate spread spectrum Clock (SSC) signal is used by electronic building brick to inhibit electromagnetic interference (EMI).Quantization caused by integral triangle modulator Noise, which can export phase-locked loop, causes shake；In order to reduce this quantizing noise, the embodiment of the present invention can utilize following more Phase frequency divider (multi-phase dividers), finite impulse response (FIR) (FIR) filter and digital analog converter (DAC) Compensation technique.

Phase rotation device (Phase rotator) or phase interpolator (Phase Interpolator, PI) allow it to adopt The phase of sample clock is able to be adjusted with very small increment.Fractional N-type frequency divider allows phase-locked loop synthesizer to be able to With the frequency resolution also subtleer than reference frequency.Fractional divider may include a phase interpolator, and if frequency dividing ratio stepping (step) enough subtle, it can be used for integer phase-locked loop, or can be used for integral triangle type fractional N-type phase-locked loop to reduce quantization Noise；However, the non-linear of phase interpolator may cause surging (spurs) in exporting clock spectrum or mix attached wave.Such as Lower described, the referred to herein as program of phase average technology removes output clock frequency to inhibit the non-linear of phase interpolator Surging in spectrum and mixed attached wave.

Fig. 1 is to show frequency-spreading clock generator circuit according to one embodiment of the invention.In this embodiment, spread spectrum clock (SSC, spread spectrum clock) generation circuit 100 includes fractional N-type phase-locked loop (PLL) 104, is shown into one Step includes phase frequency detector 105, and phase frequency detector (phase-frequency detector, PFD) 105 receives aobvious It is shown as the reference clock signal of " ref_clk " and is shown as the fractional divider 510 of " pi_out " (further chatting in lower State) output.Phase frequency detector 105 may compare frequency and phase difference between ref_clk and pi_out.For example, working as The rising edge leading (or backwardness) of ref_clk can generate (or downward) pulse upwards in pi_out, then PFD105, continue The phase difference therebetween such as time.PFD105 is shown as is provided to charge pump 106 by signal upwardly or downwardly；Loop filter Device 107 is filtered to upward (up)/(dn) pulse downwards, and provides the output of increase/reduction to control voltage controlled oscillator (voltage controlled oscillator, VCO) 108, in wherein aforementioned increase ,/the control voltage of reduction can increase/drops The frequency of oscillation of low voltage controlled oscillator.The output for being shown as the VCO108 of " vco_clk " is the spread spectrum clock output letter of circuit 100 Number, and should be compared with the vco_clk that no spread spectrum clock (SSC) is modulated.

Fractional divider 510 can change in wherein frequency divider numerical value per a period of time, including multi-modulus frequency divider (Multi-Modulus Divider, MMD) 512 receives vco_clk and n phase interpolator 514, receives and From in MMD through frequency elimination clock signal；Each component is shown as uses independent control word group-" mmd " and " ph respectively<n-1: 0>“.The frequency dividing ratio of control word group " mmd " control MMD512, and control word group " ph<n-1:0>" n phase interpolators of selection 514 phase.Above-mentioned control word group comes from the component of following digital squares 150.In addition, in addition to provide output to PFD105 with Outside, fractional divider 510 also provides output clock " clk " to integral triangle modulator 120.

As shown in this figure, digital square 150 includes three fraction-spread spectrum clock (SSC) shape generators 104, integral Delta modulation device 120 and phase accumulator (phase accumulator) (or the phase controlling for fractional divider is patrolled Volume) 124.Spread spectrum clock (SSC) shape generator 102 provides an output to integral triangle modulator 120.SSC shape generators 102 be shown as generate several output signals (herein otherwise known as code)." int.frac " code is frequency dividing ratio, wherein " int " For the integer part of frequency dividing ratio, and the fractional part that " frac " is frequency dividing ratio.Since n phase interpolators 514 are for dividing Device 510, therefore frequency divider has 1/ (2ⁿ) stepping.Therefore, " frac<k-n+1,0>" lower orientation be input to integral triangle modulation Device 120, and the output of integral triangle modulator increases back the upper position " frac at summation node 122<k-1:k-n>" and " int " (the wherein length of " frac " with k).

The integer part of the output of integral triangle modulator 120 is shown as " sdm_int ", and fractional part is " sdm_ frac<n-1:0>”.Code " sdm_frac<n-1:0>" it is input to phase accumulator 124 (herein otherwise known as phase rotation device), Its output code " ph<n-1:0>”.Code " ph<n-1:0>" control n phase interpolator 514 output phase, and generation Code " sdm_frac<n-1:0>" control phase interpolator jumped in each period it is phase stepping.The carrying of phase accumulator Position increases to " sdm_int " at summation node 126, and the frequency dividing ratio of summation " mmd " control MMD512.

Fig. 2A is to be shown to generate " mmd_clk " and delayed clock " mmd_clk_d " signal according to one embodiment of the invention Multi-modulus frequency divider schematic diagram.Multi-modulus frequency divider (MMD) 200 (it can for example be corresponded to the MMD512 of Fig. 1) wraps Containing integer frequency divider 202 and two-digit flip-flop (digital flip-flops, DFFs) 204 and 206.“vco_clk” It is input to integer frequency divider 202, and its output signal " div_out "；This clock is sampled by DFF204, and aforementioned DFF204 is shown It is triggered at by clock signal " vco_clk ", and this DFF outputs " mmd_clk ".This signal is shown as to be adopted by DFF206 again Sample, aforementioned DFF206 are also triggered by " vco_clk ", and this DFF exports another clock signal " mmd_clk_d ".

Fig. 2 B embodiments according to the present invention show MMD (such as MMD512 of Fig. 1) and phase interpolator (such as Fig. 1 Phase interpolator 514) sequence diagram.Sequence diagram 250 shows that " mmd_clk_d " is the clock signal " mmd_clk " through frequency elimination Delay；Timing period is shown as " Tvco ", and it includes a voltage controlled oscillator clock cycle." mmd_clk " and " mmd_clk_ D " signals are input to a n phase interpolator, and entire Tvco is divided into 2 by phase interpolatorⁿA phase (that is, from input clock Phase generate 2ⁿThe output of a phase offset).

The operation of fractional divider can be described by following examples：One 4 phase interpolators can provide one 1/ 16 is phase stepping, and the frequency dividing ratio of such as 40+7/16 can be achieved.Its step can be descended described：

Assuming that " vco_clk " and initial phase interpolator phase originate in " 0 ", the frequency dividing ratio of MMD can be set as " 40 ", meaning Refer to the 40th and the 41st period of MMD outputs " vco_clk ".The phase stepping of phase interpolator is set as " 7 ", first phase Position interpolater output betides 40+7/16Tvco.

Later, MMD is set as " 40 " again, and it provides the 80th and the 81st period of " vco_clk "；However, Phase interpolator is set as " 14 ", and second phase interpolator betides the time point of 80+14/16Tvco.However, first and second Time difference between phase interpolator output is 40+7/16Tvco.

MMD connectings are set as " 41 ", and it provides the 121st of " vco_clk " and the 122nd period to phase interpolator Input；Phase interpolator is set as " 5 ".The output of third phase interpolater betides 121+5/16Tvco, second and third phase Time difference between the interpolater output of position is 40+7/16Tvco again.

Therefore, the division ratio of 40+7/16 is achieved.Referring back to Fig. 1, phase accumulator 124 is by phase stepping control Word group " sdm_frac processed<n-1:0>" controlled, overflow increases to " int ", and that it changes the frequency dividing ratios of MMD512.

In embodiment, phase interpolator be it is non-linear, it is intended that phase interpolator it is phase stepping not consistent, so may be used Quantizing noise can be caused to improve.For example, in order to realize the frequency dividing ratio of 40+7/16, as the MMD of " vco_clk " in 40 periods Counter is when immobilizing, and non-uniform (that is, the 7/16Tvco from ph0 to ph7 is different from for phase interpolator phase stepping Ph1 to ph8).Therefore, non-linear be likely to result in of phase interpolator mixed attached involves surging, thereby increases and it is possible to can increase quantizing noise.

Fig. 3 A are the component that integral triangle modulator fractional N-type phase-locked loop is shown according to one embodiment of the invention.In In this example, there is 2ⁿA fractional divider 310, phase frequency detector (PFD) 302 and the electricity for being coupled to loop filter 306 Lotus pump 304.Charge pump current is the 2 of primary currentⁿ/ mono-.If such as n=4, have 16 fractional dividers, 16 PFD And 16 charge pumps.It is assumed that first phase interpolator realizes 7/ by from the 12nd phase step to third phase 16Tvco's is phase stepping, and then second phase interpolator is realized by from the 13rd phase step to the 4th phase 7/16Tvco's is phase stepping, such.Therefore, the summation of 16 phase steps operation is 7 periods, and phase summation is by 16 A charge pump is averaged；If PFD302 and charge pump 304 match, equal is phase stepping for the phase stepping of 7/16Tvco. If this case step is further shown by Figure 35 0 by Fig. 3 B；However, the practicable less component of the embodiment of the present invention, and Still most equal quantization noise suppressed can be realized in corresponding phase summation is average, as described below.

Fig. 4 A and Fig. 4 B are to be shown to inhibit phase interpolator using phase average operation according to one embodiment of the invention Nonlinear circuit.As shown in circuit 400, single shared multi-modulus frequency divider (MMD) 402 is utilized, and its frequency dividing ratio It is controlled by signal " mmd_0 ".

This signal is shown as produced by the control logic 490 by Fig. 4 B, and may include the integer point of first phase interpolater Frequency ratio.Other than signal " clk " and " clk_d ", MMD402, which is shown as, provides another clock " clk_2d ", is " clk " Two Tvco delays.

Similar to above-described embodiment, 2ⁿA phase interpolator is used, and is controlled by signal " ph_k ", wherein as controlled Shown by circuit 450 processed, k changes to 2 from 1ⁿ.Multiplexer (MUX) 406 is used for each phase interpolator 404；Each multiplexer choosing One group of clock signal (being shown as { clk, clk_d }) or another group of clock signal (being shown as { clk_d, clk_2d }) are selected, with defeated Enter to its respective phase interpolator.

Each multiplexer 406 is shown as to be controlled by signal " delta_mmd_k "；In this example, control word group is single One, to be selected from two groups of clock signals.As shown in control circuit 450, " ph_k " and " delta_mmd_k " signal comes from In the output of summation node 452.If for example, the ph_0 at a period is 9/16, and the initial phase of k-th of phase interpolator is set It is set to 11/16, then " ph_k " is " 2/16 " and " delta_mmd_k " is " 1 ".

In this example, initial phase depends on desired phase average；For example, if desired phase average granularity is 16, then first phase accumulator most first meeting is set as 0/16, and first phase interpolater jumps from the phase 0 of beginning, second phase Accumulator is initially set to 1/16, and then second phase interpolater jumps from the phase 1 of beginning.For remaining phase interpolator Also similarly (that is, third phase interpolater jumps from the phase " 2 " of beginning, and the 16th phase interpolator jumps from phase " 15 "). However, the practicable less component of the embodiment of the present invention, and still can be realized in corresponding phase summation is average most of Equal quantization noise suppressed.For desired phase average granularity 4, first phase interpolater will be jumped since phase " 0 " Jump, second phase interpolater initially jump from phase " 4 ", and third phase interpolater will initially jump from phase " 8 ", Yi Ji Four phase interpolators will initially jump from phase " 12 ".Therefore, in this embodiment, compared with prior art, only Use three additional PFD and three additional phase interpolators.

As discussed above, the quantizing noise of the integral triangle modulator in fractional N-type phase-locked loop can draw output clock It shakes dynamic.In some embodiments, the mixing finite impulse response (FIR) feedback divider based on fractional divider can be used to decrement Change noise, and also inhibits the non-linear caused surging and noise of used phase interpolator.

Fig. 5 is to show spread spectrum clock (SSC) generator circuitry according to one embodiment of the invention.In this embodiment, expand Frequency clock (SSC) generation circuit 500 includes functional unit identical with the SSC generation circuits 100 of Fig. 1, in addition to digital square 550 Not comprising spread spectrum clock shape generator (that is, compared with spread spectrum clock shape generator 104 of Fig. 1).

The quantizing noise of integral triangle modulator 120 in fractional N-type phase-locked loop can cause shake to output clock；In In some embodiments, in order to reduce quantizing noise, several technologies such as leggy frequency divider, finite impulse response (FIR) and digital simulation Converter compensation technique is used.In following embodiments, the mixing finite impulse response (FIR) feedback point based on fractional divider Frequency device to reduce quantizing noise (in addition to inhibit phase interpolator it is non-linear caused by surging and noise other than), and this side Case can be merely with single a MMD.

As shown in the figure, multi-modulus frequency divider (MMD) 512 and n phase interpolators 514 form fractional divider 510, and It is utilized respectively independent control word group " mmd " and " ph<n-1:0>”.Control word group " mmd " controls the frequency dividing of MMD frequency dividers Than, and control word group " ph<n-1:0>" selection n phase interpolator phase.Two control word groups are both from number side Block 550.Digital square can be divided into two parts-and involve the part of integral triangle modulator 120 and involve phase-accumulated The part of device 124 (or phase control logic for fractional divider 510).

Fig. 6 A to Fig. 6 C embodiments according to the present invention show the limited arteries and veins of mixing to be filtered to quantizing noise Punching response filtering unit.In this embodiment, the finite impulse response filter fractional N-type phase-locked loop 600 of Fig. 6 A is shown as packet Containing multiple phase frequency detectors (PFD) 602, charge pump 604, leggy feedback divider 606 and loop filter 608, To be filtered to quantizing noise.The output of triangular integration modulator (delta-sigma) 610 is applied to digital flip-flop (DFF) chain 612, postpone output (being shown as MC0 ... MC6, MC7, MC8 ... the MC15 in the circuit 650 of Fig. 6 B) to generate, these delays are defeated Go out to control leggy feedback divider 606.In order to be further reduced quantizing noise, using fractional divider, and non-integer division of frequency Device.

As shown in Figure 6A, this finite impulse response filter technology reduces quantizing noise, but improves power consumption and increase Chip area, is because having multiple PFD, charge pump and frequency divider.For example, if feedback divider is used based in MMD and phase Insert the fractional divider of device, then for phase average granularity 16, can have 16 simulation MMD, 16 analog phase interpolators and 16 digital phase accumulators.In order to reduce the increase of power consumption and chip area, the embodiment of the present invention can utilize single A shared MMD is for multiple phase interpolators.

Therefore, MMD generates 4 clocks { mmd_clk_-d, mmd_clk, mmd_clk_d, mmd_clk_2d }, such as Fig. 6 C Shown by digital flip-flop (DFF) chain 660；The output of integer frequency divider 661 is by digital flip-flop (DFF) 662-665 in proper order It is sampled, the output of these DFF chains is distinctly " mmd_clk_-d ", " mmd_clk ", " mmd_clk_d " and " mmd_clk_2d ". Therefore, the delay between clock in proper order is the VCO clocks of a cycle.The input of 7th phase interpolator is connected to " mmd_clk " and " mmd_clk_d ", however the input of other phase interpolators can be selected from following clock group：{(mmd_clk_- d,mmd_clk),(mmd_clk,mmd_clk_d),(mmd_clk_d,mmd_clk_2d)}。

Fig. 7 A are the frequency divider control logic shown according to one embodiment of the invention for fractional divider.In this implementation In example, frequency divider control logic 700 may include the frequency divider control logic of any fractional divider, in addition to parametric frequency divider.In In this embodiment, " frequency dividing ratio difference " accumulator 702 is shown as the difference received between any " k " DFF chains output MCk and MC7, Referred to herein as " Delta_MCk ".

The output of accumulator 702 is shown as and " ph7<n-1:0>" be added.Integer exports " delta_mmd_k " and controls kth The multiplexer 712 of a phase interpolator 710, and signal " ph_k " controls phase interpolator 714.

The range of " delta_mmd_k " depends on corresponding integral triangle modulator input form, integral triangle modulator Structure, finite impulse response (FIR) form, parametric frequency divider and initial phase setting.Initial phase for these already described embodiments Setting can from it is different compared with the embodiment early described, be because multiple phase interpolators frequency dividing ratio difference.

For example, if the input of integral triangle modulator is to immobilize, if using the moulding (multi-stage of multistage noise Noise shaping) (MASH1-1) integral triangle modulator, if finite impulse response (FIR) (FIR) exponent number (tap) is 16, if limited Impulse response form is (z-0+z-1+z-2+ ...+z-15), possible if parametric frequency divider selects MC7 as input " delta_mmd_k " can be { -1,0 ,+1 }.In this example, if " delta_mmd_k " is " -1 ", k-th of phase interpolator Select input of the group { mmd_clk_-d, mmd_clk } as n phase interpolators 714.If " delta_mmd_k " is " 0 ", then k-th of phase interpolator selection { mmd_clk, mmd_clk_d } is as input.If " delta_mmd_k " is " 1 ", the K phase interpolator selection { mmd_clk_d, mmd_clk_2d } is as input.

Fig. 7 B and Fig. 7 C are to show used finite impulse response (FIR) leggy score point according to one embodiment of the invention The function of frequency device.The example how Figure 75 0 and one finite impulse response (FIR) leggy fractional divider of following narration descriptions can operate. In the N-1 iteration (iteration), the 7th phase interpolator may be set to 5/16 phase stepping, and it is in n-th rank 40+6/16 frequency dividing ratios are realized in section；Therefore, the frequency dividing ratio of shared common MMD is set as 40, and respective phase interpolator Phase settings be 11/16.Compared with parametric frequency divider, in the N-1 iteration, " delta_mmd_6 " is " -1 ", therefore to The input clock of 6 phase interpolators is { mmd_clk_-d, mmd_clk }, and " ph " selects for respective phase interpolator 15/16 is phase stepping.

Compare the clock of the clock and the 7th phase interpolator of the 6th phase interpolator, the difference in this example is-(- 1 + 15/16) output for -5/16)=- 6/16, also referring to accumulator (such as accumulator 702 of Fig. 7) is -6/16.It changes in n-th The frequency dividing ratio of Dai Zhong, the 6th fractional divider are 40+7/16, and the frequency dividing ratio of the 7th fractional divider is 40+6/16, therefore the Frequency dividing ratio in N number of stage is 40+7/16- (40+6/16)=+ 1/16；Therefore, the accumulator output in n-th iteration is -6/ 16++1/16=-5/16.

Furthermore in n-th iteration, the phase of the 7th frequency divider is 11/16, and the output of adder is 6/16, therefore N " delta_mmd_6 " in a iteration is " 0 ", and " ph6 " in the n-th stage is 6/16.

In a similar manner, " ph8 " is 2/16, and " delta_mmd_8 " is 1 in the N-1 iteration；Therefore, the 8th The phase difference to add up between phase interpolator and the 7th phase interpolator is 13/16.Frequency dividing ratio in the n-th stage is poor Different is -1/16, therefore accumulator output is 12/16." ph7 " in the n-th stage is 11/16, and " ph7 " and accumulator output Summation is 1+7/16.Therefore " delta_mmd_8 " in n-th iteration remains as 1, and " ph8 " in n-th iteration is 7/16.

Therefore, in above-described embodiment, group's finite impulse response (FIR) frequency divider utilizes single shared MMD.Since MMD exists High-frequency operation, therefore the example for reducing MMD can significantly decrease power consumption and the chip face of finite impulse response (FIR) fractional divider Product.

The inconsistent of phase interpolator can cause phase interpolator non-linear, therefore cause and mix attached involve in surging and increase Quantizing noise in frequency.Unfortunately, the non-linear several surgings also resulted in low frequency of phase interpolator or mixed attached wave；So And if the initial setting of the accumulator 702 of Fig. 7 A is configured, the non-linear of phase interpolator can greatly be inhibited.

Initial phase setting in this embodiment is different from other embodiment discussed above, is because being used for multiple phases The frequency dividing ratio of interpolater is different.If for example, there is 16 phase interpolators in an embodiment, frequency dividing ratio can set as follows：

(1) 40+5/16 (early stage, arrive at first)

(2)40+6/16

(3)40+5/16

(4)40+7/16

(5)40+5/16

(6)40+4/16

(7)40+5/16

(8)40+6/16

(9)40+7/16

(10)40+5/16

(11)40+5/16

(12)40+4/16

(13)40+6/16

(14)40+6/16

(15)40+5/16

(16)40+4/16

(17)40+5/16

(18)40+7/16

(19)40+5/16

(20)40+4/16

(21)40+5/16

(22)40+4/16

(23)40+5/16

(24)40+4/16

(25)40+5/16

(26) 40+4/16 (finally arriving)

If there is 16 phase interpolators, frequency dividing ratio (1) 40+5/16 can be initially set up to the 16th phase interpolator, point Frequency ratio (2) 40+6/16 can initially set up to the 15th phase interpolator ... frequency dividing ratio (16) 40+4/16 and can initially set up to the 1st A phase interpolator；Assuming that the 1st phase interpolator initial phase is set as phase 0, its meeting so in the first clock time Phase 4 is jumped to from phase 0.

In the second clock time, the 2nd phase interpolator frequency dividing ratio may be set to 40+4/16, and the 1st in the first clock The frequency dividing ratio of a phase interpolator is identical.The frequency dividing ratio of the 2nd phase interpolator may be set to (15) 40+5/ in first time 16.Initial phase may be set to phase 12.Therefore in the first clock time, the 2nd phase interpolator jumps to phase from phase 12 Position 1.In the second clock time, phase 5 is jumped to from phase 1.

For the 3rd phase interpolator, frequency dividing ratio may be set to 40+6/16 in the first clock, and 40+5/16 is when second Clock, 40+4/16 is in third clock.Therefore, initial phase may be set to：Initial phase=phase 2-(40+5/16)-(40+6/ 16)=phase 7；In the first clock, phase 13 is jumped to from phase 7；In second clock, phase is jumped to from phase 13 2…。

For the 16th phase interpolator, initial phase may be set to phase 15- (40+5/16)-(40+5/16)-(40+ 6/16)-(40+5/16)-(40+7/16)-(40+5/16)-(40+4/16)-(40+5/16)-(40+6/16)-(40+7/16)- (40+5/16)-(40+5/16)-(40+4/16)–(40+6/16)-(40+6/16)-(40+5/16)；Therefore, in the 16th clock, The frequency dividing ratio of 16th phase interpolator may be set to 40+4/16, the frequency dividing ratio phase with the 1st phase interpolator in the first clock Together, phase 3 is jumped to from phase 15.

The example of the display initial phase form of Figure 76 0 of Fig. 7 C.It is assumed that the 1st phase interpolation in the N+0 stage The phase of device is 15/16, and the frequency dividing ratio of 40+7/16 causes phase step to 6/16.By the 2nd phase interpolator of selection Appropriate initial phase, it is possible, point of 40+7/16 to make the phase of the in the N+1 stage the 2nd phase interpolator be 0/16 Frequency ratio makes the phase step of the 2nd phase interpolator to phase 7/16.In the same way, when the different phase interpolator of selection Specific initial phase setting when, to allow form of the different phase interpolators according to Figure 76 0 jump its phase be can Can.

Design in the finite impulse response filter fractional N-type phase-locked loop 600 of fractional N-type phase-locked loop such as Fig. 6 A In, limit circuit bandwidth is understood in the choice between same frequency (in-band) voltage controlled oscillator noise and trigonometric integral quantizing noise Selection.It, can when the input frequency of frequency divider is too high to allow the appropriate running of programmable frequency divider or counter Using in advance except device (pre-scalar).In advance except device by input frequency divided with fixed ratio, and therefore can in higher frequencies of operation, It is because it is not exposed to and counts and reset related delay.Further, since pre- in feedback divider can be with very except device High frequency operation, therefore more feedback dividers may occupy significant chip space area and a large amount of power of consumption.Therefore, The size and power consumption for reducing finite impulse response (FIR) feedback divider can mitigate this influence.

Fig. 8 A to Fig. 8 C are to show finite impulse response (FIR) feedback divider circuit according to one embodiment of the invention.In this reality It applies in example, the finite impulse response filter fractional N-type phase-locked loop 800 of Fig. 8 A is shown as comprising multiple phase frequency detectors (PFD) 802, charge pump 804, leggy feedback divider 806 and loop filter 808, to be filtered to quantizing noise. The output of triangular integration modulator 810 is applied to DFF chains 810, and to generate delay output, and these delays export control leggies Feedback divider 806.With Fig. 6 A on the contrary, control word group is shown as " mmd_k ", expression feedback divider is integer frequency divider, Rather than fractional divider.

Fig. 8 B are to show finite impulse response (FIR) feedback divider circuit according to one embodiment of the invention.In this embodiment In, circuit 820 includes integral triangle modulator 822, digital flip-flop (DFF) chain 824 (only drawing a part), shared multimode number Frequency divider (MMD) 826, one groups of multiplexers and control logics.As previously discussed, the output of integral triangle modulator 822 is applied to DFF chains 824, with generation " MC0 ... MC6, MC7, MC8 ... MC15 ".In this embodiment, " MC7 " is selected to control The frequency dividing ratio of MMD826.In this embodiment, without phase interpolator, more than one MMD can be used.

In this embodiment, MMD826 (that is, the 8th MMD of circuit 820), which is shown as, generates 7 clock { mmd_clk_- 3d,mmd_clk_-2d,mmd_clk_-d,mmd_clk,mmd_clk_d,mmd_clk_2d,mmd_clk_3d}.For example, as schemed Shown by the DFF chains 824 of 8C, the output of integer frequency divider 830 can be sampled by digital flip-flop (DFF) 831-837 in proper order； The output of this DFF chain can be used as those output clocks (when meaning VCO of the delay between clock in proper order for a cycle Clock).The output of 8th feedback divider (referring back to Fig. 8 B) is shown as " mmd_clk ", however the input of multiple multiplexers from this Group one clock of clock selecting.

As previously discussed, the output selection " mmd_clk " of the 8th feedback divider in this example.Such as Figure 85 0 of Fig. 8 D Shown, from the N-1 stage to N stage, MMD is set to realize 40 frequency dividing ratio.For example, it is assumed that the 6th MMD is intended to 42 frequency dividing ratio is realized from the N-1 stage to the n-th stage, if such as the 6th MMD selects " mmd_ in the N-1 stage Clk_-d " is as output, then the 6th MMD will select " mmd_clk_d " as output in the n-th stage.With same side Formula, if the 8th MMD uses " mmd_clk_d " as output in the N-1 stage, and it is in order to realize 39 frequency dividing ratio, then The 8th MMD will be used " mmd_clk " in the n-th stage.

Fig. 9 is the frequency divider control logic of frequency divider of being flashed according to one embodiment of the invention.In this example, control The controllable any frequency divider other than parametric frequency divider of logic 900 processed." frequency dividing ratio difference " accumulator 902 and MCk and MC7 Between difference (be known as " Delta_MCk ") be applied to this accumulator.The output of accumulator 902 can control multiplexer 910. The range of " delta_mmd_k " depends on integral triangle modulator input form, integral triangle modulator structure, finite impulse and rings Answer form, parametric frequency divider and initial phase setting.For example, if the input of integral triangle modulator is to immobilize, if choosing MASH1-1 integral triangle modulators are selected, if finite impulse response (FIR) (FIR) exponent number (tap) is 16, if finite impulse response (FIR) form is (z-0+z-1+z-2+ ...+z-15), if parametric frequency divider select MC7 as input, possible " delta_mmd_k " can be- 3,-2,-1,0,+1,+2,+3}.If " delta_mmd_k " is " -3 ", k-th of multiplexer select " mmd_clk_-3d " as Input.Another example is, if " delta_mmd_k " is " 0 ", k-th of multiplexer selects " mmd_clk " as input.

Figure 10 is to show the device comprising the logic using the SSC signals generated according to one embodiment of the invention or be System.In this schema, certain standards with not substantial connection of the invention and known component is not shown.In certain realities Apply in example, device or system 1000 (being generally known as device herein) comprising a bus or interconnection structure 1002 or other passing Send the means of communication of data.Device 1000 may include the processor 1004 of a processing means such as one or more, with interconnection The coupling of structure 1002 is for processing information.Processor 1004 may include the entity handles device and one or more of one or more Logic processor.Bus or interconnection structure 1002 are shown as single interconnection structure, for simplification, but can represent multiple and different Interconnection structure or bus, and so far the component linker of sample interconnection structure can be changed.Interconnection structure 1002 shown in Fig. 10 Represent the independence of any one connected by bridge appropriate (bridge), adapter (adapter) or controller or more The abstract of entity bus, point-to-point link or both.

In some embodiments, device 1000 further include random access memory (random access memory, RAM) or Other dynamic memories or component are using as main memory 1012, to store information and be intended to the instruction executed by processor 1004. Random access memory may include dynamic random access memory (DRAM, dynamic random access memory).In certain In embodiment, the memory of device can further include certain buffers or the memory of other specific purposes.

Device 1000 may include read-only memory (read only memory, ROM) 1016 or other static storage devices, To store static information and for the instruction of processor 1004.Device 1000 may include the Nonvolatile memory of one or more Component (non-volatile memory elements) 1018 to store certain components, it includes such as flash memory and hard disk or Solid state disk.

The conveyer or receiver 1020 of one or more can also be coupled to interconnection structure 1002.In some embodiments, Conveyer or receiver 1020 can be coupled to the port 1022 of one or more, can be for example comprising one or more in wherein aforementioned port The port high resolution multimedia interface (HDMITM, High-Definition Multimedia Interface), one or with On action high image quality connection the port (MHLTM, Mobile High-Definition Link), one or more DVI (Digital Visual Interface, Digital Visual Interface) port and/or its analog.

In some embodiments, device 1000 includes the input equipment 1024 of one or more, and wherein input equipment includes One or more below：Keyboard, mouse, touch tablet, phonetic order identification system, gesture identification system or other providing It is input to the device of an arithmetic system.Device 1000 can also be coupled to an output device 1026 by interconnection structure 1002.Mr. Yu In a little embodiments, such as display of output device 1026 may include liquid crystal display (LCD, liquid crystal display) Or any other display technology, to show information or content to user.In certain situations, output device 1026 may include touching Screen is controlled, is also acted as at least part of input equipment.In certain situations, output device 1026 can be or may include sound Frequency device, such as loud speaker, to provide audio-frequency information.Device 1000 also may include a supply unit or equipment 1030, can Including power supply unit, battery, solar cell, fuel cell or other providing or generate the system or device of electric power. The electric power that supply unit or equipment 1030 are provided can be distributed on demand to the component of device 1000.

Above-mentioned narration proposes several specific details to illustrate the invention, in favor of thoroughly understanding the present invention.However, will It is that for having the those skilled in the art of usual knowledge in this field, the present invention can not need certain certain details therein with the person of understanding Implement under section.In other examples, it is known that structure and device show in the form of a block diagram.Between component shown in figure There may be intermediate structure.Component described herein or shown may have additional input or output not to be shown or chatted It states.Shown component or part can also be different configuration mode or sequence configured, include the row again of any field The modification of sequence or field size.

The present invention may include different methods.The method of the present invention can be implemented by hardware component or can be embodied It is available so as to the processor of general service or special-purpose or be programmed with the logic circuit of instruction in computer-readable instruction Implement this method.It is another then, this method can be implemented by the combination of hardware and software.

It is partial the present invention can provide for computer program product, above computer program product may include computer-readable Non-instantaneous store media (computer-readable non-transitory storage medium), with computer Program instruction stores thereon, can be used to program a computer (or other electronic devices) to implement side according to the present invention Method.Computer readable storage medium may include, but are not limited to floppy disk, CD, CD-ROM (compact disk read-only Memory, CD-ROMs) and magneto-optical disk (magneto-optical disks), read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (erasable programmable read-only memory, EPROMs), It can electrically formula erase programmable read only memory (electrically-erasable programmable read-only Memory, EEPROMs), magnetical or optical property card, flash memory or it is other kinds of suitable for stored electrons instruction media/calculating Machine readable media.In addition, the present invention can also download as computer program product, Program can be sent to from remote computer into The computer that row requires.

The present invention method in it is several described in the form of its is most basic, but do not departing from the present invention basic model If can be still added under enclosing drying method to it any one or from it, if any one deletes drying method, and several information can be increased to herein Described information it is any in or from it delete several information.Those of skill in the art will be understood, can to the present invention into One step makes several changes and change.Specific embodiment mentioned herein is not limiting the present invention, and to illustrate this hair It is bright.

If describing " A " component is coupled to " B " component or coupled, A components can couple directly to B components or transmission Such as the indirect coupling of C components.When specification describe A components, feature, structure, method or characteristic " cause " B components, feature, Structure, method or characteristic, referring to " A " is " B " at least part reason, but may also have at least an other assemblies, feature, knot Structure, method or characteristic assistance cause " B ".If specification point out a component, feature, structure, method or characteristic " obtaining ", " possibility " or "available" by comprising, then the specific components, feature, structure, method or characteristic be not required for having to by comprising.If specification refers to " one " component, then its be not intended to only there are one the component.

Embodiment is the realization method or example of the present invention.Point out in the description " embodiment ", " one embodiment ", " some embodiments " or " other embodiment " refer to a particular feature, structure, or characteristic described in conjunction with the embodiments be included in Without being necessarily included in whole embodiments in some few embodiments." embodiment ", " one embodiment " or " some embodiments " Various statements not necessarily referring to identical embodiment.It should be appreciated that in the foregoing description of exemplary embodiment of the present invention, The various features of the present invention are grouped together in single embodiment, attached drawing and its description sometimes for the smoothness narration present invention And it assists in terms of understanding one or more of various novel aspects.

Claims (14)

1. a kind of phase-locked loop PLL circuit generating spread spectrum clock (SSC), including：

Multiple fractional dividers, each the multiple fractional divider include multi-modulus frequency divider (MMD) and multiple phases Interpolater (PI), wherein the multi-modulus frequency divider receives the output for carrying out voltage controlled oscillator (VCO) and generates multiple through frequency elimination Clock signal, wherein the multiple phase interpolator receives described from the multi-modulus frequency divider through frequency elimination clock signal simultaneously Export respective fractional divider output signal；And

Digital square, including integral triangle modulator, wherein integral triangle modulator output is believed to generate the first control Number integer value, for will be for the frequency dividing ratio of the multi-modulus frequency divider of each in the multiple fractional divider Identical numerical value is controlled into, and is exported to generate the score numerical value of second control signal, for selecting the multiple score point The phase of the multiple phase interpolator of each in frequency device so that each in the fractional divider output signal Average phase matching it is expected it is phase stepping.

2. PLL circuit according to claim 1, wherein the phase interpolation in each in the fractional divider The quantity of device is equal to the phase stepping denominator of the expectation.

3. PLL circuit according to claim 1, wherein the phase interpolation in each in the fractional divider The quantity of device is less than the phase stepping denominator of the expectation.

4. PLL circuit according to claim 1, wherein the integral triangle modulator of the number square includes multistage The moulding integral triangle modulator of noise.

5. PLL circuit according to claim 1, further includes：

Charge pump and loop filter are coupled between phase frequency detector and the voltage controlled oscillator, to coming from The pulse upward or downward of the phase frequency detector is filtered, and provides output signal to control the voltage controlled oscillation Device.

6. a kind of phase-locked loop PLL circuit generating spread spectrum clock (SSC), including：

Multiple fractional dividers, each in the multiple fractional divider include multi-modulus frequency divider (MMD) and more A phase interpolator (PI), wherein the multi-modulus frequency divider receives the output for carrying out voltage controlled oscillator (VCO) and generates multiple Through frequency elimination clock signal, wherein the reception of the multiple phase interpolator is described through frequency elimination clock from the multi-modulus frequency divider Signal simultaneously exports respective fractional divider output signal；And

Digital square, including integral triangle modulator, wherein integral triangle modulator output is believed to generate the first control Number integer value, for according to finite impulse response (FIR) (FIR) form control for each in the multiple fractional divider The frequency dividing ratio of the multi-modulus frequency divider, in favor of inhibiting the finite impulse response filter of the multiple phase interpolator Non-linear behavior.

7. PLL circuit according to claim 6, wherein the multimode number of each in the multiple fractional divider point Frequency device includes single multi-modulus frequency divider, and the single multi-modulus frequency divider is shared between the multiple phase interpolator.

8. PLL circuit according to claim 6, wherein the initial phase form for the multiple fractional divider is passed through Selection is to inhibit the non-linear behavior of the finite impulse response filter of the multiple phase interpolator.

9. PLL circuit according to claim 6, wherein the integral triangle modulator of the number square includes multistage The moulding integral triangle modulator of noise.

10. PLL circuit according to claim 6, further includes：

Phase frequency detector；And

Charge pump and loop filter are coupled between the phase frequency detector and the voltage controlled oscillator, to right Pulse upward or downward from the phase frequency detector is filtered, and provides output signal to control described voltage-controlled shake Swing device.

11. one kind being used for the finite pulse response FIR fractional divider of phase-locked loop (PLL) circuit, including：

Integral triangle modulator, to export modulated reference signal；

Multiple number flip-flops, to receive the output of the integral triangle modulator and generate delay output, the delay is defeated Go out comprising with reference to delay output；

Multiple multi-modulus frequency dividers, each in the multi-modulus frequency divider correspond to one in the multiple digital flip-flop A, multiple through frequency elimination signal to generate, each in the multiple signal through frequency elimination is exported corresponding to respective delay；

Multiplexer, to export one in the multiple signal through frequency elimination；And

Control logic controls to be at least partially based on seleced delay output the difference with reference between delay exports The selection of the multiplexer output.

12. FIR fractional dividers according to claim 11 further include frequency dividing ratio accumulator, to control the multiplexing The selection of device output.

13. FIR fractional dividers according to claim 11, wherein the integral triangle modulator is moulded comprising multistage noise Shape integral triangle modulator.

14. FIR fractional dividers according to claim 13, wherein the moulding integral triangle modulator of the multistage noise Input is to immobilize.