CN106531793A - Semiconductor structure with epitaxial layers - Google Patents

Semiconductor structure with epitaxial layers Download PDF

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Publication number
CN106531793A
CN106531793A CN201510577437.6A CN201510577437A CN106531793A CN 106531793 A CN106531793 A CN 106531793A CN 201510577437 A CN201510577437 A CN 201510577437A CN 106531793 A CN106531793 A CN 106531793A
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China
Prior art keywords
epitaxial layer
coronal
fin
fin structure
grid
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CN201510577437.6A
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CN106531793B (en
Inventor
许智凯
洪裕祥
傅思逸
童宇诚
郑志祥
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US14/876,844 priority patent/US9780169B2/en
Publication of CN106531793A publication Critical patent/CN106531793A/en
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a semiconductor structure with epitaxial layers. The semiconductor structure comprises a base, a plurality of first fin structures, a plurality of second fin structures, a plurality of first gate structures, a plurality of second gate structures, at least two first coronary epitaxial layers and a plurality of second epitaxial layers, wherein a first conductive pattern area and a second conductive pattern area are defined on the base; the plurality of first fin structures are located on the base and located in the first conductive pattern area; the plurality of second fin structures are located on the base and located in the second conductive pattern area; the plurality of first gate structures are located in the first conductive pattern area; the plurality of second gate structures are located in the second conductive pattern area; the at least two first coronary epitaxial layers are arranged in the first conductive pattern area; the plurality of second epitaxial layers are arranged in the second conductive pattern area; and the shapes of the second epitaxial layers are different from those of the first coronary epitaxial layers.

Description

Semiconductor structure with epitaxial layer
Technical field
The present invention relates to semiconductor applications, more particularly, to a kind of semiconductor with various different epitaxial layers Structure.
Background technology
In recent years, as field-effect transistor (field effect transistors, FETs) component size constantly contracts Little, the development of existing plane formula (planar) field effect transistor element has faced the limit in manufacture craft.For Manufacture craft is overcome to limit, with the field effect transistor element of on-plane surface (non-planar), such as fin-shaped field Effect transistor (fin field effect transistor, Fin FET) element come replace flat crystal tube elements into For current mainstream development trend.Due to the stereochemical structure of fin-shaped field-effect transistor element can increase grid with The contact area of fin structure, therefore, can further increase grid for the control in carrier pathway region, So as to reduce the drain electrode that small-sized component faces cause can band reduce (drain induced barrier lowering, DIBL) effect, it is possible to suppress short-channel effect (short channel effect, SCE).Furthermore, due to Fin-shaped field-effect transistor element can have broader channel width under same grid length, thus can obtain The drain drives electric current that must be doubled.Even, the critical voltage (threshold voltage) of transistor unit Can be regulated and controled by adjusting the work function of grid.
However, in existing fin-shaped field-effect transistor element manufacture craft, the design of fin structure is still deposited In many bottlenecks, in addition to affecting the mobility of channel region carrier, the overall electrical of element is affected again Performance.Therefore how to improve existing fin-shaped field-effect transistor manufacture craft and be an important topic now.
The content of the invention
The present invention provides a kind of semiconductor element, and comprising a substrate, definition thereon has one first conductivity Region and one second conductivity region, a plurality of first fin structure be located in the substrate and positioned at this In one conductivity region, and a plurality of second fin structure be located at it is in the substrate and second conductive positioned at this In kenel region, multiple first grid structures are located in the first conductivity region, across this plurality of the One fin structure, and multiple second grid structures are in the second conductivity region, it is many across this The second fin structure of bar, and at least two first coronal epitaxial layers, are arranged at the first conductivity region It is interior, and positioned at the both sides of the respectively first grid structure, and multiple second epitaxial layers, be arranged at this second In conductivity region, positioned at the both sides of the respectively second grid structure, the wherein first coronal epitaxial layer position In one first groove of the both sides of the first grid structure, first groove has a planar bottom surface, and Contact the plurality of first fin structure simultaneously, in addition the shape of second epitaxial layer and the first coronal extension Layer is different.
The present invention provides a kind of semiconductor element, and comprising a substrate, definition thereon has one first conductivity Region, includes a first area and a second area in the first conductivity region, and a plurality of first Fin structure is located in the substrate and is located in the first area, and a plurality of second fin structure is located at and is somebody's turn to do In substrate and in the second area, multiple first grid structures are located in the first area, across this A plurality of first fin structure, and multiple second grid structures are in the second area, it is a plurality of across this Second fin structure, and at least two first coronal epitaxial layers, are arranged in the first area, and are located at The respectively both sides of the first grid structure, and multiple second epitaxial layers, are arranged in the second area, position In the both sides of the respectively second grid structure, the wherein first coronal epitaxial layer is located at the first grid structure Both sides one first groove in, first groove has a planar bottom surface, and while contact the plurality of the One fin structure, the shape of second epitaxial layer is different from the first coronal epitaxial layer in addition.
It is a feature of the present invention that among same semiconductor structure, in different conductivity regions, Include epitaxial layer of different shapes.Or the same conductivity region of same semiconductor structure It is interior, include zones of different, and each region includes epitaxial layer of different shapes respectively.The present invention is by difference The epitaxial layer of shape is made in same semiconductor structure, can improve semiconductor structure flexible in application Property.
Description of the drawings
Fig. 1 to Fig. 6 is that the preparation method of the semiconductor structure of the first preferred embodiment of the present invention is illustrated Figure, schematic perspective views of the wherein Fig. 4 for semiconductor structure；
Fig. 7 is the semiconductor structure sectional view of second preferred embodiment of the present invention；
Fig. 8 is the semiconductor structure sectional view of the third preferred embodiment of the present invention；
Fig. 9 is the semiconductor structure sectional view of the 4th preferred embodiment of the present invention.
Main element symbol description
10 substrates
12 fin structures
13 shallow isolating troughs
14 photoresist patterns
16 grooves
20 insulating barriers
30 grid structures
32 gate dielectrics
34 grid conducting layers
36 cap layers
100 first conductivity regions
100A first areas
100B second areas
The 3rd regions of 100C
The 4th regions of 100D
112 fin structures
130 grid structures
139 mask layers
140 grooves
150 coronal epitaxial layers
The coronal epitaxial layers of 150A
152 bottom surfaces
154 top surfaces
200 second conductivity regions
212 fin structures
212 ' secondary fin structures
230 grid structures
240 epitaxial layers
240B epitaxial layer
250 tooth shape epitaxial layers
250C tooth shape epitaxial layers
252 grooves
254 upper surfaces
260 coronal epitaxial layers
The coronal epitaxial layers of 260D
A1 regions
P1 etching steps
P2 fin-shaped cutting steps
P3 selective epitaxial growth steps
P4 selective epitaxial growth steps
P5 selective epitaxial growth steps
Specific embodiment
To enable the general technology person for being familiar with the technical field of the invention to be further understood that the present invention, under Wen Te enumerates the preferred embodiments of the present invention, and coordinates appended accompanying drawing, describes the composition of the present invention in detail Content and be intended to effect reached.
For convenience of explanation, each accompanying drawing of the invention is only illustrated to be easier to understand the present invention, and which is detailed Ratio can according to design demand be adjusted.It is described in the text in figure opposed member it is upper Lower relation, for people in the art will be understood which refers to the relative position of object, therefore can Overturn and identical component is presented, this should all belong to the scope disclosed by this specification together, here appearance first chats bright.
Fig. 1 to Fig. 5 depicts the preparation method of the semiconductor structure of the first preferred embodiment of the present invention and shows It is intended to.Fig. 1 is refer to, Fig. 1 depicts semiconductor structure in the sectional view of starting stage.Such as Fig. 1 institutes Show, first, there is provided a substrate 10, in substrate 10, be provided with multiple fin structures 12.Substrate 10 is removed Outside block silicon base, above-mentioned substrate 10 also can be for example one and cover containing silicon base, an III-V semiconductor Silicon base (such as GaAs-on-silicon), a Graphene cover silicon base (graphene-on-silicon) or silicon covers Insulation (silicon-on-insulator, SOI) substrate, oxidation silicon base (silicon dioxide), calorize silicon base (aluminum oxide), sapphire substrates (sapphire), germanic (germanium) substrate or SiGe are closed The semiconductor bases such as gold substrate (alloy of silicon and germanium).
Specifically, the preparation method of fin structure 12 may include the following steps, but be not limited. For example, a bulk substrate (not illustrating) is provided first, and is formed on hard mask layer and (do not painted Show), followed by photoetching and etching process, by hard mask layer pattern, to define subsequently The position of the fin structure 12 to be correspondingly formed.Then, an etching step P1 is carried out, will be defined in hard Pattern in mask layer is transferred in bulk substrate, and the fin structure 12 needed for being formed.It is last selective Ground removes hard mask layer, just can obtain structure as shown in Figure 1.In the case, fin structure 12 Can be considered that a surface of substrate 10, and the composition that is of identical composition to each other are come from extension, for example singly Crystal silicon.On the other hand, when substrate is not selected from above-mentioned bulk substrate, but it is selected from III-V semiconductor When covering silicon base, then the main composition of fin structure can be with the III-V semiconductor group of this substrate into identical.
Next, recycling a photoresist pattern 14 as mask to carry out a fin structure cutting (fin-cut) step.As shown in Fig. 2 after fin-shaped cutting step P2, part fin structure 12 It is removed with the substrate of part and forms groove 16.In general, groove 16 be located region will again after Continuous step can be received in insulating barrier, and form such as shallow isolating trough (shallow trench isolation, STI) Insulation layer.And the active region of semiconductor element is may be defined as by 16 area encompassed A1 of groove, It is exactly the region of the elements such as the transistor that formed in subsequent step.
As shown in figure 3, after removing photoresist pattern 14, the flat insulating barrier of comprehensive formation one 20 in substrate 10, covers 10 surface of substrate and inserts in groove 16, then carries out a planarization Step and an etch-back step (not shown), to form shallow isolating trough 13.Insulating barrier 20 is, for example, oxygen The isolation material such as SiClx or silicon nitride.Additionally, formed insulating barrier 20 before, can first selectivity shape Into a laying (not shown) between substrate 10 and insulating barrier 20, here is not added to repeat.
Fig. 4 depicts the stereogram of semiconductor structure.Note that, for illustrative simplicity, Fig. 4 only draws Partial semiconductor structure.As shown in figure 4, multiple grid structures 30 are formed, on insulating barrier 20 simultaneously And be across on each fin structure 12.Wherein each grid structure 30 can include a gate dielectric 32, Grid conducting layer 34 and a cap layer 36.Wherein the material of gate dielectric 32 can include silica (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or the dielectric material comprising dielectric constant more than 4, It is selected from hafnium oxide (hafnium oxide, HfO2), hafnium silicate oxygen compound (hafnium silicon Oxide, HfSiO4), hafnium silicate nitrogen oxide (hafnium silicon oxynitride, HfSiON), oxygen Change aluminium (aluminum oxide, Al2O3), lanthana (lanthanum oxide, La2O3), tantalum oxide (tantalum oxide, Ta2O5), yittrium oxide (yttrium oxide, Y2O3), zirconium oxide (zirconium oxide, ZrO2), strontium titanates (strontium titanate oxide, SrTiO3), zirconium silicate oxygen compound (zirconium Silicon oxide, ZrSiO4), zirconic acid hafnium (hafnium zirconium oxide, HfZrO4), strontium bismuth tantalum oxygen Compound (strontium bismuth tantalate, SrBi2Ta2O9, SBT), lead zirconate titanate (lead zirconate titanate,PbZrxTi1-xO3, PZT), barium strontium (barium strontium titanate, BaxSr1-xTiO3, ), or its constituted group of combination BST.The material of grid conducting layer 34 can include unadulterated many Crystal silicon, heavily doped polysilicon, metal silicide or single or multiple lift metal level, metal level is for example Workfunction layers, barrier layer and low resistance metal layer etc..Cap layer 36 may include single layer structure or many The dielectric material of layer, such as silica (SiO), silicon nitride (SiN), carborundum (SiC), carbonitride of silicium (SiCN), silicon oxynitride (SiON) or its combination.Additionally, 30 side wall of grid structure can contain gap Wall, but in order to accompanying drawing is succinct, clearance wall is not plotted in Fig. 4.
To this step, the semiconductor structure of the present invention has formed multiple fin structures 12 in substrate On 10, and multiple grid structures 30 are formed in substrate 10, and each grid structure 30 is across at least One fin structure 12.Next in substrate, definition has at least one first conductivity region 100, and One second conductivity region 200, the first conductivity region 100 and the second conductivity region 200 Between there are shallow isolating trough.Wherein the first conductivity region 100 or the second conductivity region 200 Respectively include an at least fin structure and at least a grid structure is located therein, in order to become apparent from explanation, Fin structure 12 in the first conductivity region 100 is labeled as fin structure by paragraphs below 112, the grid structure 30 in the first conductivity region 100 is labeled as grid structure 130, position Fin structure 12 in the second conductivity region 200 is labeled as fin structure 212, leads positioned at second Grid structure 30 in electric kenel region 200 is labeled as grid structure 230, its architectural feature with it is above-mentioned Fin structure 12 and grid structure 30 are identical, and here is not repeated in addition.
Wherein, the first conductivity region 100 may be a n-type transistor region, and in subsequent step A middle formation at least n-type transistor is in the first conductivity region 100, or a p-type transistor Region, and an at least p-type transistor is formed in subsequent step in the first conductivity region 100. Similarly, the second conductivity region 200 is likely to include a n-type transistor region or a p-type Transistor area.Preferably, in subsequent step, the first conductivity region 100 and the second conductivity The transistor included in region 200, with complementary conductivity.For example, if first is conductive Kenel region 100 is a n-type transistor region, then the second conductivity region 200 is a p-type crystal Area under control domain, but not limited to this.Hereinafter sequentially introduce the epitaxial layer knot included by the semiconductor structure of the present invention Structure.
1. coronal epitaxial layer (crown epitaxial layer)：
Fig. 5～Fig. 6 is refer to, and refers to above-mentioned Fig. 3～Fig. 4 in the lump.Fig. 5～Fig. 6 is the present invention First preferred embodiment semiconductor structure sectional view.Wherein coronal epitaxial layer 150 is formed in first and leads In electric kenel region 100.Its preparation method is included and is initially formed a mask layer 139 with opening, at least The fin structure (being for example covered in the second conductivity region 200) of covering part, then carries out an erosion Step (such as ionic reaction etching etc.) is carved, the fin structure 112 of part is removed, in this step, only Have and be not removed by the part fin structure covered by grid structure 130 (refer to the stereochemical structure of Fig. 4), And the fin structure that remaining exposes to the open air is then completely removed, therefore it is recessed that at least two are formed after above-mentioned etching step Groove 140 (one of them is only drawn in Fig. 5), respectively positioned at the both sides of grid structure.Its further groove 140 With a planar bottom surface, and groove 140 exposes (or contact) multiple not removed fin structures simultaneously to the open air.
Then selective epitaxial growth (SEG) step P3 is carried out again, is preced with forming one in groove 140 Shape epitaxial layer 150, coronal epitaxial layer 150 are located at the both sides of grid structure 130.According to different embodiments, Coronal epitaxial layer 150 can include a silicon germanium extension layer, and be applied to a PMOS transistor, or coronal Epitaxial layer 150 can include a silicon carbon epitaxial layer, and be applied to a nmos pass transistor.It is familiar with the skill The personage of art is, it should be understood that when epitaxial growth step P3 is carried out, coronal epitaxial layer 150 is along groove 140 Each surface grow up, but will not grow up along surface of insulating layer.Therefore coronal epitaxial layer 150 fills up groove 140, it is preferable that coronal epitaxial layer 150 has a planar bottom surface 152 and a flat top 154, but Not limited to this.It is otherwise noted that (being located at as fin structure 112 is only located at by groove 140 Below grid structure 130), and be located at groove 140 in, although therefore coronal epitaxial layer 150 be located at By multiple fin structures 112 and the multiple fin structures 112 of directly contact, but without being covered in fin On shape structure 112.
It should be noted that coronal epitaxial layer 150 is located at the first conductivity region 100 in the present embodiment It is interior, but the invention is not restricted to this, coronal epitaxial layer 150 is likely located at other regions, falls within the present invention Covering scope in.
2. time epitaxial layer (sub-epitaxial layer)
Please continue to refer to Fig. 5～Fig. 6, and above-mentioned Fig. 3～Fig. 4 is referred in the lump.In the second area, Multiple epitaxial layers 240 are formed, it is other positioned at grid structure 230 (its position refer to Fig. 4), and be covered in On each fin structure 212.It is different from the preparation method of above-mentioned coronal epitaxial layer 150 to be, make secondary outer Prolong layer 240 and step need not be etched to remove fin structure, and can be directly to carry out a selection Property epitaxial growth (SEG) step P4, time epitaxial layer 240 is formed on each fin structure 212.According to not Same embodiment, secondary epitaxial layer 240 can include a silicon germanium extension layer, and be applied to a PMOS transistor, Or secondary epitaxial layer 240 can include a silicon carbon epitaxial layer, and be applied to a nmos pass transistor.
It should be noted that in the present embodiment, in the second conductivity region 200, due to not removing fin Shape structure 212, because this epitaxial layer 240 is covered in three surfaces of part fin structure 212 to I haven't seen you for ages, Comprising a top surface and two side.According to different embodiments, adjustment selective epitaxial growth (SEG) step The parameter (such as time etc.) of P4, may cause each epitaxial layer 240 be separated from each other or mutually Polymerization (merged) is together.Said method is well known to those skilled in the art, therefore repeats no more, but this Invention is not limited.
3. tooth shape epitaxial layer (teeth epitaxial layer)：
Fig. 7 is refer to, and refers to above-mentioned Fig. 3～Fig. 4 in the lump.Fig. 7 is that of the invention second is preferred real Apply the semiconductor structure sectional view of example.Wherein coronal epitaxial layer 150 is formed in the first conductivity region In 100.Its preparation method is identical with above-mentioned first embodiment, and here is not repeated in addition.This enforcement in addition In example, at least two tooth shape epitaxial layers 250 are formed at grid structure 230 (its position refer to Fig. 4) Side, the step of its preparation method similar shape is into coronal epitaxial layer, comprising being initially formed a mask with opening Layer (not shown), at least fin structure 212 of covering part, then carry out an etching step (such as ion Reaction etching etc.), the fin structure 212 of part is removed, in this step, (please be join by grid structure 230 Examine the stereochemical structure of Fig. 4) the part fin structure 212 that covered is not removed, and the fin that remaining exposes to the open air Shape structure is then partially removed, and forms multiple fin structures 212 ', and each fin structure 212 ' is by position Immediately below grid structure 230, removed fin structure 212 does not extend out, and secondary fin-shaped knot The height of structure 212 ' is low compared with the height of the second fin structure 212.Therefore formed after above-mentioned etching step to Few two grooves 252 (one of them is only drawn in Fig. 6), respectively positioned at the both sides of grid structure.Its concave Include multiple fin structures 212 ' in groove 252.
Then selective epitaxial growth (SEG) step P5 is carried out again, to form a tooth in groove 252 Shape epitaxial layer 250, tooth shape epitaxial layer 250 are located at the both sides of grid structure 230.According to different embodiments, Tooth shape epitaxial layer 250 can include a silicon germanium extension layer, and be applied to a PMOS transistor, or tooth shape Epitaxial layer 250 can include a silicon carbon epitaxial layer, and be applied to a nmos pass transistor.It is familiar with the skill The personage of art is, it should be understood that when epitaxial growth step P5 is carried out, tooth shape epitaxial layer 250 is along groove 252 Each surface grow up, and include multiple fin structures 212 ', therefore tooth shape epitaxial layer in groove 252 250 fill up groove 250, meanwhile, a upper surface 254 of tooth shape epitaxial layer 250 should have concavo-convex profile. Additionally, tooth shape epitaxial layer 250 is directly covered in directly over time fin structure 212 ', and tie positioned at fin-shaped By structure 212.
Fig. 8 is refer to, and refers to above-mentioned Fig. 3～Fig. 4 in the lump.Fig. 8 is that of the invention the 3rd is preferred real Apply the semiconductor structure sectional view of example.Wherein coronal epitaxial layer 150 is formed in the first conductivity region In 100.Its preparation method is identical with above-mentioned first embodiment, and here is not repeated in addition.And second is conductive Then be formed with multiple coronal epitaxial layers 260 in kenel region 200, its preparation method also with coronal epitaxial layer 150 is identical, simply in the present embodiment, by the depth for adjusting groove, coronal epitaxial layer 150 and hat Shape epitaxial layer 260 has different thickness.It is otherwise noted that the epitaxial layer of above-mentioned other shapes, Also can integrate with the present embodiment, that is, change thickness by adjusting manufacture craft parameter.For example, In one embodiment of the invention, semiconductor structure includes outside a tooth shape in a conductivity region wherein Prolong layer, then include another tooth shape extension with different-thickness in another conductivity region Layer, falls within the covering scope of the present invention.
Additionally, the various embodiments described above can also be integrated mutually, for example, in one embodiment of the invention, Semiconductor structure includes multiple epitaxial layers in a conductivity region wherein, conductive at another Then include another tooth shape epitaxial layer in kenel region.Only need to meet in same semiconductor structure, Include epitaxial layer of different shapes, belong to covering scope of the present invention.
In addition, in the various embodiments described above disclosed in same semiconductor structure in, different conductivity areas In domain, include epitaxial layer of different shapes respectively.But in the present invention, even same conduction In kenel region, it is also possible to include epitaxial layer of different shapes.Fig. 9 is refer to, which illustrates the present invention The semiconductor structure sectional view of the 4th preferred embodiment.In the present embodiment, substrate 10 still includes multiple Fin structure 12 and grid structure (Fig. 9 do not show, refer to aforementioned Fig. 4), in addition the first conductivity Also include multiple regions in region 100, such as first area 100A, second area 100B, the 3rd Region 100C and the 4th region 100D etc., are mutually separated with shallow isolating trough 13 between each region. In the present embodiment, in the 100A of first area, include at least one coronal epitaxial layer 150A, second area Include in 100B in epitaxial layer 240B, the 3rd region 100C at least one times and include at least one Then include a coronal epitaxial layer 260D in tooth shape epitaxial layer 250C, the 4th region 100D, wherein being preced with The thickness of shape epitaxial layer 260D is different from coronal epitaxial layer 150A.It is coronal outer described in the present embodiment Prolong layer, secondary epitaxial layer and tooth shape epitaxial layer etc., its architectural feature and preparation method all with above-mentioned this case Identical described in one to 3rd embodiment, here is not repeated in addition.
It should be noted that being only a wherein embodiment of the present invention shown in Fig. 9, but the invention is not restricted to This.In other embodiments of the invention, in the same conductivity region of semiconductor structure, institute The epitaxial layer shape formed in the quantity of inclusion region, or each region, can be according to enforcement demand Adjustment, the present invention are not limited.
In sum, it is a feature of the present invention that among same semiconductor structure, different conductions In kenel region, include epitaxial layer of different shapes.Or be the same of same semiconductor structure In conductivity region, include zones of different, and each region includes epitaxial layer of different shapes respectively. The present invention is made in epitaxial layer of different shapes in same semiconductor structure, can improve semiconductor structure and exist Using upper flexibility.
The foregoing is only the preferred embodiments of the present invention, all impartial changes done according to the claims in the present invention Change and modification, should all belong to the covering scope of the present invention.

Claims (20)

1. a kind of semiconductor element, comprising：
Substrate, thereon definition have one first conductivity region and one second conductivity region；
A plurality of first fin structure, in the substrate and in the first conductivity region, and A plurality of second fin structure, in the substrate and in the second conductivity region；
Multiple first grid structures, in the first conductivity region, across a plurality of first fin-shaped Structure, and multiple second grid structures, in the second conductivity region, across this plurality of Two fin structures；And
At least two first coronal epitaxial layers, are arranged in the first conductivity region, and be located at respectively this The both sides of one grid structure, and multiple second epitaxial layers, are arranged in the second conductivity region, Positioned at the both sides of the respectively second grid structure, the wherein first coronal epitaxial layer is located at the first grid structure Both sides one first groove in, first groove has a planar bottom surface, and while contact the plurality of the One fin structure, the shape of second epitaxial layer is different from the first coronal epitaxial layer in addition.
2. semiconductor element as claimed in claim 1, wherein the first conductivity region are a p-type Transistor area, the second conductivity region are a n-type transistor region.
3. semiconductor element as claimed in claim 1, wherein the first conductivity region are a N-shaped Transistor area, the second conductivity region are a p-type transistor region.
4. semiconductor element as claimed in claim 1, wherein respectively first epitaxial layer has planar bottom surface And flat top.
5. semiconductor element as claimed in claim 1, wherein respectively the first coronal epitaxial layer be located at it is multiple The side of the first fin structure, and the first coronal epitaxial layer is not directly covered in respectively first fin structure Surface.
6. semiconductor element as claimed in claim 1, wherein second epitaxial layer include multiple times it is outer Prolong structure, three surfaces of each of which time epitaxial structure across respectively second fin structure.
7. semiconductor element as claimed in claim 1, wherein second epitaxial layer include at least 1 Two coronal epitaxial layers, in two second grooves by the second grid structure, second groove has flat Smooth bottom surface, and the plurality of second fin structure of directly contact.
8. semiconductor element as claimed in claim 7, the wherein thickness of the second coronal epitaxial layer with should The thickness of the first coronal epitaxial layer is different.
9. semiconductor element as claimed in claim 7, the wherein second coronal epitaxial layer are located at multiple the The side of two fin structures, and the second coronal epitaxial layer is not directly covered in each second fin structure Surface.
10. semiconductor element as claimed in claim 1, wherein second epitaxial layer include tooth shape extension Layer, a upper surface of the tooth shape epitaxial layer include a concavo-convex profile.
The second grid of 11. semiconductor elements as claimed in claim 10, the wherein second area is tied The substrate definition of structure both sides has a plurality of fin structure, and a plurality of fin structure is by a plurality of second fin Shape structure extends out, and the height of a plurality of fin structure is compared with the height of a plurality of second fin structure Degree is low, and the tooth shape epitaxial layer is directly covered in the surface of respectively this fin structure.
A kind of 12. semiconductor elements, comprising：
Substrate, thereon definition have one first conductivity region, include in the first conductivity region First area and second area；
A plurality of first fin structure, in the substrate and in the first area, and a plurality of second Fin structure is located in the substrate and is located in the second area；
Multiple first grid structures, in the first area, across a plurality of first fin structure, with And multiple second grid structures, in the second area, across a plurality of second fin structure；And
At least two first coronal epitaxial layers, are arranged in the first area, and are located at respectively first grid knot The both sides of structure, and multiple second epitaxial layers, are arranged in the second area, positioned at the respectively second grid The both sides of structure, the wherein first coronal epitaxial layer are located at the one first of the both sides of the first grid structure In groove, first groove has a planar bottom surface, and while the plurality of first fin structure of contact, separately The shape of outer second epitaxial layer is different from the first coronal epitaxial layer.
13. semiconductor elements as claimed in claim 12, wherein the first conductivity region are a p Transistor npn npn region or a n-type transistor region.
14. semiconductor elements as claimed in claim 12, wherein respectively first epitaxial layer is flat with one Bottom surface and a flat top.
15. semiconductor elements as claimed in claim 12, wherein respectively the first coronal epitaxial layer is positioned at more The side of individual first fin structure, and the first coronal epitaxial layer is not directly covered in respectively first fin-shaped knot The surface of structure.
16. semiconductor elements as claimed in claim 12, wherein second epitaxial layer include multiple times Epitaxial structure, three surfaces of each of which time epitaxial structure across respectively second fin structure.
17. semiconductor elements as claimed in claim 12, wherein second epitaxial layer include at least one Second coronal epitaxial layer, in two second grooves by the second grid structure, second groove has Planar bottom surface, and the plurality of second fin structure of directly contact.
18. semiconductor elements as claimed in claim 17, the wherein thickness of the second coronal epitaxial layer with The thickness of the first coronal epitaxial layer is different.
19. semiconductor elements as claimed in claim 17, the wherein second coronal epitaxial layer are located at multiple The side of the second fin structure, and the second coronal epitaxial layer is not directly covered in respectively second fin structure Surface
20. semiconductor elements as claimed in claim 12, wherein second epitaxial layer comprising tooth shape outside Prolong layer, a upper surface of the tooth shape epitaxial layer includes a concavo-convex profile.
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