CN106531792A - Method for forming fin-on-insulator - Google Patents
Method for forming fin-on-insulator Download PDFInfo
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- CN106531792A CN106531792A CN201510572093.XA CN201510572093A CN106531792A CN 106531792 A CN106531792 A CN 106531792A CN 201510572093 A CN201510572093 A CN 201510572093A CN 106531792 A CN106531792 A CN 106531792A
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- fin
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- oxide
- oxidation
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- 238000000034 method Methods 0.000 title claims abstract description 84
- 239000012212 insulator Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 43
- 230000008569 process Effects 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims description 30
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 24
- 229910052760 oxygen Inorganic materials 0.000 claims description 24
- 239000001301 oxygen Substances 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 18
- 229910052732 germanium Inorganic materials 0.000 claims description 17
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 17
- 238000005516 engineering process Methods 0.000 claims description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 15
- 229910052739 hydrogen Inorganic materials 0.000 claims description 15
- 239000001257 hydrogen Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 15
- 238000009279 wet oxidation reaction Methods 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 10
- 239000012159 carrier gas Substances 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 150000002500 ions Chemical class 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 11
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 1
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910002090 carbon oxide Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001657 homoepitaxy Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000006213 oxygenation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a method for forming a fin-on-insulator. The method comprises the steps of providing a substrate, wherein fins are formed on the substrate; partially filling grooves among the fins with an oxide; forming a side wall on exposed fins; performing oxidization; and removing the side wall and an oxidization layer at the tops of the fins. The method provided by the invention employs an existing semiconductor process, the fin-on-insulator is prepared on the conventional substrate by a simple and practical mode, and the problem of current leakage between the fins and the substrate in the prior art can be effectively solved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of method for forming fin on insulator.
Background technology
With the continuous development of integrated circuit technology, the channel length of device constantly shortens, appearance
Short-channel effect causes the electric property of device constantly to deteriorate.Intel is introduced in 22nm technology nodes
The three-dimensional device architecture of fin formula field effect transistor (Fin-FET), Fin-FET is with fin channel
The transistor of structure, it by the use of several surfaces of thin fin as raceway groove, such that it is able to prevent conventional crystal
Short-channel effect in pipe, while operating current can be increased.
With the research application of Fin-FET, how to reduce substrate leakage current and increasingly become people's research
Emphasis.Generally using the method for ion implanting near interlayer dielectric layer (STI) in prior art
High bulk resistor part is formed in fin, reduces substrate leakage current, but, the high resistant that the method is formed
Partial resistance still has much room for improvement, and, damage of the ion implanting to substrate and fin is larger, and meeting
Affect device performance.Further, it is also possible to pass through to form fin on silicon (SOI) substrate on insulator, with
The fin to be formed is made to be located on insulator, it is to avoid the leakage current between fin and substrate；But, SOI substrate
Cost intensive, there is presently no large-scale use.
The content of the invention
The invention provides a kind of method for forming fin on insulator, so that solve cannot be simple in prior art
Effectively reduce the problem of substrate leakage current.
The invention provides a kind of method for forming fin on insulator, including：
Substrate is provided, on the substrate, fin is formed with；
The groove between fin is filled with oxide portions；
Side wall is formed on exposed fin；
Aoxidized；
Remove side wall and the oxide layer at the top of fin.
Preferably, the groove between the filling fin with oxide portions includes：
Groove between fin is filled with oxide；
Planarized；
Perform etching, member-retaining portion oxide is between fin.
Preferably, described to be oxidized to wet oxidation, the wet process oxidation technology includes：
The carrier gas of wet oxidation is steamed for the water for reacting generation after hydrogen and oxygen and hydrogen and oxygen mix
The volume ratio of vapour, hydrogen and oxygen is：3:2-3:1；
Oxidizing temperature is 850-1200 DEG C.
Preferably, the substrate include it is following any one：Silicon substrate, germanium substrate, silicon-Germanium substrate.
Preferably, methods described also includes：
After side wall is formed on exposed fin, oxide described in etched portions, with expose portion fin.
Preferably, methods described also includes：
After removing side wall and the oxide layer at the top of fin, extension is carried out.
Preferably, the extension include it is following any one：Germanium, SiGe, iii v compound semiconductor
Material and its lamination.
Preferably, the oxidation includes：
Carry out O +ion implanted；
Carry out thermal annealing.
A kind of method of fin on formation insulator, it is characterised in that include：
Substrate is provided, on the substrate, fin is formed with；
Side wall is formed on fin；
Aoxidized；
Remove side wall and the oxide layer at the top of fin.
Preferably, the substrate is germanium substrate.
Preferably, described to be oxidized to wet oxidation, the wet process oxidation technology includes：
The carrier gas of wet oxidation is steamed for the water for reacting generation after hydrogen and oxygen and hydrogen and oxygen mix
The volume ratio of vapour, hydrogen and oxygen is：3:2-3:1；
Oxidizing temperature is 850-1200 DEG C.
Preferably, methods described also includes：
After removing side wall and the oxide layer at the top of fin, extension is carried out.
The invention provides a kind of method for forming fin on insulator, the method includes：Use oxide portions
The groove between established fin is filled, and then side wall is formed to protect in side wall on exposed fin
Fin, is then aoxidized so that not by the fin of side wall protection in the oxide and oxidation technology filled
In the presence of, insulator is oxidized to, it is final to remove side wall and the oxide layer at the top of fin, form exhausted
Fin on edge body.As the method that the present invention is provided adopts existing semiconductor technology, with the side of simple possible
Formula prepares fin on insulator in general substrate, in energy effectively solving prior art between fin and substrate
Leakage problem.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present application or technical scheme of the prior art, below will be to implementing
Accompanying drawing to be used needed for example is briefly described, it should be apparent that, drawings in the following description are only
Some embodiments described in the present invention, for those of ordinary skill in the art, can be with according to these
Accompanying drawing obtains other accompanying drawings.
Figure 1A to Fig. 1 D is a kind of cross section structure schematic diagram of Fin preparation process in prior art；
Fig. 2 is the cross section structure schematic diagram of another kind Fin in prior art；
Fig. 3 is the flow chart of the method according to formation Fin provided in an embodiment of the present invention；
Fig. 4 A to Fig. 4 E are the process for forming Fin on insulator provided according to the embodiment of the present invention one
Cross section structure schematic diagram；
Fig. 5 A to Fig. 5 D are the process for forming Fin on insulator provided according to the embodiment of the present invention two
Cross section structure schematic diagram；
Fig. 6 A to Fig. 6 C are the process for forming Fin on insulator provided according to the embodiment of the present invention three
Cross section structure schematic diagram.
Specific embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, its
In from start to finish same or similar label represent same or similar element or have same or like work(
The element of energy.It is exemplary below with reference to the embodiment of Description of Drawings, is only used for explaining this
It is bright, and be not construed as limiting the claims.
Additionally, the present invention can in different examples repeat reference numerals and/or letter.This repetition is
For purposes of simplicity and clarity, between itself not indicating discussed various embodiments and/or arranging
Relation.Additionally, the invention provides various specific technique and material example, but this area
Those of ordinary skill can be appreciated that the applicable property of other techniques and/or the use of other materials.Separately
Outward, fisrt feature described below second feature it " on " structure can be including first and second special
Levy the embodiment for being formed as directly contact, it is also possible to first and second are formed in including other feature special
Embodiment between levying, such first and second feature may not be directly contact.
For a better understanding of the present invention, first below to preparing fin (Fin) and interlayer in prior art
The process of dielectric layer (STI) carries out brief introduction, mainly includes：First, perform etching to form Fin, such as
Shown in Figure 1A；Filling SiO2Dielectric material simultaneously carries out chemical-mechanical planarization (CMP), such as Figure 1B institutes
Show；Then, corrode certain thickness SiO using HF2Dielectric material, member-retaining portion SiO2Medium material
Material so as to form STI, as shown in Figure 1 C, then carries out ion implanting with close between Fin
High bulk resistor part is formed in the fin of STI, reduces substrate leakage current, as shown in figure ip, in figure
Round dot is ion to be implanted, and arrow represents ion motion direction.Further, it is also possible to by insulation
The method of fin is prepared to reduce substrate leakage current on silicon (SOI) substrate on body, with reference to shown in Fig. 2.
The method of Fin, the part between the fin on substrate on a kind of formation insulator that the present invention is provided
Fill oxide, then on the fin being exposed to outside STI forms side wall, is then aoxidized, by
The fin in which can be protected not oxidized in side wall, and be oxidized the fin point of thing parcel, oxide with
Be oxidized under the collective effect of oxidation technology, insulated part is formed to prevent the electric leakage between fin and substrate,
The process is described in detail below with reference to specific embodiment, with reference to Fig. 3 to Fig. 4
It is shown.
In the present invention, the substrate 100 is Semiconductor substrate, such as：Si substrates, Ge substrates, SiGe
Substrate.The oxidation can be wet oxidation, dry oxidation, O +ion implanted oxidation etc..Need
Bright, the order of oxidation technology and oxidation technology in whole technological process can be according to practical application
Demand and effect are adjusted.
Embodiment one
In the present embodiment, the substrate 100 is silicon substrate, and the material of fin 101 is silicon.A kind of shape
Into on insulator, the method for fin includes：
Step S01, there is provided substrate 100, is formed with fin 101 on the substrate 100, such as Fig. 4 A institutes
Show.
In the present embodiment, the fin 101 on the substrate 100 can pass through double-pattern imaging technique
Obtain, concrete steps include：
A mask layer (not shown) is formed on substrate；Formed on the mask layer and schemed for the first time
Shape (not shown), the first time figure are used for forming first time side wall 102；Perform etching, shape
Into first time figure in above-mentioned mask layer, and remove all layers on mask layer；In first time figure
Surrounding forms first time side wall 102, and removes first time figure；With first time side wall 102 as mask
Perform etching, form fin 101.As shown in Figure 4 A, wherein, it is described to be formed around first time figure
First time side wall 102, and remove first time figure and can include：Deposit another mask layer；Done
Method is etched, to form first time side wall 102；Remove first time figure.
Wherein, the mask layer can be hard mask, for example：By chemical vapour deposition technique (CVD)
Silicon nitride film, silicon oxide film and its lamination, amorphous carbon layer Deng formation etc.；For forming the
The photoresist layer (not shown) of figure can be the photoresist layer and anti-reflective formed by spin-coating method
Penetrate layer etc..
In a specific embodiment, by strengthening plasma chemical vapor deposition on substrate
(PECVD) cvd silicon dioxide film, then using photoetching process, etching technics etc. in titanium dioxide
First time figure is formed on silicon thin film, then, by the cvd nitride silicon thin film such as PECVD, so
After carry out dry etching to form first time side wall 102 around the first time figure, then, with first
Secondary side wall 102 carries out dry etching for mask, until it reaches remove first time side wall 102 after designated depth,
Fin 101 is formed on the substrate 100.Additionally, in actual applications, in addition it is also necessary to first time side wall 102
It is modified, to remove unnecessary connection figure, will not be described in detail herein.
It should be noted that a photoetching process and etching technics can also be passed through certainly in substrate 100
Upper formation fin 101, but the method is difficult to prepare small size fin, for example, fin of the width less than 20nm.
Step S02, fills the groove between fin 101 with oxide portions, as shown in Figure 4 B.
In the present embodiment, the groove between the filling fin 101 with oxide portions includes：With oxygen
Groove between compound filling fin；Planarized；Perform etching, member-retaining portion oxide is in fin 101
Between.
Wherein, the oxide is used for forming interlayer dielectric layer (ILD) 103, for example, SiO2, phosphorus
Silica glass (PSG), boron-phosphorosilicate glass (BPSG) etc. by chemical vapour deposition technique (CVD),
The techniques such as spin coating insulating medium layer (SOD), HARP are realized.Further, it is also possible to be that composition is oxygen
The low-k dielectric layer of compound, for example, carbon oxide (Carbon Doped Oxide, CDO), to drop
Impact of parasitic capacitance C between low circuit layer to RC retardation ratio.The planarization can by anti-carving,
The methods such as chemical-mechanical planarization (CMP) are forming smooth substrate surface.
In a specific embodiment, the groove between fin 101 is filled by SOD, is then carried out
CMP, until exposure fin 101, then using the solution containing hydrofluoric acid, such as BOE etching fins 101
Between oxide, and member-retaining portion oxide is between fin 101, to expose the fin of Partial Height.
Step S03, forms side wall 104, as shown in Figure 4 C on exposed fin 101.
In the present embodiment, the material of the material needs and fin 101 of the side wall 104 has larger
Selective etching ratio, meanwhile, to also have larger selection to carve with the oxide being filled between fin 101
Erosion ratio, in order to not injure fin 101 and the STI 103 for being formed during follow-up removal side wall 104.
In a specific embodiment, the side wall 104 that formed on exposed fin includes：Pass through
PECVD cvd nitride silicon thin film on the substrate that step S02 is obtained, for example, reacting gas is
SiH2Cl2And NH3Flow-rate ratio be 1/5～1/10, and NH3Flow for 1L/min to 5L/min
Under the conditions of reaction form silicon nitride film；Then fin 101 is removed by reactive ion etching (RIE)
Silicon nitride film between top and fin 101, to form side wall 104 on fin 101.
Step S04, is aoxidized, as shown in Figure 4 D.
In the present embodiment, by oxidation step, to form insulating barrier in the bottom of fin 101.Pass through
On the insulator that oxidation step is formed, fin 101 is passed through similar to the fin 101 formed using SOI substrate
Leakage problem between the insulating barrier energy effectively solving fin 101 of formation and substrate 100.
Specifically, it is described to be oxidized to wet oxidation, including：Using hydrogen and oxygen and hydrogen and oxygen
The water vapour for reacting generation after gas mixing is 3 as the volume ratio of carrier gas, hydrogen and oxygen:2-3:1；Oxygen
It is 850-1200 DEG C, depending on oxidization time is according to concrete oxidation effectiveness, for example, oxidization time to change temperature
Determined according to the critical size CD of Fin, CD bigger oxidization time is longer, specifically, during oxidation
Between can be calculated according to the oxidation rate of 0.3～0.5nm/min, it should be noted that in order to ensure oxidation
Effect, the oxidization time of usual actual set can be more than calculated oxidization time, for example, actual
The oxidization time of setting is actual than calculated oxidation more 10 minutes.Additionally, in actual applications,
Self-inspection can be carried out after this oxidation step, for example, to accompanying the test of piece or design in Cutting Road
Pattern detected, if it find that threshold value of the leakage current between fin and substrate more than setting, then basis
Actually measured leakage current value is aoxidized again to substrate.
It should be noted that in the oxidizing process, fin 101 is not only affected by wet process oxidation technology,
Also affected by the oxide being filled between fin 101 simultaneously, in pyroprocess, in oxide
Oxygen diffused in the form of ion in fin 101, at high temperature with pasc reaction generate silica；Together
When, the oxygen element that the oxygen in outside atmosphere is also lost in oxide is supplemented.In order to reach preferable oxygen
Change effect, for example, for width is the fin of 22nm, in order to the fin for ensureing ILD parcels has divided
Oxidized, oxidizing temperature is 1000 DEG C, and oxidization time is 90min.
Step S05, removes side wall 104 and the oxide layer at the top of fin 101, as shown in Figure 4 E.
In the present embodiment, remove what is be oxidized at the top of side wall 104 and fin 101 by wet etching etc.
Part.
Specifically, the silicon nitride film on the wall of fin side is removed by hot phosphoric acid etc., then by hydrofluoric acid
Deng the oxide layer removed at the top of fin 101.
In embodiments of the present invention, form side wall 104 to protect in side wall around exposed fin 101
Fin 101 do not affected by subsequent step, and the oxide by being filled between fin 101 and oxidation
Technique so that insulating barrier is formed on 101 bottom of fin, to prevent the electric leakage between fin 101 and substrate 100
Stream.The method that the present invention is provided adopts existing semiconductor technology, forms similar in common silicon substrate
The fin formed in SOI substrate, effectively solves leakage current between fin of the prior art and substrate
Problem, improve device performance.
Embodiment two
A kind of method of fin on formation insulator, as described in embodiment one, except that, in this reality
Apply in example, the material of the fin 101 is germanium；By removing false fin 105 on part and/or whole silicon substrates
Afterwards, fin-shaped germanium layer is obtained using epitaxy；After side wall 104 is formed on fin 101, etched portions
The fin 101 that the STI 103 of thickness is covered by STI with exposed portion.
On a kind of formation insulator, the method for fin includes：
Step S11, there is provided substrate 100, is formed with fin 101 on the substrate 100.
In the present embodiment, the substrate 100 is silicon substrate, and the fin 101 on the substrate 100 can
To be obtained by epitaxy technique, concrete steps include：
First, perform etching, form false fin 105 on a silicon substrate；Then, fill SiO2Medium material
Expect and carry out chemical-mechanical planarization (CMP), so as to form STI 103；Then, by selective etching
The false fin 105 of Partial Height is removed, to form groove 106, as shown in Figure 5A；Finally, by outer
Epitaxial growth forms fin 101 on false fin 105.
Wherein, the extension can be homoepitaxy or hetero-epitaxy, in the present embodiment, described outer
Prolong as hetero-epitaxy, epitaxial layer is germanium-silicon layer.Certainly, the epitaxial layer can also be germanium layer, here
It is not construed as limiting.
Step S12, fills the groove between fin 101 with oxide portions；And step S13：Naked
Side wall 104 is formed on the fin 101 of dew, with embodiment one, be will not be described in detail herein.It should be noted that
Step S12 can be omitted, directly using the STI 103 formed in step S01.
Step S14, oxide described in etched portions, with expose portion fin 101.As shown in Figure 5 B.
In the present embodiment, after forming side wall 104 in step s 13, the filling of etched portions thickness
Silica between fin 101, with expose portion fin.Wherein, the solution pair of etching silicon dioxide
The selective etching ratio of silica and side wall 104 (such as silicon nitride) is very big, in etching process,
Side wall 104 is not interfered with.The height of the fin protected by side wall 104 can accurately be adjusted by the step,
For example, after STI 103 are formed, it is found that the height of exposure fin outside will than the height of predetermined fin
It is little, can accurately be adjusted by the step, exposed part fin can be carried out by subsequent oxidation process
Oxidation, forms insulator.
Step S15, is aoxidized, as shown in Figure 5 C.
In the present embodiment, can be by the method such as wet oxidation or ion implanting at the bottom of fin 101
Portion forms oxide layer.
In a specific embodiment, oxide layer, for example, ion implanting are formed by ion implantation
Using injection method twice, carried out with identical injection technology on the two sides of fin 101 respectively.Wherein, institute
The implanted dopant for stating ion implanting is oxygen, and corresponding process conditions are：Implantation dosage is 1E14cm-2, note
Enter energy for 5KeV, implant angle is perpendicular to 30 ° of fin direction.Then thermal annealing is carried out, so that
The impurity of injection is reacted completely with germanium, forms oxide, and wherein, the temperature of the thermal annealing is more than 850 DEG C,
Oxidization time refers to the wet oxidation time.Certainly, the oxidation can also be wet oxidation, pass through
After high-temperature oxydation, annealing steps, oxide layer is formed in the bottom of fin 101.
It should be noted that due to defining side wall 104 on the outside of the fin that need not inject in the present embodiment,
Can not affected by ion implanting with the fin of effective protection non-exposed.Also, as etching can be passed through
STI adjusts the height of exposed fin, and the region of energy precise control ion implanting is reduced in prior art
Ion implanted regions uncontrollable factor.
Step S16, removes side wall 104 and the oxide layer at the top of fin 101, as shown in Figure 5 D.Together
Embodiment one, will not be described in detail herein.
Embodiment three
A kind of method of fin 101 on formation insulator, as described in embodiment one, except that,
In the present embodiment, the substrate 100 is germanium；The direct shape around fin 101 after fin 101 is formed
Fill oxide between fin 101 is not used in into side wall 104；In the removal side wall 104 and fin
Extension is carried out after oxide layer at the top of 101.
Step S21, there is provided substrate 100, is formed with fin 101 on the substrate 100.
In the present embodiment, the substrate 100 is germanium substrate, as germanium material and silicon materials have one
Different characteristics：Silicon materials can form one layer of fine and close oxide layer on surface, and the oxide layer can be protected under which
Silicon be no longer oxidized, germanium material is easier to obtain the deeper oxide layer of oxidation depth.Shape in germanium substrate
Process into fin 101 is no longer described in detail with embodiment one.
It should be noted that after fin is formed with first time side wall 102 as mask etching substrate, not going
Except first time side wall 102, (the first time side wall 102 during a kind of formation fin of reference implementation example, such as schemes
Shown in 4A), in follow-up oxidizing process, the first time side wall 102 protects the top of fin 101 not
It is oxidized.
Step S22, forms side wall 104, as shown in Figure 6A on fin 101.Wherein, done
In method etching process, need to control etch period, after ensureing to form side wall 104, fin 101 is pushed up
The first time side wall 102 in portion is not completely removed.
Step S23, is aoxidized, as shown in Figure 6B.
In the present embodiment, due to the germanium substrate for adopting, it is easier to obtain thicker on 100 surface of substrate
Germanium oxide layer, and using the germanium oxide layer as STI 103.For example, noted using wet oxidation or ion
Enter to coordinate thermal anneal process to form thicker germanium oxide layer on 100 surface of substrate, and using the layer as STI
103.Wherein, the carrier gas of wet oxidation, carrier gas ratio, oxidizing temperature reference implementation example one, here is not
Describe in detail again.Certainly, oxidation rate of the different materials in different carrier gas atmosphere can be different, corresponding oxygen
The change time will be adjusted, actual oxidation rate of the specific oxidization time according to germanium in oxidizing process
Depending on, the method for oxidization time is calculated with embodiment one.
Step S24, removes side wall 104 and the oxide layer at the top of fin 101.
In the present embodiment, as the first time side wall 102 at the top of fin 101 is affected by dry etching,
Differ in oxidizing process surely completely protect fin top it is not oxidized, in order to ensure the performance of device,
Etched portions height fin 101.
Step S25, carries out epitaxial growth, with reference to shown in Fig. 6 C.
In the present embodiment, in order to adjust carrier mobility or protect fin 101 not exposed in air
In, epitaxial growth can be carried out, for example：By metal-organic chemical vapor deposition equipment (MOCVD)
Or molecular beam epitaxy (MBE) is in 101 Epitaxial growth III-V compound semiconductor material of fin, silicon
Material etc..
In embodiments of the present invention, due to the method by the groove between fin 101 in, partly fill out
Oxygenation compound, then on exposed fin forms side wall 104 to protect fin 101, then passes through oxidation
Technique causes 101 bottom of fin to form an oxide layer, to solve what is leaked electricity between fin 101 and substrate 100
Problem.The method adopts semiconductor technology commonly used in the prior art and substrate, makes in this fashion for clarity
It is standby go out insulator on fin 101, the problem leaked electricity between effective fin 101 and substrate 100.
Although the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.Appoint
What those of ordinary skill in the art, under without departing from technical solution of the present invention ambit, all can profit
Many possible variations are made to technical solution of the present invention with the methods and techniques content of the disclosure above and are repaiied
Decorations, or the Equivalent embodiments for being revised as equivalent variations.Therefore, it is every without departing from technical solution of the present invention
Content, according to the present invention technical spirit to any simple modification made for any of the above embodiments, equivalent
Change and modification, still fall within the range of technical solution of the present invention protection.
Claims (12)
1. it is a kind of formed insulator on fin method, it is characterised in that include：
Substrate is provided, on the substrate, fin is formed with；
The groove between fin is filled with oxide portions；
Side wall is formed on exposed fin；
Aoxidized；
Remove side wall and the oxide layer at the top of fin.
2. method according to claim 1, it is characterised in that described to be filled with oxide portions
Groove between fin includes：
Groove between fin is filled with oxide；
Planarized；
Perform etching, member-retaining portion oxide is between fin.
3. method according to claim 1, it is characterised in that described to be oxidized to wet oxidation,
The wet process oxidation technology includes：
The carrier gas of wet oxidation is steamed for the water for reacting generation after hydrogen and oxygen and hydrogen and oxygen mix
The volume ratio of vapour, hydrogen and oxygen is：3:2-3:1；
Oxidizing temperature is 850-1200 DEG C.
4. method according to claim 1, it is characterised in that the substrate include it is following arbitrarily
It is a kind of：Silicon substrate, germanium substrate, silicon-Germanium substrate.
5. the method according to any one of Claims 1-4, it is characterised in that methods described is also
Including：
After side wall is formed on exposed fin, oxide described in etched portions, with expose portion fin.
6. the method according to any one of Claims 1-4, it is characterised in that methods described is also
Including：
After removing side wall and the oxide layer at the top of fin, extension is carried out.
7. method according to claim 6, it is characterised in that the extension include it is following arbitrarily
It is a kind of：Germanium, SiGe, III-V compound semiconductor material and its lamination.
8. method according to claim 5, it is characterised in that the oxidation includes：
Carry out O +ion implanted；
Carry out thermal annealing.
9. it is a kind of formed insulator on fin method, it is characterised in that include：
Substrate is provided, on the substrate, fin is formed with；
Side wall is formed on fin；
Aoxidized；
Remove side wall and the oxide layer at the top of fin.
10. method according to claim 9, it is characterised in that the substrate is germanium substrate.
11. methods according to claim 9, it is characterised in that described to be oxidized to wet oxidation,
The wet process oxidation technology includes：
The carrier gas of wet oxidation is steamed for the water for reacting generation after hydrogen and oxygen and hydrogen and oxygen mix
The volume ratio of vapour, hydrogen and oxygen is：3:2-3:1；
Oxidizing temperature is 850-1200 DEG C.
12. methods according to any one of claim 9 to 11, it is characterised in that methods described
Also include：
After removing side wall and the oxide layer at the top of fin, extension is carried out.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109473478A (en) * | 2017-09-07 | 2019-03-15 | 格芯公司 | More fin height with dielectric isolation |
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