CN106531690B - Method for forming lightly doped drain region - Google Patents

Method for forming lightly doped drain region Download PDF

Info

Publication number
CN106531690B
CN106531690B CN201611178623.3A CN201611178623A CN106531690B CN 106531690 B CN106531690 B CN 106531690B CN 201611178623 A CN201611178623 A CN 201611178623A CN 106531690 B CN106531690 B CN 106531690B
Authority
CN
China
Prior art keywords
region
drain region
gate
lightly doped
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201611178623.3A
Other languages
Chinese (zh)
Other versions
CN106531690A (en
Inventor
姚兰
周俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan Xinxin Integrated Circuit Co ltd
Original Assignee
Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan Xinxin Semiconductor Manufacturing Co Ltd filed Critical Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority to CN201611178623.3A priority Critical patent/CN106531690B/en
Publication of CN106531690A publication Critical patent/CN106531690A/en
Application granted granted Critical
Publication of CN106531690B publication Critical patent/CN106531690B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to the technical field of semiconductor design and manufacture, in particular to a method for forming a lightly doped drain region.

Description

Method for forming lightly doped drain region
Technical Field
The invention relates to the technical field of semiconductor design and manufacture, in particular to a method for forming a lightly doped drain region.
Background
In a semiconductor process, a plurality of devices are usually formed on a wafer, and different gate oxide thicknesses of different devices have different requirements for implantation of a Lightly Doped Drain (LDD).
At present, the process methods for realizing different doping concentrations of the LDD regions of each device are to use a photomask to cover other devices after the gate of each device is formed, so as to perform the implantation of a specific device to form the LDD region, then use the photomask to cover other devices, and perform the selective implantation in such a cycle, thereby realizing the implantation of different doses for the LDD regions of each device.
Although the method of separately performing selective implantation can accurately control the doping concentration of the LDD region of each device, the process is complex, the steps are multiple, the number of layers of the adopted photomask is large, and the production cost is high.
Disclosure of Invention
In view of the above technical problems, the present invention provides a method for forming a lightly doped drain region, which can simplify the process and reduce the production cost.
The main technical scheme for solving the technical problems is as follows:
a method for forming a lightly doped drain region comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first device area and a second device area;
defining a first gate region and first source drain regions positioned on two sides of the first gate region on the first device region, and defining a second gate region and second source drain regions positioned on two sides of the second gate region on the second device region;
forming a first gate oxide layer with a first thickness on the first source drain region and the second gate region, and forming a second gate oxide layer with a second thickness on the second source drain region and the first gate region;
forming a first gate above the first gate region and a second gate above the second gate region; and
and carrying out ion implantation with uniform dosage on the first source drain region and the second source drain region so as to form a first lightly doped drain region with first doping concentration in the first source drain region and form a second lightly doped drain region with second doping concentration in the second source drain region.
In the method for forming the lightly doped drain region, a first thickness of the first gate oxide layer is greater than a second thickness of the second gate oxide layer, and a first doping concentration of the first lightly doped drain region is less than a second doping concentration of the second lightly doped drain region.
In the method for forming the lightly doped drain region, a first thickness of the first gate oxide layer is smaller than a second thickness of the second gate oxide layer, and a first doping concentration of the first lightly doped drain region is greater than a second doping concentration of the second lightly doped drain region.
In the method for forming the lightly doped drain region, the first device region and the second device region are isolated by a shallow trench.
In the method for forming the lightly doped drain region, the shallow trench is filled with an insulator.
In the method for forming the lightly doped drain region, the semiconductor substrate is a silicon substrate.
In the method for forming the lightly doped drain region, the semiconductor substrate is a P-type silicon substrate.
The technical scheme has the following advantages or beneficial effects:
the invention simplifies the process steps from the angle of process integration, forms gate oxide layers with different thicknesses in the source and drain regions of different device regions by utilizing the blocking characteristic of the gate oxide layer to ion implantation, adopts a uniform implantation mode for LDD regions with different dosage energy requirements, and achieves the effect of differential implantation by blocking the implantation by the gate oxide layers with different thicknesses in the source and drain regions, thereby realizing the selective implantation of the LDD regions, reducing the times of photomask and implantation and lowering the production cost.
Drawings
Embodiments of the present invention will be described more fully with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
Fig. 1 is a flow chart of a method of forming lightly doped drain regions of the present invention;
fig. 2 to 5 are structural diagrams corresponding to steps of a method for forming a lightly doped drain region in an embodiment.
Detailed Description
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
It should be noted that the technical solutions and the technical features in the technical solutions described below can be combined with each other without conflict.
Referring to the flowchart of fig. 1 and the structure diagrams of fig. 2 to 5, the method for forming Lightly Doped Drain (LDD) regions of the present embodiment mainly includes the following steps:
first, as shown in fig. 2, a semiconductor substrate 1 including a first device region 11 and a second device region 12 is provided. Fig. 2 illustrates only two device regions, and in actual production, a plurality of device regions may be formed on the semiconductor substrate 1 as needed. Between the first device region 11 and the second device region 12, isolation is performed by a shallow trench 13. The shallow trench 13 may be filled with an insulator to realize insulation between the first device region 11 and the second device region 12, so as to ensure that devices in the two device regions do not affect each other. The semiconductor substrate 1 may be a silicon substrate, such as a wafer, and the first device region 11 and the second device region 12 are two device regions on the wafer. Of course, other auxiliary films, such as an epitaxial layer, are disposed on the wafer, and therefore, the auxiliary films do not substantially affect the method for forming the lightly doped drain region of the present invention and are not included in the invention point of the present invention, and therefore, the discussion of the auxiliary films is omitted here.
Next, as shown in fig. 3, a first gate region 22 and first source-drain regions 21 located at two sides of the first gate region 22 are defined on the first device region 11 (including a first source region and a first drain region located at two sides of the first gate region 22, which are collectively denoted as the first source-drain regions 21 in the figure); and, defining a second gate region 24 and second source-drain regions 23 located at two sides of the second gate region 24 (including a second source region and a second drain region respectively located at two sides of the second gate region 24, which are collectively referred to as the second source-drain regions 23 in the figure) on the second device region 12.
Then, with continued reference to fig. 3, a first gate oxide layer having a first thickness is formed on the first source-drain regions 21 and the second gate region 24, and then a second gate oxide layer having a second thickness is formed on the second source-drain regions 23 and the first gate region 22. It should be noted that, in the present embodiment, two device regions (i.e., the first device region 11 and the second device region 12) are included on the semiconductor substrate 1 for illustration, so that the formation of the gate oxide layer is divided into two steps (i.e., first forming a first gate oxide layer with a first thickness covering the first source/drain region 21 and the second gate region 24, and then forming a second gate oxide layer with a second thickness covering the second source/drain region 23 and the first gate region 22), that is, the formation of the gate oxide layers with different thicknesses on the first source/drain region 21 and the second source/drain region 23 can be realized, and a barrier layer basis with different thicknesses is laid for the subsequent ion implantation. If a plurality of device regions are formed on the semiconductor substrate 1, the deposition of the gate oxide layer can be performed by a combination step between different device regions to form a gate oxide layer of a specific thickness in each device region in accordance with the process requirements.
In addition to the above technical solution, as a preferred embodiment, the value of the first thickness is greater than the value of the second thickness, for example, the value of the first thickness is twice as large as the second thickness.
Further, as shown in fig. 4, the first gate 3 is formed above the first gate region 22, and the second gate 4 is formed above the second gate region 24.
After the first gate 3 and the second gate 4 are formed, referring to fig. 5, ion implantation with uniform dose is performed on the first source drain region 21 and the second source drain region 23 to form a first lightly doped drain region 5 in the first source drain region 21 and a second lightly doped drain region 6 in the second source drain region 23.
On the basis of the above technical solution, as a preferred embodiment, in the step shown in fig. 3, since the value of the first thickness of the first gate oxide layer above the first source drain region 21 is greater than the value of the second thickness of the second gate oxide layer above the second source drain region 23, for example, the value of the first thickness is twice the second thickness, the doping concentration of the first lightly doped drain region 5 formed in this step through ion implantation with uniform dose is less than the doping concentration of the second lightly doped region 6, and specifically, the doping concentration of the first lightly doped drain region 5 is half of the doping concentration of the second lightly doped region 6. Different doping concentrations are formed under the condition of ion implantation with uniform dosage because the gate oxide layers with different thicknesses have different blocking degrees on the ion implantation, the first gate oxide layer above the first source drain region 21 is thicker, the blocking effect is better during the ion implantation, and the doping concentration of the formed first lightly doped drain region 5 is small; and the second gate oxide layer above the second source drain region 23 is thin, so that the blocking effect is poor during ion implantation, and the doping concentration of the formed second lightly doped drain region 6 is high.
Of course, as another preferred embodiment, the first thickness may also be formed to a value smaller than the second thickness, that is, the first thickness of the first gate oxide layer above the first source drain region 21 is smaller than the second thickness of the second gate oxide layer above the second source drain region 23. Thus, when ion implantation is carried out, the blocking effect of the first gate oxide layer above the thinner first source drain region 21 is poorer, and the doping concentration of the formed first lightly doped drain region 5 is large; and the blocking effect of the second gate oxide layer above the thicker second source drain region 23 is better, so that the doping concentration of the formed second lightly doped drain region 6 is small.
In this embodiment, by using the principle that different thicknesses of gate oxide layers have different blocking effects when forming LDD regions, when a plurality of device regions are provided on a semiconductor substrate, gate oxide layers with different thicknesses are formed on the respective device regions, and the LDD regions with different doping concentrations meeting process requirements can be formed in different device regions by using the effect difference of the gate oxide layers with different thicknesses on ion implantation. And the gate oxide layer is a necessary step before forming the gate, so the method of the embodiment realizes the selective injection effect of the LDD region on the premise of not additionally increasing the steps, is simple and easy to implement and greatly saves the process cost.
In summary, the invention simplifies the process steps from the perspective of process integration, forms gate oxide layers with different thicknesses in different device regions by utilizing the blocking characteristic of the gate oxide layer to ion implantation, adopts a uniform implantation mode for LDD regions with different dosage energy requirements, and achieves the effect of differential implantation by blocking the implantation by the gate oxide layers with different thicknesses in the source and drain regions, thereby realizing the selective implantation of the LDD region, reducing the times of photomask and implantation, and reducing the production cost.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (7)

1. A method for forming a lightly doped drain region is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first device area and a second device area;
defining a first gate region and first source drain regions positioned on two sides of the first gate region on the first device region, and defining a second gate region and second source drain regions positioned on two sides of the second gate region on the second device region;
simultaneously forming a first gate oxide layer with a first thickness on the first source drain region and the second gate region, and simultaneously forming a second gate oxide layer with a second thickness on the second source drain region and the first gate region;
forming a first gate above the first gate region and a second gate above the second gate region; and
and carrying out ion implantation with uniform dosage on the first source drain region and the second source drain region so as to form a first lightly doped drain region with first doping concentration in the first source drain region and form a second lightly doped drain region with second doping concentration in the second source drain region.
2. The forming method of claim 1,
the first thickness of the first gate oxide layer is larger than the second thickness of the second gate oxide layer, and the first doping concentration of the first lightly doped drain region is smaller than the second doping concentration of the second lightly doped drain region.
3. The forming method of claim 1,
the first thickness of the first gate oxide layer is smaller than the second thickness of the second gate oxide layer, and the first doping concentration of the first lightly doped drain region is larger than the second doping concentration of the second lightly doped drain region.
4. The method of forming of claim 1, in which the first device region and the second device region are separated by a shallow trench.
5. The method of forming of claim 4 wherein the shallow trenches are filled with an insulator.
6. The method of forming of claim 1, wherein the semiconductor substrate is a silicon substrate.
7. The forming method of claim 6, wherein the semiconductor substrate is a P-type silicon substrate.
CN201611178623.3A 2016-12-19 2016-12-19 Method for forming lightly doped drain region Active CN106531690B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201611178623.3A CN106531690B (en) 2016-12-19 2016-12-19 Method for forming lightly doped drain region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611178623.3A CN106531690B (en) 2016-12-19 2016-12-19 Method for forming lightly doped drain region

Publications (2)

Publication Number Publication Date
CN106531690A CN106531690A (en) 2017-03-22
CN106531690B true CN106531690B (en) 2020-03-10

Family

ID=58339589

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611178623.3A Active CN106531690B (en) 2016-12-19 2016-12-19 Method for forming lightly doped drain region

Country Status (1)

Country Link
CN (1) CN106531690B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1913163A (en) * 2005-08-13 2007-02-14 三星电子株式会社 Thin film transistor substrate and method of manufacturing the same
CN101399288A (en) * 2008-10-23 2009-04-01 北京时代民芯科技有限公司 LDMOS chip light doped drift region structure and forming method
CN104167391A (en) * 2014-08-11 2014-11-26 矽力杰半导体技术(杭州)有限公司 Method for manufacturing CMOS structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100721553B1 (en) * 2004-06-30 2007-05-23 삼성에스디아이 주식회사 fabrication method of CMOS TFT and CMOS TFT fabricated using the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1913163A (en) * 2005-08-13 2007-02-14 三星电子株式会社 Thin film transistor substrate and method of manufacturing the same
CN101399288A (en) * 2008-10-23 2009-04-01 北京时代民芯科技有限公司 LDMOS chip light doped drift region structure and forming method
CN104167391A (en) * 2014-08-11 2014-11-26 矽力杰半导体技术(杭州)有限公司 Method for manufacturing CMOS structure

Also Published As

Publication number Publication date
CN106531690A (en) 2017-03-22

Similar Documents

Publication Publication Date Title
US9947785B2 (en) Junction field effect transistor and manufacturing method therefor
US9281393B2 (en) Super junction semiconductor device and associated fabrication method
US8704300B1 (en) Semiconductor device and fabricating method thereof
US9054129B1 (en) Semiconductor device and method for manufacturing the same
US10453921B2 (en) Semiconductor structure and fabrication method thereof
US10128244B2 (en) CMOS devices having charged punch-through stopper layer to reduce punch-through and methods of manufacturing the same
CN108666219A (en) Semiconductor devices and forming method thereof
CN104900652B (en) A kind of low-temperature polycrystalline silicon transistor array base palte and preparation method thereof, display device
CN105428241A (en) Manufacturing method of trench gate power device with shield grid
US8723256B1 (en) Semiconductor device and fabricating method thereof
CN103578996A (en) Method for manufacturing transistor
CN104332499B (en) A kind of forming method of VDMOS device and its terminal structure
US10205026B2 (en) Thin film transistor having a composite metal gate layer
CN102637600B (en) Preparation method of MOS (metal oxide semiconductor) device
CN104183500A (en) Method for forming ion-implantation side wall protection layer on FinFET device
CN106531690B (en) Method for forming lightly doped drain region
CN104637814B (en) A kind of fin formula field effect transistor and preparation method thereof
CN106033727A (en) Manufacturing method of field effect transistor
US10644103B2 (en) Semiconductor devices having charged punch-through stopper layer to reduce punch-through and methods of manufacturing the same
CN104992943A (en) Manufacturing technique method of SONOS memory
CN113299753A (en) Shielded gate trench field effect transistor structure and preparation method thereof
CN103579317A (en) Gate structure and manufacturing method
CN103165453B (en) High dielectric metal gate MOS and manufacture method thereof
CN105870021A (en) Fabrication method of metal oxide semiconductor transistor
CN105023831B (en) The manufacturing method of polysilicon resistance in CMOS technology

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP03 Change of name, title or address

Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province

Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd.

Country or region after: China

Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province

Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd.

Country or region before: China

CP03 Change of name, title or address