CN1065167A - Run-length-limited code length-undefined modulating demodulating method and realization circuit thereof - Google Patents
Run-length-limited code length-undefined modulating demodulating method and realization circuit thereof Download PDFInfo
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- CN1065167A CN1065167A CN 91101683 CN91101683A CN1065167A CN 1065167 A CN1065167 A CN 1065167A CN 91101683 CN91101683 CN 91101683 CN 91101683 A CN91101683 A CN 91101683A CN 1065167 A CN1065167 A CN 1065167A
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Abstract
A kind of run-length-limited code length-undefined modulating demodulating method and realization circuit thereof belong to digital signal processing technique field.The present invention proposes a kind of new random length modulation-demo-demodulation method, by the Data Control input figure place and the decoding of this input, and the automatic time delay output that translates sign indicating number of realization different length.According to this method, the present invention designs the modulation that is used for (2,7) sign indicating number and realizes circuit.Only need a plurality of d type flip flops and logic gates to constitute, link is simple, realize easily, and can be continuously, at a high speed, real-time working.Can be widely used in computer communication and the storing process.
Description
The invention belongs to digital signal processing technique field, particularly relate to the modulation-demodulation technique of binary digital signal.
The modulation and demodulation technology of binary digital signal is widely used in transmission, reception and the storage of digital signal and reads in the process, to reduce the error code that digital signal produces in these processes, improve the reliability of transfer of data, access, particularly important in computer communication and storing process.Usually the coded system that adopts is coding efficiency (d, k) length limit sign indicating number preferably, promptly between per two " 1 " number of " 0 " be restricted, its minimum must not be less than the lower limit d of coding, at most can not be more than the upper limit k of coding.In this sign indicating number, because the brigade commander of (2,7) sign indicating number coding back serial data is more even, the error rate is low, and the code length behind its coding is the integral multiple (2 times) of code length before the coding, be convenient to the input and output Coordination Treatment, thereby be applied to more in the computer peripheral equipment, particularly in massage storage-optical digital disk memory.
Adopt modulation, the demodulation method of length limit sign indicating number generally basic as decoding with a byte length (being generally 8) at present, this is owing to computer transmission, computing etc. generally are unit with the byte.Adopt modulation, the demodulation method of this whole byte, because the length of each decoding fixes, strong, the sequential of job step rule is easy to design in implementation procedure.But because (d, k) code length of length limit sign indicating number is not isometric in code table, for example (2,7) sign indicating number, its true form code length has two, three, four different lengths, as shown in table 1, therefore the data of any one octet can not be just with the representation in the code table, promptly in fixed word length (for example 8) decoding, can not only translate the N bit code, and must consider result's (factors such as content of remaining bit state and next byte start bit) of last decoding with N position amount of information, as shown in Figure 1, thereby in decoding, no matter be the memory mapped method, or logic gate method, the input information position of its decoding is a lot, the decoder architecture complexity.Fixed cycle is long more, and its structure is huge more, and output is to the delay time of input long more (behind the word bit of the regular length of promptly must being totally lost, could begin decoding).By several pieces of patent documentations that Patent Office of the People's Republic of China's literature department retrieves, US-A-4,841,299, US-A-4,618,846, US-A-4,881,075, US-A-4876,541, EP-A2-0,231,736, its method all belongs to the fixedly method of code length modulation, though implementation is different, common weak point is that complex structure, application are dumb, has limited application.For overcoming the deficiency of said method, United States Patent (USP) (US-A-3,689,899) has been described a kind of modulation-demo-demodulation method of not regular length decoding.Its main contents are: at first serial shift is imported the laggard row decoding of W bit code (W is the figure place of maximum length code in the code table), if wherein contain a N bit code (looking into) in the code table from highest order, then export a M bit code corresponding (M is the figure place of N bit code corresponding sign indicating number in code table) with it, and neglect the remaining thereafter sign indicating number of having imported (being the W-N position), write down the true form length N simultaneously, and decipher length M, and it is sent into input respectively, in carry-out bit numerical control system register and the converter.Before deciphering next time, answer the figure place of serial shift input with control output register output figure place and input register.When the figure place of input once more equals N, and after having exported the M position, decoder begins to translate next yard.The figure place of input equals the length of a sign indicating number before each decoding.
Though the described modulation-demo-demodulation method in United States Patent (USP) ' 899 is more progressive to some extent than the modulator approach of fixing code length, but when realizing that elongated degree is deciphered, adopted the length of the input code that translated last time to control the input figure place of this decoding, the carry-out bit figure place of each decoding also will be controlled with the output code length of current decoding.Therefore, realize the method, need add several counters, as the control of input and output figure place, in decoder, to be provided with simultaneously can represent to import, enough mode bits of output code length.For example, be the long code table in W position for maximum length code, insert the binary system of counter and will put the N position at least, N need satisfy 2
N〉=W+1.Owing to adopted a plurality of counters that load, thereby also must the many sequencing control links of affix, these factors increase the link of decoder and whole modulation, demodulator circuit, complex timeization, and make the maximum speed of circuit working be restricted.
The present invention is intended to the weak point at above-mentioned modulation-demo-demodulation method, proposes a kind of new non-whole byte modulation-demo-demodulation method, and achieving circuit, simpler and more direct rationally decoder architecture is simple, and sequential control circuit is simplified, and is easy to improve coding rate.
The indefinite length modulation-demo-demodulation method that the present invention proposes may further comprise the steps: the Data Position complete " 1 " that 1) will import serial/parallel transducer; 2) serial shift input data, and the decoder Enable Pin is opened, after importing the K position, begin decoding (K is that the shortest figure place of true form subtracts 1 code table), if the sign indicating number that meets code table is arranged, then translate corresponding with it sign indicating number, translate the state bit code of expression code length simultaneously, if input data and code table are inconsistent, then continue input next bit data, up to translating sign indicating number; 3) open delay controller, receive the decode results and the state bit code of said decoder output, the buffering amount of delay of the output register of packing into is deciphered in control according to the state bit code; 4) but the parallel/serial transducer that loads with step-by-step as said output register, by the position of control loading data, realize automatic time delay output; 5) more said serial/parallel transducer is put " 1 " entirely, prepare to receive next sign indicating number.In this method, the buffering amount of delay is set at M-N and claps, and wherein M is that the position of the maximum length code in the code table is long, and N is that the position of said decoding is long.Because being uneven in length of true form, decoding, for realizing the continuous duty of decoding, can choose different inputs, the output clock, input clock frequency promptly is set equals to import code length (true form) and the ratio of exporting code length (decoding), as shown in Figure 2 with the ratio of exporting clock frequency.
Adopt this on-fixed code length modulation-demo-demodulation method of the present invention, the figure place of each decoder input is no longer controlled by the result of decoding last time, but self is controlled by the sign indicating number of this input, need not to keep with counter the state of decoding.During decoder output, mode bit with this decoding is controlled amount of delay automatically, and needn't be with the figure place of counter records output, this is for (d, k) length limit sign indicating number, because the kind (state) of code length number is much smaller than the length (figure place) of decoding, so the decoder capacity is significantly reduced, simple in structure.The present invention can tie up to according to the long pass, position of input code in the code table and decoding to import and export and adopt different clock frequencies because sequential is simple, realizes modulation work continuous, real-time, high speed.This method link that the present invention proposes is simple, be easy to realize, can be widely used in computer communication and the storage process.
Serve as that decoding illustrates modulation-demo-demodulation method of the present invention now with (2,7).Its standard code table such as table 1, at first before each decoding, input register is put " 1 " entirely, true form is from low level serial shift input register, decoder can be held unlatching, begins decoding after importing second, then translates corresponding with it (2,7) sign indicating number (if short code, then high-order polishing " 1 "), translate the state bit code of expression code length simultaneously, for the modulation of (2,7) sign indicating number, the true form code length has only three state (promptly 2,3,4), and actual decoding table is shown in table 3,4.Again with the input register set, prepare decoding next time when packing decode results into output register.Decode results is packed into automatically by the buffering amount of delay of mode bit control and is exported behind the output register, and back output is clapped in promptly former two bit codes (10,11) time-delay two, and back output is clapped in three bit codes (010,011,000) time-delay one, the directly output of then need not delaying time of four bit codes.As can be seen from Table 1, when modulation, (2,7) sign indicating number is the longest is 8 bit codes, and promptly minimum 2 perseverances of all yards are zero, needn't export, utilize these two as the state bit code,, only need 2 bit codes can represent (01 because of the true form state has only three kinds, 10,11), thus when modulation decoder in fact input be four, be output as 8, as shown in table 3, this is very easily realized by logic gate array.Because carry-out bit is 2 times of the input position, it is 2 times that import that clock can be designed to export, to realize input, output continuous operation.
Table 1 is (2,7) sign indicating number standard code table
Table 2 is used (2, the 7) sign indicating number of the present invention and the code table of mode bit
Table 3 is the modulation decoding table of (2,7) sign indicating number of the present invention's use
Table 4 is the demodulation coding table of (2,7) sign indicating number of the present invention's use
Fig. 1 is the decoding relation when putting in order the byte modulation.
The modulation/demodulation methods flow chart that Fig. 2 proposes for the present invention
Fig. 3 is the realization circuit theory diagrams of modulation/demodulation methods of the present invention.
Fig. 4 is a kind of embodiment of realization circuit of the present invention.
The realization circuit theory of modulation-demo-demodulation method of the present invention is by the serial/parallel transducer that can give reset or " 1 ", former code decoder, and the parallel/serial transducer that can load by turn, and four parts of state decoder form, as shown in Figure 3.Wherein, said serial/parallel transducer is provided with the M+K position, and (M is the longest figure place in the input code table, K subtracts 1 figure place for the shortest figure place in the input code table), said parallel/serial transducer is provided with N position (N is the longest figure place that translates in the code table), they can be respectively be made of M+K and N d type flip flop, and remainder all can be realized by gate.In conjunction with the accompanying drawings, its operation principle state chat as follows: before decoding input, in serial/parallel transducer, from high position K position reset, all the other figure place sets, the input data are under the control of input clock, enter serial/parallel transducer by turn, former code decoder begins decoding during from input K+1 position, and decoder is exported two groups of data, one group of result (Q for decoding
N-1... Q
0), another group is the mode bit (S of expression code length
I-1... S
0, wherein i is the kind of code length, i satisfies 2
i〉=M=1), state bit code (S
I-1... S
0) as control signal, work as S
I-1=...=S
0=Q
N-1=...=Q
0=0, the sign indicating number in the sufficient code table then with thumb down does not allow decoder output, and requires to continue the input data, works as S
I-1... S
0Be not 0 o'clock entirely, then the sign indicating number in the code table has been satisfied in expression, then translates corresponding sign indicating number, Q
N-1... Q
0, will import the set again of serial/parallel transducer simultaneously, can begin decoding input next time.The parallel/serial transducer that load controlled position is as output register, state bit code S
I-1... S
0As Load Signal, control translates the " loaded " position and the figure place of sign indicating number.For example, for a r bit code,, control parallel/serial transducer and only load the r position, and be contained in apart from highest order D by state decoder
N-1The distance of position be on the position of N-r like this, after N-r claps, just export the r bit code that this is translated.Thereby realized need not the automatic time delay output of counter.
A kind of most preferred embodiment of the realization circuit that the present invention is above-mentioned is the realization circuit of (2,7) sign indicating number modulation, is described in detail as follows in conjunction with the accompanying drawings as shown in Figure 4: five d type flip flops constitute said giving and put serial/parallel transducer, wherein D
0, D
1, D
2, D
3As input data register, another D
4With the cascade of input data register, allow control end as decoding.Said former code decoder is realized actual decoding table shown in the table 3 by gate, promptly since in the table last two perseverances in eight decodings of (2,7) sign indicating number be zero, needn't take the input position of decoder, only need the first six digits decode results Q of former decoder
2～Q
1Directly the input with the parallel/serial transducer of output links to each other, and minimum two perseverances of exporting parallel/serial transducer connect " 0 " and can realize.Two output of all the other of former decoder B, A translates the state bit code in the table 3 as mode bit.The parallel/serial transducer of said output is by 8 d type flip flop (Q
0～Q
7) form as the output register that can independently load.
The workflow of this realization circuit is as follows: when each decoding begins, import five d type flip flops of serial/parallel transducer and be set to 00111, the input data are in the position input of input clock control next bit, two clap the back serial/parallel defeated parallel operation of input becomes 111 * * (* * be two bit data of input), at this moment the 5th of serial/parallel transducer becomes 1(and starts at from low level), make former code decoder allow end EN effectively promptly to begin decoding.This moment, then translating sign indicating number was 0100 if the input two bits be " 10 ", mode bit B, A becomes " 01 " from " 00 ", through or make the D that imports serial/parallel transducer behind the door
4, D
3Clear terminal CLR is effective, D
2, D
1, D
0Set terminal DR is effective, is about to input register and is changed to 00111, restarts decoding, makes low four Q of the parallel/serial transducer of output simultaneously
0, Q
1, Q
2, Q
3Loading control end LD effective, even 0100 be loaded into low four.Because B=0,, promptly clap and 0100 export after exporting clocks by the Q8 serial through four so through with invalid behind the door, exporting high four, to load control ends invalid.This moment is not if the two bits of input satisfies code table, do not have to translate sign indicating number, and state decoder does not still load and gives for " 00 " puts the work of grade, imports serial/parallel transducer and continues to receive the 3rd, and the 4th data are imported, up to translating sign indicating number.When three of inputs when satisfying code table, mode bit decoder BA=10 then will export low 6 loads new data of parallel/serial transducer, promptly through 2 clap the output clocks after, output is deciphered.When being input as four bit codes, BA=11 by 8 whole loading datas of the parallel/serial transducer of output, at this moment, need not delay time, and promptly goes out Q
7Serial output data.Because the feature of (2,7) sign indicating number as can be known, basic true form is 1: 2 with the ratio of (2,7) code data figure place, and it is the twice of input clock frequency that present embodiment is provided with the output clock frequency, and to guarantee input, the time of exporting same sign indicating number is identical, realizes continuous duty.
Claims (6)
1, a kind of brigade commander limits the indefinite length modulation-demo-demodulation method of sign indicating number, it is characterized in that may further comprise the steps:
1) will import the Data Position complete " 1 " of serial/parallel transducer;
2) serial shift input data, and the decoder Enable Pin is opened, after importing the K position, begin decoding (K is that the shortest figure place of true form subtracts 1 code table), if the sign indicating number that meets code table is arranged, then translate corresponding with it sign indicating number, translate the state bit code of expression code length simultaneously, if input data and code table are inconsistent, then continue input next bit data, up to translating sign indicating number;
3) open delay controller, receive the decode results and the state bit code of said decoder output, the buffering amount of delay of the output register of packing into is deciphered in control according to the state bit code;
4) but the parallel/serial transducer that loads with step-by-step as said output register, by the position of control loading data, realize automatic time delay output;
5) more said serial/parallel transducer is put " 1 " entirely, prepare to receive next sign indicating number.
2, modulation/demodulation methods as claimed in claim 1 is characterized in that said buffering amount of delay is set at M-N and claps, and wherein M is that the position of the maximum length code in the code table is long, and N is that the position of said decoding is long.
3, modulation-demo-demodulation method as claimed in claim 1 or 2 is characterized in that also comprising that the input clock frequency and the ratio of output clock frequency equal to import code length and the ratio of exporting code length.
4, the realization circuit of modulation-demo-demodulation method as claimed in claim 1, by the serial/parallel transducer that gives reset or " 1 ", former code decoder, the parallel/serial transducer that can adorn by turn, and four parts of state decoder are formed, it is characterized in that, said serial/parallel transducer is provided with the M+K position, and (M is the longest figure place in the input code table, K subtracts 1 figure place for the shortest figure place in the input code table), said parallel/serial transducer is provided with N position (N is the longest figure place that translates in the code table), they are made of M+K and N d type flip flop respectively, and remainder all can be realized by gate.
5, realization circuit as claimed in claim 4 is characterized in that constituting said giving by five d type flip flops puts serial/parallel transducer, wherein D
0, D
1, D
2, D
3As input data register, another D
4With the cascade of input data register, allow control end as decoding.Said former code decoder realized by gate, wherein the first six digits decode results Q of said former decoder
2～Q
7Directly the input with the parallel/serial transducer of output links to each other, minimum two perseverances of exporting parallel/serial transducer connect " 0 " and can realize, two output of all the other of former decoder B, and A is as mode bit, translate the state bit code, said parallel/serial output translator is by 8 d type flip flop (Q
0～Q
7) form as the output register that can independently load.
6, realization circuit as claimed in claim 5 is characterized in that also comprising that it is the twice of input clock frequency that the output clock frequency is set.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 91101683 CN1065167A (en) | 1991-03-21 | 1991-03-21 | Run-length-limited code length-undefined modulating demodulating method and realization circuit thereof |
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|---|---|---|---|
| CN 91101683 CN1065167A (en) | 1991-03-21 | 1991-03-21 | Run-length-limited code length-undefined modulating demodulating method and realization circuit thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104050119A (en) * | 2013-03-15 | 2014-09-17 | 英特尔公司 | Crosstalk aware encoding for a data bus |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104050119A (en) * | 2013-03-15 | 2014-09-17 | 英特尔公司 | Crosstalk aware encoding for a data bus |
| CN104050119B (en) * | 2013-03-15 | 2017-06-20 | 英特尔公司 | For the decoding of the consideration crosstalk of data/address bus |
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