CN106502959B - The structure and system in package, pcb board of master chip and Beidou chip shared drive - Google Patents
The structure and system in package, pcb board of master chip and Beidou chip shared drive Download PDFInfo
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- CN106502959B CN106502959B CN201611006059.7A CN201611006059A CN106502959B CN 106502959 B CN106502959 B CN 106502959B CN 201611006059 A CN201611006059 A CN 201611006059A CN 106502959 B CN106502959 B CN 106502959B
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- chip
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
Abstract
The invention discloses the structures and system in package, pcb board of a kind of master chip and Beidou chip shared drive, including master chip, Beidou chip and flash chip, master chip is equipped with flash controller, chip select terminal, the chip select terminal of flash controller of Beidou chip are connected with the input terminal of arbitration unit, the output end of arbitration unit is connected with flash chip, and the control terminal of data selector and data distributor is connected with the second output terminal of arbitration unit；The output end of Beidou chip and flash controller is connected with data selector；First output end of data distributor is connected with Beidou chip, and the second output terminal of data distributor is connected with flash controller；The output end of data selector, the input terminal of data distributor are connected with flash chip.The present invention realizes master chip and Beidou chip shares flash chip, and package dimension is small, packaging cost and testing cost are low；Occupy that pcb board area is small, pcb board low manufacture cost；Functional reliability and highly-safe.
Description
Technical field
The present invention is more particularly directed to the structures and system in package, pcb board of a kind of master chip and Beidou chip shared drive.
Background technique
With the progress of encapsulation technology, different chip dies, such as master chip bare die and Beidou chip dies are encapsulated in one
It rises, is a kind of common technological means, technology abbreviation SiP(System in package, system in package).System-level envelope
Dress technology can be effectively reduced chip and apply entirety BOM(Bill of Materials, bill of materials) cost.
After master chip bare die and Beidou chip dies are carried out system in package, master chip and Beidou chip are respectively necessary for
Flash chip stores corresponding startup program, upgrade procedure, application program, needs data to be saved etc. in program operation process.
Existing way is a flash chip to be equipped with to master chip and Beidou chip, therefore need two flash chips altogether.
Existing way has the following deficiencies:
First, if above-mentioned two flash chip bare dies and master chip bare die, Beidou chip dies done together system-level
Encapsulation, since there are two flash chips, package dimension is larger, and packaging cost and testing cost are higher.
Second, if not doing system-level envelope together to above-mentioned two flash chips and master chip bare die, Beidou chip dies
Dress, but two flash chips, the system in package comprising Beidou chip and master chip are placed in pcb board (Printed simultaneously
Circuit Board, printed circuit board) on, since there are two flash chips, more printed circuit plate suqares can be occupied,
Lead to printed circuit board cost increase.
Third, Beidou chip need to complete positioning function, storage location information and pass location information by communication interface
Master chip is given, and location information is very sensitive and crucial information, due to not considering Beidou chip in the prior art
Safety issue in use, therefore generated in the startup program of Beidou chip, upgrade procedure, program operation process
Data are easy to be distorted by hacker, to influence the reliability and safety of location information.
Summary of the invention
In the prior art, master chip and Beidou chip are equipped with a flash chip, and size is big after encapsulation, packaging cost
With testing cost height；Occupancy pcb board area is big, pcb board cost of manufacture is high；Beidou chip operation reliability and safety are low.This
The purpose of invention is, in view of the above shortcomings of the prior art, provides the structure of a kind of master chip and Beidou chip shared drive
And system in package, pcb board, only it need to be equipped with a flash chip, package dimension is small, packaging cost and testing cost are low；It occupies
Pcb board area is small, pcb board low manufacture cost；Beidou chip operation reliability and highly-safe.
In order to solve the above technical problems, the technical scheme adopted by the invention is that:
A kind of structure of master chip and Beidou chip shared drive, including master chip, Beidou chip and flash chip, it is described
Master chip is equipped with arbitration unit, flash controller, data selector and data distributor；The chip select terminal of Beidou chip, flash memory
The chip select terminal of controller is connected with the input terminal of arbitration unit, and the first output end of arbitration unit is connected with flash chip, number
It is connected with the second output terminal of arbitration unit according to the control terminal of selector, the control terminal of data distributor；Beidou chip it is defeated
Outlet is connected with the first input end of data selector, the second input terminal phase of the output end and data selector of flash controller
Even；First output end of data distributor is connected with Beidou chip, the second output terminal of data distributor and flash controller
Input terminal is connected；The output end of data selector, the input terminal of data distributor are connected with flash chip.
By above structure, it is responsible for by arbitration unit to the chip selection signal from Beidou chip and from flash memory in master chip
The chip selection signal of controller is arbitrated, and determines to be enjoyed by Beidou chip or master chip to sudden strain of a muscle within the period according to arbitration result
Deposit the access control power of chip, at the same export chip selection signal to flash chip, output arbitration useful signal to data selector and
Data distributor.After flash chip receives the chip selection signal from arbitration unit, it can judge that this access control is
Issued by master chip or had the sending of Beidou chip.If Beidou chip enjoys the access control power to flash chip, list is arbitrated
Member selects the first input end of data selector for effective input terminal by arbitrating useful signal, while arbitration unit passes through arbitration
Useful signal selects the first output end of data distributor for effective output end, to realize visit of the Beidou chip to flash chip
Ask control.If master chip enjoys the access control power to flash chip, arbitration unit selects data by arbitration useful signal
Second input terminal of selector is effective input terminal, while arbitration unit selects the of data distributor by arbitration useful signal
Two output ends are effective output end, to realize master chip to the access control of flash chip.As it can be seen that in the present invention, master chip
A flash chip is shared with Beidou chip.For flash chip, flash chip (for example capacity of a general large capacity
Be 16 Mbytes) than two capacity of price there was only high-capacity flash memory chip 1/2(for example capacity be 8 Mbytes) price it
With it is low.Therefore, master chip and Beidou chip, which share flash chip, can reduce production cost.
It further, further include the flash content verification unit being connected with flash controller on the master chip.
By above structure, in master chip electrifying startup and after possessing to the access control power of flash chip, Ke Yitong
Flash content verification unit is crossed to the content (liter including data integrity, master chip and Beidou chip stored on flash chip
The data for needing to write flash chip in grade program, master chip and Beidou chip operational process) it is digitally signed verification inspection
It looks into, to ensure the safety of data on flash chip, improves the safety of Beidou chip in the process of running.
It is defeated to be equipped with the first chip-select pin, the first output pin and first for the Beidou chip as a preferred method,
Enter pin, the master chip is equipped with the second input pin, third input pin, the second output pin, the second chip-select pin, the
Three output pins, the 4th input pin, the flash chip are equipped with third chip-select pin, the 5th input pin and the 4th output
Pin；First chip-select pin is connected by the second input pin with the first input end of arbitration unit, flash controller
Chip select terminal is connected with the second input terminal of arbitration unit, and the first output end of arbitration unit passes through the second chip-select pin and third piece
Pin is selected to be connected；First output pin passes sequentially through third input pin, data selector, third output pin and the 5th input
Pin is connected, and the 4th output pin passes sequentially through the 4th input pin, data distributor, the second output pin and the first input pipe
Foot is connected.
Based on the same inventive concept, the present invention also provides a kind of system in package, including the master chip and north
The structure of bucket chip shared drive, the master chip is together with Beidou chip package.
Further, the master chip, Beidou chip and flash chip are packaged together.
Based on the same inventive concept, the present invention also provides a kind of pcb boards, including the system in package.
The cost using flash chip can be reduced, system is reduced due to there was only a flash chip by above structure
The cost of grade encapsulation or printed circuit board.
Compared with prior art, the present invention realizes master chip and Beidou chip shares flash chip, only needs to be equipped with
One flash chip, package dimension is small, packaging cost and testing cost are low；Occupy that pcb board area is small, pcb board low manufacture cost；
Beidou chip operation reliability and highly-safe.
Detailed description of the invention
Fig. 1 is the schematic diagram of master chip of the present invention and Beidou chip shared drive structure.
Wherein, 1 is master chip, and 2 be Beidou chip, and 3 be flash chip, and 4 be the first chip-select pin, and 5 be the first efferent duct
Foot, 6 be the first input pin, and 7 be the second input pin, and 8 be third input pin, and 9 be the second output pin, and 10 be flash memory control
Device processed, 11 be flash content verification unit, and 12 be arbitration unit, and 13 be the second chip-select pin, and 14 be third output pin, and 15 are
4th input pin, 16 be data selector, and 17 be data distributor, and 18 be third chip-select pin, and 19 be the 5th input pin,
20 be the 4th output pin.
Specific embodiment
As shown in Figure 1, the structure of master chip 1 and 2 shared drive of Beidou chip includes master chip 1, Beidou chip 2 and flash memory
Chip 3, the master chip 1 are equipped with arbitration unit 12, flash controller 10, data selector 16 and data distributor 17；North
Chip select terminal, the chip select terminal of flash controller 10 of bucket chip 2 are connected with the input terminal of arbitration unit 12, and the of arbitration unit 12
One output end is connected with flash chip 3, and the control terminal of data selector 16, the control terminal of data distributor 17 are and arbitration unit
12 second output terminal is connected；The output end of Beidou chip 2 is connected with the first input end of data selector, flash controller 10
Output end be connected with the second input terminal of data selector；First output end of data distributor 17 is connected with Beidou chip 2,
The second output terminal of data distributor 17 is connected with the input terminal of flash controller 10；The output end of data selector, data point
The input terminal of orchestration 17 is connected with flash chip 3.
Wherein, 3 bare die of flash chip includes but is not limited to serial NOR flash memory, serial nand flash memory, parallel nand flash memory.
It further include the flash content verification unit 11 being connected with flash controller 10 on the master chip 1.
The Beidou chip 2 is equipped with the first chip-select pin 4, the first output pin 5 and the first input pin 6, the master
Chip 1 is equipped with the second input pin 7, third input pin 8, the second output pin 9, the second chip-select pin 13, third output
Pin 14, the 4th input pin 15, the flash chip 3 are equipped with third chip-select pin 18, the 5th input pin 19 and the 4th
Output pin 20；First chip-select pin 4 is connected by the second input pin 7 with the first input end of arbitration unit 12, is dodged
The chip select terminal of memory controller 10 is connected with the second input terminal of arbitration unit 12, and the first output end of arbitration unit 12 passes through second
Chip-select pin 13 is connected with third chip-select pin 18；First output pin 5 passes sequentially through third input pin 8, data selector
16, third output pin 14 is connected with the 5th input pin 19, and the 4th output pin 20 passes sequentially through the 4th input pin 15, number
It is connected according to distributor 17, the second output pin 9 with the first input pin 6.
First output pin 5, the first input pin 6, third input pin 8, the second output pin 9, third output pin
14, the 4th input pin 15, the 5th input pin 19, the 4th output pin 20 only list one here, actual pipe
Foot number is that the specification of foundation flash chip 3 is determined.
Flash controller 10 is responsible for completing to operate erasing, read-write of flash chip 3 etc..
System in package of the present invention, the structure including the master chip 1 and 2 shared drive of Beidou chip are described
Master chip 1 is packaged together with Beidou chip 2 or the master chip 1, Beidou chip 2 and flash chip 3 are encapsulated in one
It rises.
Pcb board of the present invention, including the system in package.
The features of the present invention and workflow are as follows:
1) contents such as startup program, application program needed for master chip 1 and Beidou chip 2 are preset in flash chip 3 respectively
On.
2) master chip 1 is after electrifying startup, by flash content verification unit 11 to the data integrity of flash chip 3
It is digitally signed verification.Common digital signature verification algorithm is SHA(Secure Hash Algorithm).Secure Hash Algorithm is to realize
One of method of digital signature, the present invention applied by Digital Signature Algorithm be not limited to Secure Hash Algorithm.If verification passes through,
Illustrating the content integrity on flash chip 3 is reliably that master chip 1 works on.Otherwise, master chip 1 directly restart or
Program is allowed to run in endless loop.Endless loop restarts the warm reset realization by software control master chip 1 by software code realization.
3) master chip 1 also can periodically the upgrade procedure to master chip 1 and Beidou chip 2, master chip 1 and Beidou chip 2 be transported
The data for needing to write flash chip 3 during row carry out signature check, it is ensured that the data safety on flash chip 3.
4) master chip 1 is issued by flash controller 10 and is operated to erasing, read-write of flash chip 3 etc.；Beidou chip 2 is logical
The first chip-select pin 4, the first output pin 5 and the first input pin 6 is crossed to issue to the operation such as erasing, read-write of flash chip 3.
5) chip selection signal and Beidou chip 2 that arbitration unit 12 is exported according to 10 chip select terminal of flash controller in master chip 1
The chip selection signal of first chip-select pin 4 output is arbitrated, and determines that master chip 1 or Beidou chip 2 are enjoyed in a certain period of time
There is the access right to flash chip 3, and chip selection signal is exported by the first output end of arbitration unit 12, is managed via second choosing
Foot 13 is connected to the third chip-select pin 18 of flash chip 3.The arbitration useful signal of the second output terminal output of arbitration unit 12
Determine that Beidou chip 2 or flash controller 10 enjoy the access right to flash chip 3.For example:
When the arbitration useful signal that the second output terminal of arbitration unit 12 exports is high level, Beidou chip 2 is enjoyed pair
The control of flash chip 3.At this point, the first output pin 5 passes through third input pin 8, data selector 16, third efferent duct
Foot 14 is connected to the 5th input pin 19；4th output pin 20 is defeated by the 4th input pin 15, data distributor 17, second
Pin 9 is connected to the first input pin 6 out.
When the arbitration useful signal that the second output terminal of arbitration unit 12 exports is low level, master chip 1 is enjoyed to sudden strain of a muscle
Deposit the control of chip 3.At this point, in master chip 1 flash controller 10 output end output signal, by data selector 16,
Third output pin 14 is connected to the 5th input pin 19；4th output pin 20 enters data point by the 4th input pin 15
Orchestration 17 is connected to by the second output terminal of data distributor 17 with flash controller 10.
Claims (5)
1. the structure of a kind of master chip and Beidou chip shared drive, which is characterized in that including master chip (1), Beidou chip (2)
With flash chip (3), the master chip (1) be equipped with arbitration unit (12), flash controller (10), data selector (16) and
Data distributor (17)；
The chip select terminal of Beidou chip (2), the chip select terminal of flash controller (10) are connected with the input terminal of arbitration unit (12), secondary
The first output end for cutting out unit (12) is connected with flash chip (3), the control terminal of data selector (16), data distributor (17)
Control terminal be connected with the second output terminal of arbitration unit (12)；The output end of Beidou chip (2) and data selector (16)
First input end be connected, the output end of flash controller (10) is connected with the second input terminal of data selector (16)；Data
First output end of distributor (17) is connected with Beidou chip (2), and the second output terminal and flash memory of data distributor (17) control
The input terminal of device (10) is connected；The output end of data selector (16), data distributor (17) input terminal and flash chip
(3) it is connected；
The Beidou chip (2) is equipped with the first chip-select pin (4), the first output pin (5) and the first input pin (6), institute
Master chip (1) is stated equipped with the second input pin (7), third input pin (8), the second output pin (9), the second chip-select pin
(13), third output pin (14), the 4th input pin (15), the flash chip (3) be equipped with third chip-select pin (18),
5th input pin (19) and the 4th output pin (20)；
First chip-select pin (4) is connected by the second input pin (7) with the first input end of arbitration unit (12), flash memory
The chip select terminal of controller (10) is connected with the second input terminal of arbitration unit (12), and the first output end of arbitration unit (12) passes through
Second chip-select pin (13) is connected with third chip-select pin (18)；First output pin (5) passes sequentially through third input pin
(8), data selector (16), third output pin (14) are connected with the 5th input pin (19), the 4th output pin (20) according to
Secondary the 4th input pin (15), data distributor (17), the second output pin (9) of passing through is connected with the first input pin (6).
2. the structure of master chip as described in claim 1 and Beidou chip shared drive, which is characterized in that the master chip
It (1) further include the flash content verification unit (11) being connected with flash controller (10) on.
3. a kind of system in package, which is characterized in that shared including master chip as claimed in claim 1 or 2 and Beidou chip
The structure of memory, the master chip (1) are packaged together with Beidou chip (2).
4. a kind of system in package, which is characterized in that shared including master chip as claimed in claim 1 or 2 and Beidou chip
The structure of memory, the master chip (1), Beidou chip (2) and flash chip (3) are packaged together.
5. a kind of pcb board, which is characterized in that including system in package as described in claim 3 or 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201611006059.7A CN106502959B (en) | 2016-11-16 | 2016-11-16 | The structure and system in package, pcb board of master chip and Beidou chip shared drive |
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| CN201611006059.7A CN106502959B (en) | 2016-11-16 | 2016-11-16 | The structure and system in package, pcb board of master chip and Beidou chip shared drive |
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| CN106502959B true CN106502959B (en) | 2019-09-13 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108182036B (en) * | 2018-01-19 | 2021-05-11 | 湖南国科微电子股份有限公司 | Multi-chip system storage implementation device and method |
| CN109101455A (en) * | 2018-08-01 | 2018-12-28 | 湖南国科微电子股份有限公司 | Shared memory systems and the pending program reading/writing method based on shared memory systems |
| CN110456150A (en) * | 2019-06-28 | 2019-11-15 | 宁波三星医疗电气股份有限公司 | A kind of date storage method of multiplexing electric energy meter and the electric energy meter |
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