CN106487259B - A kind of neutral point voltage balance method for three Level Full Bridge DC converters - Google Patents
A kind of neutral point voltage balance method for three Level Full Bridge DC converters Download PDFInfo
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- CN106487259B CN106487259B CN201611094276.6A CN201611094276A CN106487259B CN 106487259 B CN106487259 B CN 106487259B CN 201611094276 A CN201611094276 A CN 201611094276A CN 106487259 B CN106487259 B CN 106487259B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
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- Dc-Dc Converters (AREA)
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Abstract
The invention discloses a kind of neutral point voltage balance methods for three Level Full Bridge DC converters.On the one hand neutral point voltage balance method of the invention is that the turn-on times of three Level Full Bridge DC converter middle external tubes is adjusted according to the deviation of input capacitance voltage to realize, it on the other hand is open-minded simultaneously by controlling concatenated outer tube and inner tube, but the outer tube timing that is turned off in advance compared with inner tube guarantees.Using neutral point voltage balance method of the invention, the striding capacitance in three Level Full Bridge DC converters can be saved, only reservation clamp diode can be realized switching device and the real-time of derided capacitors in device and press, guarantee neutral point voltage balance, meets the needs of high pressure occasion so as to select the device of low-voltage quota, the switching frequency for being conducive to improve device, reduces volume, weight and cost.
Description
Technical field
The present invention relates to a kind of DC-DC electrical energy changers, and in particular to is suitable for high pressure, high-power applications occasion
The control method of lower isolated form three level DC converting means.
Background technique
It is at full speed with the relevant technologies such as generation of electricity by new energy, D.C. high voltage transmission, marine electric power propulsion, high-speed railway be electrical
Development, suitable for high pressure, electrical isolation, high-power applications occasion three Level Full Bridge DC converters cause it is more and more
Concern.Three Level Full Bridge DC converters are solved under high-power occasion using the series connection of low pressure rapidly switched tube
The problems such as switch tube voltage stress is excessively high, and loss is excessive, and device is difficult to select, and cost is excessively high, and switching frequency is too low, improves electricity
Efficiency, power density and the economy of force transformation, are widely used in many instances.
In three Level Full Bridge DC converters, due to the dispersibility of device, route, two concatenated switching tubes and its drive
It is dynamic unavoidably to deposit certain otherness, it needs additionally to apply definitely pressure measure to guarantee what two tandem tap pipes undertook
The consistent neutral point voltage balance with series connection derided capacitors of voltage stress, that is, guarantee the pressure of device, be all the half of input voltage,
To guarantee the safety and reliability of device.Currently, common devices in series technology of pressure equalization includes power end technology of pressure equalization and grid
Pole drive end technology of pressure equalization, wherein power end technology of pressure equalization be on the main circuit increase RC buffer circuit, clamping diode circuit,
Striding capacitance etc., with the raising of voltage class, expense caused by the technology of pressure equalization and loss will all increase.Gate driving end is equal
Pressure technology is then by increasing the clamp circuits such as capacitor, diode, resistance on the driving circuit of device, to realize Tandem devices
Pressure and Control.Since under high-power application, the driving circuit of switching device often uses device supplier to provide
Standard Maturation reliable circuit, and integrated with switching device, interface is fixed, the gate driving equalizer circuit gesture newly introduced
The improvement cost of driving circuit must be caused higher, in addition, discrete component is more in the equalizer circuit, to the coherence request of element
It is very high, screening cost and larger workload.
Therefore, hardware circuit is minimized, guarantees the pressure of Tandem devices from control and neutral point voltage balance is to work as
One of the research hotspot of preceding power electronics field.
Summary of the invention
For the above problem existing for three Level Full Bridge circuits, the invention proposes one kind to become for three Level Full Bridge direct currents
The neutral point voltage balance method of changing device.Neutral point voltage balance method of the invention can be saved in three Level Full Bridge circuits
Striding capacitance, while realizing the neutral point voltage balance for pressing and inputting derided capacitors of two tandem tap pipes, guarantee device
Safety meets the needs of high pressure occasion so as to select the device of low-voltage quota, is conducive to the switch for improving device
Frequency reduces volume, weight and cost.
Specifically, the present invention provides a kind of neutral point voltage balance method for three Level Full Bridge DC converters,
The three Level Full Bridges DC converter includes: the first input derided capacitors Cin1, second input derided capacitors Cin2, first open
Close pipe Q1, second switch Q2, third switching tube Q3, the 4th switching tube Q4, the 5th switching tube Q5, the 6th switching tube Q6, the 7th open
Close pipe Q7With the 8th switching tube Q8, the first rectifier diode DR1, the second rectifier diode DR2, third rectifier diode DR3, the 4th
Rectifier diode DR4, the first clamp diode Dc1, the second clamp diode Dc2, third clamp diode Dc3, the 4th clamp two poles
Pipe Dc4, capacitance Cb, resonant inductance Lr, transformer T, filter inductance Lf, output filter capacitor Cf, which is characterized in that described three
Level Full Bridge DC converter, which does not include, is connected to the first clamp diode Dc1Cathode and the second clamp diode Dc2Anode two
The striding capacitance at end does not include yet and is connected to third clamp diode Dc3Cathode and the 4th clamp diode Dc4Anode both ends
Striding capacitance, the first input derided capacitors Cin1With the second input derided capacitors Cin2It is connected in series in DC input voitage Uin
Between, midpoint O, the first input derided capacitors Cin1Anode and cathode be connected to DC input voitage UinJust
Between pole and midpoint O, the second input derided capacitors Cin2Anode and cathode be connected to midpoint O and DC input voitage Uin
Between cathode, the DC input voitage UinAnode is additionally coupled to first switch tube Q1Collector and the 5th switching tube Q5Collection
Electrode, the DC input voitage UinCathode is additionally coupled to the 4th switching tube Q4Emitter and the 8th switching tube Q8Transmitting
Pole, the first switch tube Q1Emitter be respectively connected to second switch Q2Collector and the first clamp diode Dc1's
Cathode, the 5th switching tube Q5Emitter be respectively connected to the 6th switching tube Q6Collector and the third clamp
Diode Dc3Cathode, the first clamp diode Dc1Anode, the second clamp diode Dc2Cathode, third clamp two
Pole pipe Dc3Anode and the 4th clamp diode Dc4Cathode be connected to midpoint O, the second switch Q2Emitter point
It is not connected to third switching tube Q3Collector and resonant inductance LrFirst end, LrSecond end be connected to the primary side of transformer T
First end, the 6th switching tube Q6Emitter be respectively connected to the 7th switching tube Q7Collector and capacitance Cb?
One end, capacitance CbSecond end be connected to the primary side second end of transformer T, the third switching tube Q3Emitter difference
It is connected to the second clamp diode Dc2Anode and the 4th switching tube Q4Collector, the 7th switching tube Q7Emitter point
It is not connected to the 4th clamp diode Dc4Anode and the 8th switching tube Q8Collector,
The secondary side first end of transformer T is respectively connected to the first rectifier diode DR1Anode and the second rectifier diode DR2
Cathode, the secondary side second end of transformer T is respectively connected to third rectifier diode DR3Anode and the 4th rectifier diode DR4
Cathode, the first rectifier diode DR1Cathode be separately connected third rectifier diode DR3Cathode and filter inductance LfFirst
End, inductance LfSecond end be connected to output filter capacitor CfAnode, and the anode as output voltage, the second two poles of rectification
Pipe DR2Anode be separately connected the 4th rectifier diode DR4Anode and output filter capacitor CfCathode, and as output voltage
Cathode,
The control method includes the following steps:
(1), it will be used to control the control signal G of the first to the 8th switching tube respectively1、G2、……、G8It is delivered to three level
Respective switch pipe Q in full-bridge direct current converting means1、Q2、……、Q8, wherein control signal G2、G3、G6、G7Turn-on time it is solid
It is set to the predetermined amount of time less than 1/2 switch periods --- set time TGu, control signal G1、G4、G5、G8Initial turn-on
Time is less than the set time TGuAbout 2-5 microsecond,
(2), the control signal G is set2、G3、G6、G7So that inner tube second switch Q2With third switching tube Q3Complementation is led
It is logical, the 6th switching tube Q6With the 7th switching tube Q7Complementation conducting.
(3), the control signal G is set1、G2、……、G8So that first switch tube Q1, second switch Q2, the 7th switch
Pipe Q7With the 8th switching tube Q8It simultaneously turns on, third switching tube Q3, third switching tube Q4, the 5th switching tube Q5With the 6th switching tube Q6
It simultaneously turns on；
(4), sampling obtains DC input voitage UinFirst capacitor voltage u between anode and midpoint OCin1And midpoint O
With DC input voitage UinThe second capacitance voltage u between cathodeCin2；
(5), judge first capacitor voltage uCin1With the second capacitance voltage uCin2Between size relation；
(6), work as uCin1>uCin2When, while increasing control signal G1And G8Turn-on time, or simultaneously reduce control letter
Number G4And G5Turn-on time, turn-on time variation delta t=Δ v × (kp+ki/s), wherein Δ v be uCin1And uCin2Electricity
Deviation is pressed, u is equal toCin1–uCin2, proportional integration is carried out to input capacitance voltage deviation Δ v, kp and ki are to input capacitance electricity
Deviation delta v is pressed to carry out ratio and integral coefficient used by proportional integration；
(7), work as uCin1<uCin2When, while reducing control signal G1And G8Turn-on time, or simultaneously increase control letter
Number G4And G5Turn-on time, turn-on time variable quantity is similarly Δ t=Δ v × (kp+ki/s)；
(8), signal G is controlled1And G8Final turn-on time be equal to Ton+ Δ t controls signal G4And G5Final conducting when
Between be equal to TonΔ t, wherein TonIt is obtained by the given regulating error signal fed back with output voltage of output voltage, size Ton
=(Uoref–Uo)×(kp1+ki1/ s), wherein UorefFor output voltage Setting signal, UoFor output voltage feedback signal, wherein
The error with output voltage feedback given to output voltage carries out proportional integration, kp1And ki1To give and exporting to output voltage
The error of Voltage Feedback carries out ratio and integral coefficient used by proportional integration；
(9), to control signal G1、G4、G5、G8Final maximum turn-on time carries out clipping, guarantees turn-on time all always
Less than control signal G2、G3、G6、G7Turn-on time.
Using above-mentioned control strategy, clamp diode D is connected in parallel in three Level Full Bridge DC convertersc1Cathode and Dc2
The striding capacitance at anode both ends is connected in parallel on clamp diode Dc3Cathode and Dc4The striding capacitance at anode both ends can be cancelled.
The advantages of band neutral-point voltage balance method, is:
(1) complicated hardware circuit is not needed, so that it may guarantee the pressure of tandem tap pipe, all the input electricity of receiving half
Pressure, is effectively reduced the voltage stress of device, guarantees its safety；
(2) complicated hardware circuit is not needed, so that it may guarantee the pressure of input derided capacitors, all the input electricity of receiving half
Pressure, is further ensured that the pressure and neutral point voltage balance of tandem tap pipe；
(3) striding capacitance in traditional three Level Full Bridge DC transfer circuits can be saved, the control of striding capacitance voltage is solved
The problem that system is complicated, floating voltage is unbalance and volume is larger is conducive to simplify circuit topological structure, improve circuit reliability and
Reduce cost；
(4) be conducive to select the quick switching device of low pressure, improve switching frequency, reduce volume, the weight of whole device
And cost；
(5) control method is simple, effectively, and easily realizes.
Detailed description of the invention
Fig. 1 is the main circuit diagram using no three Level Full Bridge DC converter of striding capacitance type of the invention；
Fig. 2 is driving control signal schematic diagram of the invention；
Fig. 3 is the control schematic diagram that turn-on time is adjusted in the present invention；
Fig. 4 is that the present invention illustrates without the driving control signal that capacitor voltage deviation is adjusted；
Fig. 5 is a kind of driving control signal schematic diagram of prior art；
Fig. 6 is the input derided capacitors voltage and tandem tap tube voltage wave that Fig. 1 topological structure uses the embodiment of the present invention
Shape；
Fig. 7 is the input derided capacitors voltage and tandem tap tube voltage that Fig. 1 topological structure uses Fig. 4 driving control signal
Waveform；
Fig. 8 is the input derided capacitors voltage and tandem tap tube voltage wave that Fig. 1 topological structure uses Fig. 5 prior art
Shape.
Specific embodiment
The present invention will be further explained below with reference to the attached drawings and specific examples.
Fig. 1 is the used main circuit without three Level Full Bridge DC converter of striding capacitance type controlled of the method for the present invention
Figure.As shown in Figure 1, eliminating striding capacitance in the circuit, the first input derided capacitors C is specifically included thatin1With the second input point
Voltage capacitance Cin2；First switch tube Q1, second switch Q2, third switching tube Q3, the 4th switching tube Q4, the 5th switching tube Q5, the 6th
Switching tube Q6, the 7th switching tube Q7With the 8th switching tube Q8；First rectifier diode DR1, the second rectifier diode DR2, third it is whole
Flow diode DR3, the 4th rectifier diode DR4；First clamp diode Dc1, the second clamp diode Dc2, third clamp diode
Dc3, the 4th clamp diode Dc4；Capacitance Cb；Resonant inductance Lr；Transformer T；Filter inductance Lf；Output filter capacitor Cf.Figure
Inputted on derided capacitors in 1+,-, O characterize the input direct-current bus anodes of three Level Full Bridge DC converters, cathode and in
Point, uCin1And uCin2The voltage of respectively first input derided capacitors and the second input derided capacitors both ends.
Fig. 2 shows the timing diagram of the driving control signal in the embodiment of the present invention, wherein G1、G2、……、G8Respectively
It is delivered to respective switch pipe Q in three Level Full Bridge DC converters1、Q2、……、Q8Driving control signal, wherein Q1、Q4、
Q5And Q8For the outer tube in device, Q2、Q3、Q6And Q7For the inner tube in device.The specific timing of driving control signal shown in Fig. 2
Are as follows: G1With G2Open-minded, G simultaneously1Compared with G2It turns off in advance, i.e. G1With G2Rising edge is overlapped, G1Compared with G2Failing edge is advanced, similar, G4With
G3Rising edge is overlapped, G4Compared with G3Failing edge is advanced, G5With G6Rising edge is overlapped, G5Compared with G6Failing edge is advanced, G8With G7Rising edge weight
It closes, G8Compared with G7Failing edge is advanced.Driving control signal G in Fig. 21、G2、G7、G8It is similarly while open-minded, rising edge is overlapped, driving
Control signal G3、G4、G5、G6To be open-minded simultaneously, rising edge is overlapped, and meets G4With G1Open that differ 1/2 switch constantly all
Phase, G5With G8Open constantly difference 1/2 switch periods, G2With G3Open constantly difference 1/2 switch periods, G6With G7's
Open 1/2 switch periods of difference constantly.In addition, control signal shown in Fig. 2 also meets G2And G3Complementation conducting, i.e. G2For high electricity
Usually, G3It must be low level, G2When for low level, G3It must be high level, G is not present2And G3It is all the time of high level, it is similar
, G6And G7Also complementary conducting.In control signal shown in Fig. 2, G2、G3、G6、G7Turn-on time be TGu, it is one less than 1/2 switch
The fixed value in period, G1、G4、G5、G8Turn-on time consist of two parts, a part be Ton, another part is shadow region in figure
Δ t shown in the part of domain, i.e., final turn-on time are equal to Ton+ Δ t or TonΔ t, it should be noted that G1、G4、G5、G8Most
Whole turn-on time still needs to guarantee to be less than G2、G3、G6、G7Turn-on time be TGu。
Fig. 3 is the control schematic diagram that turn-on time is adjusted in the present invention, due to inner tube driving control signal already described in Fig. 2
G2、G3、G6、G7Turn-on time be fixed as TGu, therefore outer tube driving control signal G is only provided in Fig. 31、G4、G5、G8Turn-on time
The schematic diagram of adjusting.In Fig. 3, driving control signal G1、G4、G5、G8Turn-on time consists of two parts, and a part is by output electricity
Pressure gives and the error of feedback is obtained by output voltage feedback proportional integral controller, is denoted as Ton=(Uoref–Uof)×(kp1+
ki1/ s), wherein UorefFor output voltage Setting signal, UofFor output voltage UoSampled feedback signal, kp1And ki1For output
The ratio and integral coefficient of Voltage Feedback ratio integral controller；G1、G4、G5、G8Another part of turn-on time is by capacitor electricity
Press deviation delta v=uCin1–uCin2It is obtained through capacitance voltage deviation ratio integral controller, is denoted as Δ t=Δ v × (kp+ki/s),
Wherein kp and ki is the ratio and integral coefficient in capacitance voltage deviation ratio integral controller.Signal G is controlled in Fig. 31、G8Most
Whole turn-on time is denoted as Ton1=Ton+ Δ t, G4、G5Final turn-on time is denoted as Ton2=Ton–Δt.In order to guarantee device
Press performance, Ton1And Ton2It also needs to carry out amplitude limiting processing, guarantees that its maximum value is both less than G2、G3、G6、G7Fixation turn-on time
TGu。
Fig. 4 is the driving control signal schematic diagram adjusted in the embodiment of the present invention without capacitor voltage deviation.It is shown in Fig. 4
Driving control signal in, control signal G1、G4、G5、G8The turn-on time error that is only given by output voltage and fed back pass through
Output voltage feedback proportional integral controller obtains, and will not further be adjusted again with capacitance voltage deviation, i.e., no Fig. 2
Shown in shadow region, other parts are identical with Fig. 2.
Fig. 5 is a kind of driving control signal schematic diagram of the prior art.In driving control signal shown in Fig. 5, all drives
The turn-on time of dynamic signal is all equal, is all fixed as TGu, guaranteed by adjusting the phase difference Φ of inner and outer tubes control signal
Output voltage stabilization.
Fig. 6 gives Fig. 1 topological structure using the main waveform diagram after the embodiment of the present invention, is followed successively by from top to bottom
Outer tube Q1With inner tube Q2Driving control signal waveform G1、G2, Q1And Q2Collector Emitter both end voltage waveform uce_Q1、
uce_Q2, input derided capacitors both end voltage waveform ucin1And ucin2, it can be seen that after using the embodiment of the present invention, tandem tap
Pipe Q1And Q2Collector Emitter both end voltage and input derided capacitors voltage all keep equal, are the one of input voltage
Half, it ensure that the pressure and neutral point voltage balance of Tandem devices.
Fig. 7 is the main waveform diagram that Fig. 1 topological structure uses Fig. 4 driving control signal, waveform from top to bottom with
Fig. 6 is consistent, respectively outer tube Q1With inner tube Q2Driving control signal waveform G1、G2, Q1And Q2Collector Emitter both ends
Voltage waveform uce_Q1、uce_Q2, input derided capacitors both end voltage waveform ucin1And ucin2, it can be seen that using shown in Fig. 3 without
After the driving control signal of capacitance voltage bias adjustment, tandem tap pipe Q1And Q2Collector Emitter both end voltage and input
Derided capacitors voltage cannot keep it is equal, have one be greater than half input voltage, another be less than half input voltage,
The neutral point voltage balance of pressure and derided capacitors of Tandem devices all not can guarantee.
Fig. 8 is Fig. 1 topological structure using the main waveform diagram after Fig. 5 prior art, waveform and Fig. 6 from top to bottom
Unanimously, respectively outer tube Q1With inner tube Q2Driving control signal waveform G1、G2, Q1And Q2Collector Emitter both end voltage
Waveform uce_Q1、uce_Q2, input derided capacitors both end voltage waveform ucin1And ucin2, it can be seen that using drive control shown in Fig. 5
After signal, tandem tap pipe Q1And Q2Collector Emitter both end voltage and input derided capacitors voltage have all had occurred completely
Deviate, concatenated each device, including switching tube and input derided capacitors, requires to bear entire input voltage, voltage stress
It is excessively high, the safety and reliability of device is seriously affected, is also unfavorable for reducing cost and improves switching frequency.
Using the main circuit parameter of the embodiment of the present invention are as follows: input voltage Uin=1200VDC；Output voltage Uo=
900VDC；Export electric current Io=330A；Input derided capacitors Cin1=Cin2=1450 μ F；Output filter capacitor Cf=750 μ F；Become
The no-load voltage ratio of depressor T is 1:1；Resonant inductance Lr=12 μ H；Capacitance Cb=150 μ F；Filter inductance Lf=450 μ H；Switching tube
Q1、Q2、Q3、Q4、Q5、Q6、Q7And Q8It is all IGBT；Rectifier diode DR1、DR2、DR3And DR4It is all fast recovery diode；Clamp two
Pole pipe Dc1、Dc2、Dc3、Dc4It is all fast recovery diode.
The parameter of the corresponding driving circuit of the embodiment of the present invention are as follows: switching frequency fs=10kHz；Switch periods Ts=100 μ
s；1 μ s of dead time；Inner tube G2、G3、G6、G7Turn-on time be fixed as 49 μ s；Outer tube G1、G4、G5、G8Maximum turn-on time
It is limited to 45 μ s；The maximum constraint of regulating time Δ t is 2 μ s,.
Claims (1)
1. a kind of neutral point voltage balance method for three Level Full Bridge DC converters, the three Level Full Bridges DC converting
Device includes: the first input derided capacitors Cin1, second input derided capacitors Cin2, first switch tube Q1, second switch Q2,
Three switching tube Q3, the 4th switching tube Q4, the 5th switching tube Q5, the 6th switching tube Q6, the 7th switching tube Q7With the 8th switching tube Q8,
One rectifier diode DR1, the second rectifier diode DR2, third rectifier diode DR3, the 4th rectifier diode DR4, first clamp two
Pole pipe Dc1, the second clamp diode Dc2, third clamp diode Dc3, the 4th clamp diode Dc4, capacitance Cb, resonance electricity
Feel Lr, transformer T, filter inductance Lf, output filter capacitor Cf, which is characterized in that the three Level Full Bridges DC converter is not
Comprising being connected to the first clamp diode Dc1Cathode and the second clamp diode Dc2The striding capacitance at anode both ends, does not include yet
It is connected to third clamp diode Dc3Cathode and the 4th clamp diode Dc4The striding capacitance at anode both ends, first input
Derided capacitors Cin1With the second input derided capacitors Cin2It is connected in series in DC input voitage UinBetween, midpoint O, described
One input derided capacitors Cin1Anode and cathode be connected to DC input voitage UinBetween anode and midpoint O, described second
Input derided capacitors Cin2Anode and cathode be connected to midpoint O and DC input voitage UinBetween cathode, the direct current is defeated
Enter voltage UinAnode is further connected to first switch tube Q1Collector and the 5th switching tube Q5Collector, the direct current is defeated
Enter voltage UinCathode is further connected to the 4th switching tube Q4Emitter and the 8th switching tube Q8Emitter, described first opens
Close pipe Q1Emitter be respectively connected to second switch Q2Collector and the first clamp diode Dc1Cathode, the described 5th
Switching tube Q5Emitter be respectively connected to the 6th switching tube Q6Collector and the third clamp diode Dc3Yin
Pole, the first clamp diode Dc1Anode, the second clamp diode Dc2Cathode, third clamp diode Dc3Anode
With the 4th clamp diode Dc4Cathode be connected to midpoint O, the second switch Q2Emitter be respectively connected to third
Switching tube Q3Collector and resonant inductance LrFirst end, LrSecond end be connected to the primary side first end of transformer T, it is described
6th switching tube Q6Emitter be respectively connected to the 7th switching tube Q7Collector and capacitance CbFirst end, blocking electricity
Hold CbSecond end be connected to the primary side second end of transformer T, the third switching tube Q3Emitter be respectively connected to the second pincers
Position diode Dc2Anode and the 4th switching tube Q4Collector, the 7th switching tube Q7Emitter be respectively connected to the 4th
Clamp diode Dc4Anode and the 8th switching tube Q8Collector,
The secondary side first end of transformer T is respectively connected to the first rectifier diode DR1Anode and the second rectifier diode DR2Yin
The secondary side second end of pole, transformer T is respectively connected to third rectifier diode DR3Anode and the 4th rectifier diode DR4Yin
Pole, the first rectifier diode DR1Cathode be separately connected third rectifier diode DR3Cathode and filter inductance LfFirst end,
Inductance LfSecond end be connected to output filter capacitor CfAnode, and the anode as output voltage, the second rectifier diode
DR2Anode be separately connected the 4th rectifier diode DR4Anode and output filter capacitor CfCathode, and as output voltage
Cathode,
The neutral point voltage balance method includes the following steps:
(1), it will be used to control the control signal G of the first to the 8th switching tube respectively1、G2、……、G8It is delivered to three Level Full Bridges
Respective switch pipe Q in DC converter1、Q2、……、Q8, wherein control signal G2、G3、G6、G7Turn-on time be fixed as
Less than a predetermined amount of time of 1/2 switch periods --- set time TGu, control signal G1、G4、G5、G8Maximum turn-on time
Less than the set time TGu；
(2), the control signal G is set2、G3、G6、G7So that inner tube second switch Q2With third switching tube Q3Complementation conducting,
6th switching tube Q6With the 7th switching tube Q7Complementation conducting；
(3), the control signal G is set1、G2、……、G8So that first switch tube Q1, second switch Q2, the 7th switching tube Q7
With the 8th switching tube Q8It simultaneously turns on, third switching tube Q3, third switching tube Q4, the 5th switching tube Q5With the 6th switching tube Q6Simultaneously
Conducting；
(4), the control signal G is set4With G1Open constantly difference 1/2 switch periods, G5With G8Open and differ constantly
1/2 switch periods, G2With G3Open constantly difference 1/2 switch periods, G6With G7Open constantly differ 1/2 switch
Period；
(5), sampling obtains DC input voitage UinFirst capacitor voltage u between anode and midpoint OCin1And midpoint O and straight
Flow input voltage UinThe second capacitance voltage u between cathodeCin2；
(6), judge first capacitor voltage uCin1With the second capacitance voltage uCin2Between size relation；
(7), work as uCin1>uCin2When, while increasing control signal G1And G8Turn-on time, or simultaneously reduce control signal G4With
G5Turn-on time, turn-on time variation delta t=Δ v × (kp+ki/s), wherein Δ v be uCin1And uCin2Voltage deviation,
It is equal to uCin1–uCin2, proportional integration is carried out to input capacitance voltage deviation Δ v, kp and ki are to input capacitance voltage deviation Δ
V carries out ratio and integral coefficient used by proportional integration；
(8), work as uCin1<uCin2When, while reducing control signal G1And G8Turn-on time, or simultaneously increase control signal G4With
G5Turn-on time, turn-on time variable quantity is similarly Δ t=Δ v × (kp+ki/s)；
(9), signal G is controlled1And G8Turn-on time be equal to Ton+ Δ t controls signal G4And G5Turn-on time be equal to TonΔ t,
Wherein, TonIt is obtained by the given regulating error signal fed back with output voltage of output voltage, size Ton=(Uoref–Uof)×
(kp1+ki1/ s), wherein UorefFor output voltage Setting signal, UofFor output voltage UoSampled feedback signal, wherein to defeated
The given error with output voltage feedback of voltage carries out proportional integration, kp out1And ki1For to output voltage is given and output voltage
The error of feedback carries out ratio and integral coefficient used by proportional integration；
(10), to control signal G1、G4、G5、G8Final turn-on time carries out clipping, guarantees that turn-on time is all always less than control letter
Number G2、G3、G6、G7Turn-on time.
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| EP4203292A4 (en) * | 2020-09-09 | 2023-10-11 | Huawei Digital Power Technologies Co., Ltd. | Three-level inverter and control method and system |
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