CN106486532B - The forming method of ring gate field-effect transistor - Google Patents
The forming method of ring gate field-effect transistor Download PDFInfo
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- CN106486532B CN106486532B CN201510532178.5A CN201510532178A CN106486532B CN 106486532 B CN106486532 B CN 106486532B CN 201510532178 A CN201510532178 A CN 201510532178A CN 106486532 B CN106486532 B CN 106486532B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of forming method of ring gate field-effect transistor, comprising: the substrate including first area, second area and third region is provided；Several sacrificial layers arranged in parallel positioned at the buffer layer of substrate surface and positioned at second area buffer-layer surface are sequentially formed, the orientation of the sacrificial layer and the orientation of first area, second area and third region are mutually perpendicular to；Sequentially form the semiconductor doping layer positioned at the channel layer of buffer-layer surface and positioned at channel layer surface；Remove the semiconductor doping layer of the middle area；The sacrificial layer is removed, the breaker topping surface is exposed；Etching removes the buffer layer of the second area, until exposing substrate surface；The gate structure of covering residual buffer layer sidewall surfaces is formed in the substrate surface exposed, gate structure surround the channel layer of the second area, and gate structure also covers the semiconductor doping layer surface of external zones.Present invention improves the electric properties of the ring gate field-effect transistor of formation.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular to a kind of forming method of ring gate field-effect transistor.
Background technique
With the continuous development of semiconductor process technique, the development trend that semiconductor technology node follows Moore's Law is continuous
Reduce.In order to adapt to the reduction of process node, the measure generallyd use is constantly to shorten the channel length of MOSFET field-effect tube.
The shortening of channel length has the tube core density for increasing chip, increases the benefits such as the switching speed of MOSFET field-effect tube.
However, with the shortening of device channel length, device source electrode between drain electrode at a distance from also shorten therewith, so
Grid is deteriorated to the control ability of channel, and the difficulty of grid voltage pinch off (pinch off) channel is also increasing, so that subthreshold
Value electric leakage (subthreshold leakage) phenomenon, i.e., so-called short-channel effect (SCE:short-channel
Effects it) is easier to occur.
Therefore, in order to preferably adapt to the scaled requirement of device size, semiconductor technology gradually starts from plane
Mosfet transistor to more high effect three-dimensional transistor transient, such as fin field effect pipe (FinFET).
In FinFET, grid can at least be controlled ultra-thin body (fin) from two sides, be had more much better than than planar MOSFET devices
Grid can be good at inhibiting short-channel effect to the control ability of channel；And FinFET has better relative to other devices
The compatibility of existing production of integrated circuits technology.
In order to which the driving capability of electric current is continuously improved and inhibits short-channel effect, traditional fin field effect pipe has been difficult to full
The sufficient ever-reduced demand of process node, therefore the concept of ring grid (GWR, Gate-Wrape-Around) field-effect tube is suggested,
The application of ring gate field-effect transistor can obtain bigger integrated level, and effectively improve short channel effect problem.
However, the electric property for the ring gate field-effect transistor that the prior art is formed is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of ring gate field-effect transistor, improves the electricity of ring gate field-effect transistor
Learn performance.
To solve the above problems, the present invention provides a kind of forming method of ring gate field-effect transistor, comprising: provide substrate, institute
Stating substrate includes the first area being arranged successively along first direction, second area and third region, during the second area includes
Between area and the external zones positioned at middle area two sides, wherein the orientation of the middle area and external zones and the first direction
In parallel；Sequentially form several parallels positioned at the buffer layer of the substrate surface and positioned at second area buffer-layer surface
The sacrificial layer of column, and the orientation of the sacrificial layer is mutually perpendicular to the first direction；It sequentially forms and is located at the buffering
The channel layer of layer surface and semiconductor doping layer positioned at the channel layer surface, the channel layer cover the sacrificial layer
Partial sidewall surface, the semiconductor doping layer covers the partial sidewall surface of the sacrificial layer；Remove the middle area
Semiconductor doping layer retains the semiconductor doping layer of the external zones, first area and third region；The sacrificial layer is removed,
Expose the breaker topping surface；Etching removes the buffer layer of the second area, until exposing substrate surface；Institute
State the gate structure that the substrate surface that exposes forms covering residual buffer layer sidewall surfaces, the gate structure is around described the
The channel layer in two regions, the gate structure also cover the semiconductor doping layer surface of external zones.
Optionally, while etching removes the buffer layer of the second area, also etching removal first area part is wide
The buffer layer of degree and the buffer layer of third region partial width.
Optionally, the gate structure also covers first area part semiconductor doping layer surface and third region part
Semiconductor doping layer surface.
Optionally, positioned at the gate structure sidewall of the substrate surface and positioned at the semiconductor doping layer top surface
Gate structure sidewall flushes.
Optionally, the substrate is InP substrate；The material of the buffer layer is InP.
Optionally, the material of the channel layer is iii-v element compound material.
Optionally, the iii-v element compound material is InGaAs, GaAs, InAs or InSb.
Optionally, the channel layer is formed using metal organic vapor technique；Using metal organic vapor work
Skill forms the semiconductor doping layer.
Optionally, the material of the semiconductor doping layer is the InGaAs of n-type doping；Alternatively, the semiconductor doping layer
Material be p-type doping InGaAs.
Optionally, the buffer layer with a thickness of 10 angstroms to 50 angstroms, the channel layer with a thickness of 10 angstroms to 300 angstroms, institute
State semiconductor doping layer with a thickness of 10 angstroms to 100 angstroms.
Optionally, etching barrier layer is also formed between the channel layer and the semiconductor doping layer.
Optionally, the material of the etching barrier layer is InP.
Optionally, the material of the sacrificial layer is metallo organic material.
Optionally, the material of the sacrificial layer is zirconium naphthenate, nickel naphthenate, aphthenic acids tungsten or aphthenic acids titanium.
Optionally, it before forming the channel layer, further comprises the steps of: and hydrogenation treatment is carried out to the sacrificial layer, reduce
The line edge roughness of sacrificial layer.
Optionally, the hydrotreated technological parameter includes: H2Flow is 100sccm to 1000sccm, chamber pressure
For 0.1atm to 2atm, chamber temp is 100 degrees Celsius to 1000 degrees Celsius, and handling duration is 10 minutes to 5 hours.
Optionally, the processing step for removing the semiconductor doping layer of the middle area includes: in the first area and
The semiconductor doping layer top surface in three regions forms graph layer, and the graph layer is also located at the semiconductor doping layer of external zones
Top surface；Using the graph layer as exposure mask, etching removes the semiconductor doping layer of the middle area；Remove the graph layer.
Optionally, the gate structure includes: gate dielectric layer and the gate electrode layer positioned at gate dielectric layer surface.
Optionally, the material of the gate dielectric layer is silica, silicon nitride or high-k gate dielectric material.
Optionally, the material of the gate electrode layer be Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN,
W, WN or WSi.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of the forming method of ring gate field-effect transistor provided by the invention, in second area buffer-layer surface shape
At several sacrificial layers arranged in parallel, and the orientation of the sacrificial layer and first area, second area and third region
Orientation is mutually perpendicular to；Then, it sequentially forms positioned at the channel layer of buffer-layer surface and partly leading positioned at channel layer surface
Body doped layer, the partial sidewall surface of the channel layer covering sacrificial layer, semiconductor doping layer cover the partial sidewall of sacrificial layer
Surface；The semiconductor doping layer of middle area is removed, the semiconductor doping layer of external zones, first area and third region is retained, with
Form source region and the drain region of ring gate field-effect transistor；Sacrificial layer is removed, breaker topping surface is exposed；Etching removal described second
The buffer layer in region, until exposing substrate surface；Covering residual buffer layer side wall is formed in the substrate surface exposed
The gate structure on surface, the gate structure surround the channel layer of the second area, and the gate structure also covers the secondth area
The semiconductor doping layer surface in domain.In the present invention, sacrificial layer, the secondth area are removed after formation channel layer between adjacent sacrificial layer
The channel layer (i.e. channel region) in domain is determined that therefore, channel region does not undergo etching technics in the present invention by adjacent sacrificial layer, is avoided
The figure that etching technics introduces transmits the problem of deviation so that in the present invention position precision of channel region and pattern accuracy compared with
It is high, it is thus also avoided that etching technics etching injury problem caused by channel region, to improve the electric property of ring gate field-effect transistor.
Further, while the buffer layer of etching removal second area, also etching removes first area partial width
The buffer layer of buffer layer and third region partial width, therefore the channel layer bottom surface of first area partial width and
The channel layer bottom surface of three region partial widths is exposed, so that the contact area of gate structure and channel layer increases,
That is, the contact area of channel region and gate structure is increased, to improve gate structure to the control ability of channel region, further
Improve the electric property of ring gate field-effect transistor.
Further, in the present invention, the material of channel layer is InGaAs, so that the material of the channel region of ring gate field-effect transistor is
III-V material, therefore channel region carriers mobility is high, to further increase the electric property of ring gate field-effect transistor.
Further, in the present invention, the material of sacrificial layer is metallo organic material, enables sacrificial layer by exposing work
The problem of skill and developing process are directly formed, and the figure transmitting deviation of etching technics introducing is avoided, so that the sacrifice formed
The position precision and pattern accuracy of layer are higher, so that channel region position precision with higher and pattern are accurate
Degree.Also, after carrying out hydrogenation treatment to sacrificial layer, the line edge roughness of sacrificial layer can be reduced, accordingly make this hair
The channel region of bright middle formation also has lesser line edge roughness, further increases the pattern accuracy of channel region, thus into
The electric property of one step improvement ring gate field-effect transistor.
Detailed description of the invention
Fig. 1 to Figure 19 is the structural schematic diagram for the ring gate field-effect transistor forming process that one embodiment of the invention provides.
Specific embodiment
It can be seen from background technology that it is urgent to provide a kind of forming methods of new ring gate field-effect transistor, solve in the prior art
The problem of the electric property difference of ring gate field-effect transistor.
It has been investigated that the formation of channel region has been usually subjected to etching technics in ring gate field-effect transistor, it will be in mask layer
Figure is transferred to channel region, in the figure transmittance process, is limited the figure transmitting by etching technics and is easy to appear
Deviation, the channel region pattern resulted in is poor, and the electric property in turn resulting in ring gate field-effect transistor is poor.And due to the shape of channel region
At experienced etching technics, the etching technics easily causes the degradation of channel region, to further result in ring gate field-effect
The electric property of pipe is deteriorated.
To solve the above problems, the present invention provides a kind of forming method of ring gate field-effect transistor, substrate, the substrate are provided
Including along the first area that first direction is arranged successively, second area and third region, the second area include middle area and
External zones positioned at middle area two sides, wherein the orientation of the middle area and external zones is parallel with the first direction；According to
It is secondary to form the buffer layer for being located at the substrate surface and several sacrifices arranged in parallel positioned at second area buffer-layer surface
Layer, and the orientation of the sacrificial layer is mutually perpendicular to the first direction；It sequentially forms positioned at the buffer-layer surface
Channel layer and semiconductor doping layer positioned at the channel layer surface, the channel layer cover the part side of the sacrificial layer
Wall surface, the semiconductor doping layer cover the partial sidewall surface of the sacrificial layer；The semiconductor for removing the middle area is mixed
Diamicton retains the semiconductor doping layer of the external zones；The sacrificial layer is removed, the breaker topping surface is exposed；It carves
Etching off removes the buffer layer of the second area, until exposing substrate surface；Covering is formed in the substrate surface exposed
The gate structure of residual buffer layer sidewall surfaces, channel layer of the gate structure around the second area, the grid knot
Structure also covers the semiconductor doping layer surface of second area.
In the present invention, adjacent sacrificial layer defines the channel region of ring gate field-effect transistor, is initially formed several arranged in parallel
Then sacrificial layer forms channel layer between buffer-layer surface and sacrificial layer, then remove sacrificial layer, adjacent sacrificial layer it
Between channel layer be ring gate field-effect transistor channel region.Therefore, the channel region in the present invention does not undergo etching technics, avoids
Figure caused by etching technics transmits the problem of deviation, so that the channel region in the present invention has good pattern；Simultaneously as
Channel region in the present invention does not undergo etching technics, etching technics etching injury caused by channel region is avoided, so that channel
Area keeps good performance, to improve the electric property of the ring gate field-effect transistor of formation.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 19 is the structural schematic diagram for the ring gate field-effect transistor forming process that one embodiment of the invention provides.
Be schematic perspective view with reference to Fig. 1, Fig. 1, substrate 100 be provided, the substrate 100 include along first direction successively
First area I, the second area II and third region III of arrangement, the second area II include middle area 110 and are located at intermediate
The external zones 120 of 110 two sides of area, wherein the orientation of the middle area 110 and external zones 120 is parallel with first direction.
In the present embodiment, the substrate 100 is InP substrate.It is subsequent that channel layer, the ditch are formed on the substrate 100
The material of channel layer is iii-v element compound material, III-V element compound-material and InP Lattice Matching, so that channel
The carrier concentration and electron mobility of layer are very high, are conducive to the electric property for improving ring gate field-effect transistor.
In the present embodiment, the second area II be ring gate field-effect transistor to be formed channel region region, described first
Region I and third region III is the region of the source-drain area of ring gate field-effect transistor to be formed, and the gate structure being subsequently formed also position
In part first area I and part second area II.
The middle area 110 is the region that the channel region top surface being subsequently formed is exposed, and the external zones 120 is
The region for the semiconductor doping layer covering that channel region top surface is subsequently formed.
It continues to refer to figure 1, forms the buffer layer (buffer layer) 101 for being located at 100 surface of substrate.
In the present embodiment, the material of the buffer layer 101 is InP, using metal organic chemical compound vapor deposition technique shape
At the buffer layer 101.
In order to improve the electric property of ring gate field-effect transistor, the material of the substrate 100 is generally the InP adulterated, and institute
The material for stating buffer layer 101 is undoped InP.The effect of the buffer layer 101 is: reducing substrate 100 and is subsequently formed
Channel layer between lattice mismatch, avoid the stress between substrate 100 and channel layer excessive, to prevent substrate
100 and channel layer deform.Meanwhile the buffer layer 101 also provides good interface basis, energy to be subsequently formed channel layer
Adverse effect of the defects of the substrate 100 to channel layer is enough reduced, so that the channel layer formed is superior in quality.
If subsequent directly form channel layer on 100 surface of substrate, then, due to the lattice between substrate 100 and channel layer
Constants are larger, then the lattice mismatch between substrate 100 and channel layer is larger, and substrate 100 and channel layer is easy to cause to send out
Change shape, and the lattice defect being located in the channel layer on 100 surface of substrate increases, and influences the quality of channel layer.Also, substrate
The defects of 100 can also make the second-rate of the channel layer being subsequently formed.
Also, it is subsequent after the buffer layer 101 of removal second area II, it can be by the second area II's being subsequently formed
Channel layer bottom surface is exposed, so that the channel layer bottom surface of the gate structure being subsequently formed and second area II
It is in contact, forms the gate structure around channel region.
In the present embodiment, the buffer layer 101 with a thickness of 10 angstroms to 50 angstroms.
With reference to Fig. 2 and Fig. 3, wherein Fig. 2 is schematic perspective view, and Fig. 3 is the top view of Fig. 2, in the second area
101 surface of II buffer layer forms several sacrificial layers 102 arranged in parallel, and the orientation of the sacrificial layer 102 and described the
One direction is mutually perpendicular to.
In the present embodiment, cutting line AA1, cutting line BB1 and first direction are parallel to each other, and cut meeting along cutting line AA1
Sacrificial layer 102 is cut to, the buffer layer 101 between adjacent sacrificial layer 102 can be cut to along cutting line BB1 cutting.
The adjacent sacrificial layer 102 defines the position of ring gate field-effect transistor channel region, it is subsequent adjacent sacrificial layer 102 it
Between channel region of the channel layer as ring gate field-effect transistor that is formed of 101 surface of buffer layer.
The material of the sacrificial layer 102 is different from the material of the buffer layer 101, and the material of the sacrificial layer 102 with
The material for the channel layer being subsequently formed and the material of semiconductor doping layer are different, so that subsequent can be by sacrificial layer
102 etching removals.
Also, the material of the sacrificial layer 102 should also be material easy to remove, and remove the sacrificial layer 102
Technique will not cause to damage to the channel layer and semiconductor doping layer being subsequently formed.
In one embodiment, the material of the sacrificial layer 102 can be amorphous silicon, amorphous carbon or silicon nitride.Form institute
The processing step for stating sacrificial layer 102 includes: to form expendable film on 101 surface of buffer layer；It is formed in the sacrifice film surface
Patterned photoresist layer；Using the patterned photoresist layer as exposure mask, etches the expendable film and formed positioned at second area
The sacrificial layer 102 on 101 surface of II buffer layer.
In the present embodiment, the material of the sacrificial layer 102 is organic (metallic organic) material of metal.Form institute
The processing step for stating sacrificial layer 102 includes: to form expendable film on 101 surface of buffer layer using spin coating process；To institute
It states expendable film and is exposed processing and development treatment, removal first area I, third region III and part second area II
Expendable film, formed be located at the second area II several sacrificial layers 102 arranged in parallel.
Material using metallo organic material as sacrificial layer 102, is advantageous in that: on the one hand, using the organic material of metal
Expect the material as sacrificial layer 102, the sacrificial layer 102 directly can be formed by exposure development processing, reduces etching and pass
Pass the figure deviation occurred in graphic procedure；On the other hand, the technique of subsequent removal sacrificial layer 102 is to metallo organic material and ditch
Etching selection ratio with higher between road layer material avoids the technique of removal sacrificial layer 102 from introducing unnecessary damage.Together
When, it is subsequent that hydrogenation treatment also is carried out to sacrificial layer 102, side wall line edge roughness (LER, the Line of sacrificial layer 102 can be reduced
Edge Roughness), improve the sidewall profile of sacrificial layer 102, improves the channel layer and semiconductor being subsequently formed accordingly
The sidewall profile of doped layer then improves the pattern of ring gate field-effect transistor channel region.
The material of the sacrificial layer 102 is zirconium naphthenate (Zirconium naphthenate), nickel naphthenate (Nickel
Naphthenate), aphthenic acids tungsten (Tungsten naphthenate) or aphthenic acids titanium (Titanium naphthenate).
In the present embodiment, the material of the sacrificial layer 102 is nickel naphthenate.
The thickness of the sacrificial layer 102 is more than or equal to the sum of the channel layer being subsequently formed and thickness of semiconductor doping layer,
Guarantee that the top surface for being subsequently formed sacrificial layer 102 after semiconductor doping layer is exposed, therefore the sacrificial layer 102
Thickness is determined according to the sum of the channel layer being subsequently formed and the thickness of semiconductor doping layer.
It after forming the sacrificial layer 102, further comprises the steps of: and hydrogenation treatment is carried out to the sacrificial layer 102, reduce sacrificial
The line edge roughness of domestic animal layer 102.
In the present embodiment, the hydrotreated technological parameter includes: H2Flow is 100sccm to 1000sccm, chamber
Pressure is 0.1atm to 2atm, and chamber temp is 100 degrees Celsius to 1000 degrees Celsius, and handling duration is 10 minutes to 5 hours.
With reference to fig. 4 to fig. 6, Fig. 4 is top view, and Fig. 5 is the schematic diagram of the section structure that Fig. 4 is cut along cutting line AA1, Fig. 6
For the schematic diagram of the section structure that Fig. 4 is cut along cutting line BB1, the channel layer positioned at 101 surface of buffer layer is sequentially formed
103 and positioned at 103 top surface of channel layer semiconductor doping layer 104.
In the present embodiment, the channel layer 103 covers the partial sidewall surface of the sacrificial layer 102, and the semiconductor is mixed
Diamicton 104 also covers the partial sidewall surface of the sacrificial layer 102, and 104 top of the semiconductor doping layer and sacrificial layer 102
Top flushes.In other embodiments, at the top of can also be lower than the sacrificial layer at the top of the semiconductor doping layer.
The channel layer 103 provides Process ba- sis to be subsequently formed the channel region of ring gate field-effect transistor.The channel layer 103
Material be iii-v element compound material so that carrier mobility with higher in channel region, wherein described
Iii-v element compound material is InGaAs, GaAs, InAs or InSb.
In the present embodiment, the material of the channel layer 103 is InGaAs, the channel layer 103 with a thickness of 10 angstroms to 300
Angstrom.
It is formed using metal organic vapor technique (MOPVE, Metal-organic vapor phase epitaxy)
The channel layer 103.During forming channel layer 103, growth of the crystal grain along 101 surface of buffer layer from bottom to top
Form the channel layer 103, and the partial sidewall surface of the closely sacrificial layer 102 of the channel layer 103, and 102 top of sacrificial layer
Surface not will do it the growth of crystal grain then.
The channel layer 103 is located at 101 surface of buffer layer, and the 101 material lattice constant of buffer layer is located at channel layer 103
Between 100 material lattice constant of material lattice constant and substrate, therefore can to play lattice constant buffered for the buffer layer 101
The effect crossed avoids generating lattice defect since lattice constant is mutated in channel layer 103, so that 103 matter of channel layer formed
It measures excellent.Also, the channel layer 103 is located at 102 partial sidewall surface of sacrificial layer, since 102 side wall line edge of sacrificial layer is thick
Rugosity is small, so that 103 side wall of channel layer of second area II also has lesser line edge roughness.
The semiconductor doping layer 104 provides Process ba- sis for the source region for forming ring gate field-effect transistor and drain region.
The material of the semiconductor doping layer 104 be doping InGaAs, the semiconductor doping layer 104 with a thickness of 10
Angstrom to 100 angstroms.In one embodiment, when the ring gate field-effect transistor of formation is NMOS device, the semiconductor doping layer 104
Material is the InGaAs of n-type doping, and the Doped ions of n-type doping are P or Sb.In another embodiment, the ring grid field effect of formation
When Ying Guanwei PMOS device, the material of the semiconductor doping layer 104 is the InGaAs of p-type doping, the Doped ions of p-type doping
For B or In.
In other embodiments, the material of the semiconductor doping layer can also be GaAs, InAs or InSb of doping.
The semiconductor doping layer 104 is formed using metal organic vapor technique, crystal grain is along 103 top of channel layer
The growth of surface from bottom to top, forms the semiconductor doping layer 104, and the semiconductor doping layer 104 closely sacrificial layer 102
Sidewall surfaces.Line edge roughness by sacrificial layer 102 in this present embodiment is small, therefore the semiconductor doping layer of second area II
104 side wall line edge roughness are also smaller.
Since rear extended meeting etches removal second area II part semiconductor doped layer 104, and the semiconductor doping layer 104
It is close with the material type of channel layer 103, etching technics to the Etch selectivity of semiconductor doped layer 104 and channel layer 103 compared with
Difference.In order to avoid channel layer 103 of the etching technics to second area II causes etching injury, in the present embodiment, in the channel
Etching barrier layer 105 is also formed between layer 103 and semiconductor doping layer 104.In the part subsequent etching removal second area II half
During conductor doped layer 104, the etching barrier layer 105 plays the role of etching stopping, and channel layer 103 is avoided to be etched
Damage.
The etching barrier layer 105 both plays the role of etching stopping, will not be to the electric property of ring gate field-effect transistor
Generate adverse effect.For this purpose, the material of the etching barrier layer 105 is that InP adopts with a thickness of 5 angstroms to 20 angstroms in the present embodiment
The etching barrier layer 105 is formed with metal organic vapor technique, and the also closely sacrificial layer of the etching barrier layer 105
102 partial sidewall surface.
It is top view with reference to Fig. 7 to Fig. 9, Fig. 7, Fig. 8 is the schematic diagram of the section structure that Fig. 7 is cut along cutting line AA1, Fig. 9
For the schematic diagram of the section structure that Fig. 7 is cut along cutting line BB1, in the semiconductor doping of the first area I and third region II
104 top surface of layer form graph layer 106, and the graph layer 106 is also located at the top of semiconductor doping layer 104 of external zones 120
Portion surface.
Exposure mask of the graph layer 106 as the semiconductor doping layer 104 of subsequent etching removal middle area 110, so that in
Between the channel layer 103 in area 110 be exposed.
In the present embodiment, the graph layer 106 be photoresist layer, formed the graph layer 106 processing step include:
104 top surface of semiconductor doping layer and 102 top surface of sacrificial layer form photoresist film；To the photoresist film into
Row exposure-processed and development treatment, removal are located at the photoresist film right above middle area 110, form the graph layer 106.
It is top view with reference to figures 10 to Figure 12, Figure 10, Figure 11 is the cross-section structure signal that Figure 10 is cut along cutting line AA1
Figure, Figure 12 are the schematic diagram of the section structure that Figure 10 is cut along cutting line BB1, (are with reference to Fig. 7 to Fig. 9) with the graph layer 106
Exposure mask, etching remove the semiconductor doping layer 104 of the middle area 110, retain the semiconductor doping layer of the external zones 120
104。
In the present embodiment, the semiconductor doping layer 104 of the middle area 110 is removed using dry etch process etching.
Due to being formed with etching barrier layer 105, the etching barrier layer between semiconductor doping layer 104 and channel layer 103
105 play the role of etching stopping, and dry etch process is avoided to cause etching injury to channel layer 103, so that channel layer 103 is always
Keep good performance.
In the present embodiment, the external zones 120 of the semiconductor doping layer 104 of first area I and closely first area I
Semiconductor doping layer 104 is used as source region (Source Area), is used to form the source electrode of ring gate field-effect transistor；Third region III's
The semiconductor doping layer 104 of the external zones 120 of semiconductor doping layer 104 and closely third region III is used as drain region (Drain
Area), it is used to form the drain electrode of ring gate field-effect transistor.In other embodiments, the semiconductor doping layer of first area and tight
The semiconductor doping layer of the external zones of first area is suffered as drain region, is used to form drain electrode；The semiconductor doping layer in third region,
And closely the semiconductor doping layer of the external zones in third region is used to form source electrode as source region.
Then, the removal graph layer 106 is further comprised the steps of:.In the present embodiment, the material of the graph layer 106 is light
Photoresist, is removed photoresist using wet process or cineration technics removes the graph layer 106.
It is top view with reference to figures 13 to Figure 14, Figure 13, Figure 14 is the cross-section structure signal that Figure 13 is cut along cutting line AA1
Figure, removes the sacrificial layer 102 (with reference to figures 10 to Figure 12), until exposing 101 top surface of buffer layer.
In the present embodiment, the material of the sacrificial layer 102 is metallo organic material, removes the sacrifice using cineration technics
Layer 102.
In a specific embodiment, it is 10 millitorrs to 1000 that the technological parameter of the cineration technics, which includes: chamber pressure,
Millitorr, N2Flow is 0sccm to 500sccm, O2Flow is 0sccm to 1000sccm, H2Flow is 0sccm to 200sccm, function
Rate is 100 watts to 2000 watts.
It is top view with reference to Figure 15 to Figure 17, Figure 15, Figure 16 is the cross-section structure signal that Figure 15 is cut along cutting line AA1
Figure, Figure 17 are the schematic diagram of the section structure that Figure 15 is cut along cutting line BB1, and etching removes the buffer layer of the second area II
101, until exposing 100 surface of substrate.
The buffer layer 101 of the second area II is removed, until 100 surface of substrate is exposed, to be subsequently formed grid knot
Structure is prepared.
The buffer layer 101 of the second area II is etched removal, so that 103 bottom surface of channel layer of second area II
The gate structure for being exposed, therefore being subsequently formed is except 103 top surface of channel layer and sidewall surfaces with second area II
Contact is outer, and the gate structure can also increase gate structure and channel with 103 bottom surface contact of channel layer of second area II
The contact area of layer 103.
In the present embodiment, in addition to the buffer layer 101 of etching removal second area II, also etching removes the portion first area I
Divide the buffer layer 101 of width, the buffer layer 101 of etching removal third region III partial width.It is advantageous in that: further increasing
Add 103 exposed area of channel layer, so that channel layer 103 and the contact area for the gate structure being subsequently formed become larger, that is,
The channel region of ring gate field-effect transistor and the contact area of gate structure become larger, therefore gate structure obtains the control ability of channel region
To raising, improve the electric property of ring gate field-effect transistor.
The buffer layer 101 of the second area II, also etching removal first are removed using isotropic etching technique etching
The buffer layer 101 of region I partial width and the buffer layer 101 of third region III partial width.
In the present embodiment, the processing step for removing aforementioned buffer layer 101 includes: firstly, using O2By buffering to be removed
Layer 101 aoxidizes；Then, the buffer layer 101 after oxidation is etched by removal using wet-etching technology.
In a specific embodiment, technological parameter buffer layer 101 to be removed aoxidized includes: O2Flow is
50sccm to 500sccm, chamber pressure are 10 millitorrs to 1000 millitorrs.The technological parameter of wet-etching technology includes: etching temperature
Degree be 0 degree Celsius to 80 degrees Celsius, etch liquids are sulfuric acid solution, wherein in sulfuric acid solution sulfuric acid and deionized water volume ratio
For 1:1, etching duration is 10 seconds to 600 seconds.
It is schematic diagram on the basis of Figure 16 referring to figs. 18 to Figure 19, Figure 18, Figure 19 is schematic diagram on the basis of Figure 17,
The gate structure of covering 101 sidewall surfaces of residual buffer layer, the gate structure are formed on 100 surface of substrate exposed
Around the channel layer 103 of the second area II, the gate structure also covers the semiconductor doping layer of the external zones 120
104 surfaces.
In the present embodiment, positioned at the gate structure sidewall on 100 surface of substrate and positioned at the semiconductor doping layer 104
The gate structure sidewall of top surface flushes.
Due to the buffer layer 101 of first area I partial width and 101 quilt of buffer layer of third region III partial width
Etching removal, and the gate structure for being located at 100 surface of substrate covers 101 sidewall surfaces of residual buffer layer, therefore, the present embodiment
In, the gate structure also covers 104 surface of first area I part semiconductor doped layer and the part third region III and partly leads
104 surface of body doped layer, so that the gate structure sidewall for being located at 100 surface of substrate is pushed up with semiconductor doping layer 104 is located at
The gate structure sidewall on portion surface flushes.
The gate structure includes: gate dielectric layer 107 and the gate electrode layer 109 positioned at 107 surface of gate dielectric layer.
The material of the gate dielectric layer 107 is silica, silicon nitride or high-k gate dielectric material, the high-k gate dielectric material
Refer to relative dielectric constant be greater than silica relative dielectric constant material, for example, LaO, AlO, BaZrO, HfZrO,
HfZrON, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3、Al2O3Or Si3N4.It is described
The material of gate electrode layer 109 is Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN or WSi.
It is also formed with protective layer 108 between the gate dielectric layer 107 and gate electrode layer 109, plays protection gate dielectric layer
107 effect, for example, the protective layer 108 can stop the metal ion in gate electrode layer 109 to diffuse to gate dielectric layer 107
It is interior.The material of the protective layer 108 is Ga2O3、In2O3、MoO、Pt、Ru、TaCNO、Ir、TaC、MoN、WN、TiN。
In the present embodiment, the material of the gate dielectric layer 107 is Al2O3, the grid are formed using atom layer deposition process and are situated between
Matter layer 107；The material of the gate electrode layer 109 is TaN, and the material of the protective layer 108 is TiN.
The processing step for forming the gate structure includes: to form covering residue on 100 surface of substrate exposed
The gate dielectric film of 101 sidewall surfaces of buffer layer, the gate dielectric film surround the channel layer 103 of the second area II, and described
Gate dielectric film also covers 104 surface of semiconductor doping layer of first area I, second area II and third region III；In the grid
Medium film surface forms protective film；Gate electrode film is formed in the protection film surface；It is formed initially on the gate electrode film surface
Mask layer；Patterned photoresist layer is formed in the original mask layer surface；Using the patterned photoresist layer as exposure mask,
It etches the original mask layer and forms hard mask layer；Then, it using the hard mask layer as exposure mask, etches the gate electrode film and is formed
Gate electrode layer 109 etches the protective film and forms protective layer 108, etches the gate dielectric film and forms gate dielectric layer 107.
It further comprises the steps of: and forms gate contact layer in the gate structure top surface；In partly leading for the first area I
104 surface of body doped layer forms source and drain contact layer；Source and drain is formed on 104 surface of semiconductor doping layer of the third region III
Contact layer.
The ring gate field-effect transistor formed in the present embodiment is fin field effect pipe, wherein positioned at the channel of second area II
Layer 103 is the fin of fin field effect pipe.The gate structure surround the channel layer 103 of the second area II, so that grid
Structure and the contact area of channel region are larger, and the gate structure is also located at 103 bottom surface of the first area part I channel layer
And 103 bottom surface of the third region part III channel layer, to further increase the contact surface of gate structure and channel region
Product, so that gate structure increases the control ability of channel region, to improve the electric property for the ring gate field-effect transistor to be formed.
Also, in the present embodiment, the side wall line edge roughness positioned at the channel layer 103 of second area II is small, so that ring
The channel region of gate field-effect transistor has good pattern, to further increase the electric property of ring gate field-effect transistor.Meanwhile this
In embodiment, the channel layer 103 of second area II does not undergo etching technics, avoids the pattern transfer errors of etching technics introducing
The problem of, further increase the position precision and pattern accuracy of channel region；And the channel layer 103 of second area II is not undergone
Etching technics avoids channel region by etching injury, so that the ring gate field-effect transistor function admirable formed.
Finally, the material of the channel region of ring gate field-effect transistor is InGaAs, i.e. the material of channel region is in the present embodiment
III-V compound material, the III-V compound material carrier mobility with higher, so that forming ring grid field
The performance of effect pipe is more superior.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of ring gate field-effect transistor characterized by comprising
Substrate is provided, the substrate includes the first area being arranged successively along first direction, second area and third region, described
Second area includes middle area and the external zones positioned at middle area two sides, wherein the orientation of the middle area and external zones
It is parallel with the first direction；
It sequentially forms positioned at the buffer layer of the substrate surface and positioned at the several arranged in parallel of second area buffer-layer surface
Sacrificial layer, and the orientation of the sacrificial layer is mutually perpendicular to the first direction；
The semiconductor doping layer positioned at the channel layer of the buffer-layer surface and positioned at the channel layer surface is sequentially formed,
The channel layer covers the partial sidewall surface of the sacrificial layer, and the semiconductor doping layer covers the part side of the sacrificial layer
Wall surface；
The semiconductor doping layer of the middle area is removed, the semiconductor for retaining the external zones, first area and third region is mixed
Diamicton；
The sacrificial layer is removed, the breaker topping surface is exposed；
Etching removes the buffer layer of the second area, until exposing substrate surface；
The gate structure of covering residual buffer layer sidewall surfaces, the gate structure ring are formed in the substrate surface exposed
Around the channel layer of the second area, the gate structure also covers the semiconductor doping layer surface of external zones.
2. the forming method of ring gate field-effect transistor as described in claim 1, which is characterized in that remove secondth area in etching
While the buffer layer in domain, also etching removes the buffer layer of first area partial width and the buffering of third region partial width
Layer.
3. the forming method of ring gate field-effect transistor as claimed in claim 2, which is characterized in that the gate structure also covers
One region part semiconductor adulterates layer surface and third region part semiconductor adulterates layer surface.
4. the forming method of ring gate field-effect transistor as claimed in claim 1 or 3, which is characterized in that be located at the substrate surface
Gate structure sidewall be located at the semiconductor doping layer top surface gate structure sidewall flush.
5. the forming method of ring gate field-effect transistor as described in claim 1, which is characterized in that the substrate is InP substrate；Institute
The material for stating buffer layer is InP.
6. the forming method of ring gate field-effect transistor as described in claim 1, which is characterized in that the material of the channel layer is
Iii-v element compound material.
7. the forming method of ring gate field-effect transistor as claimed in claim 6, which is characterized in that the iii-v element compounds
Object material is InGaAs, GaAs, InAs or InSb.
8. the forming method of ring gate field-effect transistor as described in claim 1, which is characterized in that use metal organic vapor
Technique forms the channel layer；The semiconductor doping layer is formed using metal organic vapor technique.
9. the forming method of ring gate field-effect transistor as described in claim 1, which is characterized in that the material of the semiconductor doping layer
Material is the InGaAs of n-type doping；Alternatively, the material of the semiconductor doping layer is the InGaAs of p-type doping.
10. the forming method of ring gate field-effect transistor as described in claim 1, which is characterized in that the buffer layer with a thickness of
10 angstroms to 50 angstroms, the channel layer with a thickness of 10 angstroms to 300 angstroms, the semiconductor doping layer with a thickness of 10 angstroms to 100 angstroms.
11. the forming method of ring gate field-effect transistor as described in claim 1, which is characterized in that the channel layer with it is described
Etching barrier layer is also formed between semiconductor doping layer.
12. the forming method of ring gate field-effect transistor as claimed in claim 11, which is characterized in that the material of the etching barrier layer
Material is InP.
13. the forming method of ring gate field-effect transistor as described in claim 1, which is characterized in that the material of the sacrificial layer is
Metallo organic material.
14. the forming method of ring gate field-effect transistor as claimed in claim 13, which is characterized in that the material of the sacrificial layer is
Zirconium naphthenate, nickel naphthenate, aphthenic acids tungsten or aphthenic acids titanium.
15. the forming method of ring gate field-effect transistor as claimed in claim 13, which is characterized in that formed the channel layer it
Before, it further comprises the steps of: and hydrogenation treatment is carried out to the sacrificial layer, reduce the line edge roughness of sacrificial layer.
16. the forming method of ring gate field-effect transistor as claimed in claim 15, which is characterized in that the hydrotreated technique
Parameter includes: H2Flow is 100sccm to 1000sccm, and chamber pressure is 0.1atm to 2atm, and chamber temp is 100 degrees Celsius
To 1000 degrees Celsius, handling duration is 10 minutes to 5 hours.
17. the forming method of ring gate field-effect transistor as described in claim 1, which is characterized in that remove the half of the middle area
The processing step of conductor doped layer includes: the semiconductor doping layer top surface formation figure in the first area and third region
Shape layer, and the graph layer is also located at the semiconductor doping layer top surface of external zones；Using the graph layer as exposure mask, etching is gone
Except the semiconductor doping layer of the middle area；Remove the graph layer.
18. the forming method of ring gate field-effect transistor as described in claim 1, which is characterized in that the gate structure includes: grid
Dielectric layer and gate electrode layer positioned at gate dielectric layer surface.
19. the forming method of ring gate field-effect transistor as claimed in claim 18, which is characterized in that the material of the gate dielectric layer
For high-k gate dielectric material.
20. the forming method of ring gate field-effect transistor as claimed in claim 18, which is characterized in that the material of the gate electrode layer
For Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN or WSi.
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