CN106486453A - A kind of capital interconnection kenel semiconductor packaging structure and its manufacture method - Google Patents
A kind of capital interconnection kenel semiconductor packaging structure and its manufacture method Download PDFInfo
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- CN106486453A CN106486453A CN201510525891.7A CN201510525891A CN106486453A CN 106486453 A CN106486453 A CN 106486453A CN 201510525891 A CN201510525891 A CN 201510525891A CN 106486453 A CN106486453 A CN 106486453A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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Abstract
The present invention discloses a kind of capital interconnection (PTI) kenel semiconductor packaging structure and its manufacture method of use molding interconnection substrates technique, and this semiconductor packaging structure comprises a reconfiguration line layer being formed in support plate plane, a plurality of metal column being arranged at reconfiguration line layer, a chip being arranged in reconfiguration line layer and a molding substrate layer.Molding substrate layer is formed in support plate plane, the lower surface of molding substrate layer is defined in support plate plane, so that reconfiguration line layer is depressed in molding substrate layer, the package thickness of molding substrate layer is more than the chip rational height of chip, so that chip is coated in molding substrate layer and metal column is coated on the periphery of molding substrate layer.Metal column has the top not coated by molding substrate layer.Therefore, can reach POP and encapsulate the ultra-thin effect with miniaturization, longitudinal guiding path thin space of encapsulation storehouse of storehouse, and the zero clearance that POP encapsulates storehouse can be completed.
Description
Technical field
The present invention is related to semiconductor die package field, and the capital particularly with regard to a kind of use molding interconnection substrates technique interconnects (PTI) kenel semiconductor packaging structure and its manufacture method, can be applicable to POP encapsulation storehouse.
Background technology
POP (Package-On-Package) encapsulates the stereo-stacking composite construction that storehouse is multiple semiconductor packaging structures, and a top top semiconductor packaging structure can be bonded on a lower section base semiconductor packaging structure on surface.Longitudinal joint element between two packaging structures is the soldered ball of top semiconductor packaging structure, therefore can produce a POP storehouse gap.And, the molding colloid of base semiconductor packaging structure is formed on a substrate, a molding height can be produced.Neighboring area cladding soldered ball in molding colloid, using as longitudinal breakover element.Soldered ball was to be fixed on substrate with planting ball mode before not being wrapped by, and after molding cladding soldered ball, then so that soldered ball local is manifested with laser drill (laser drill) technique.During POP encapsulation storehouse, what the soldered ball of top semiconductor packaging structure was bonded to be wrapped by soldered ball in base semiconductor packaging structure appears surface.It is wrapped by the sphere diameter of soldered ball and spacing will limit quantity and the arranging density of longitudinal joint element.
Refer to Fig. 1, the base semiconductor packaging structure 300 that can operate with POP encapsulation storehouse known in another kind comprises an adhesive body 310, a plurality of filling solder 320, a chip 330, a circuit base plate 340 and a plurality of soldered ball 390.This circuit base plate 340 has multilayer line and the line constructions such as the hole that electrically conducts 343.This chip 330 can be using a upper surface 342 of plurality of bump 331 chip bonding to this circuit base plate 340.This adhesive body 310 is formed on this upper surface 342 of this circuit base plate 340, to seal this chip 330.The periphery of this adhesive body 310 forms a plurality of molding perforations 311 with bore mode, runs through this adhesive body 310, to manifest the periphery connection pad of this circuit base plate 340.Those filling solders 320 are formed in those molding perforations 311, are engaged with the soldered ball that POP encapsulates storehouse.Those soldered balls 390 are engaged in the lower surface 341 of this circuit base plate 340.In more advanced POP encapsulation storehouse, package thickness is that base semiconductor packaging structure that is thinner and compact in size and can reach the longitudinal guiding path of micro- spacing arrangement is expected to.Additionally, POP encapsulation storehouse gap is also expected to reduce further.
Content of the invention
Above-mentioned in order to solve the problems, such as, present invention is primarily targeted at providing a kind of capital interconnection (PTI) kenel semiconductor packaging structure and its manufacture method of use molding interconnection substrates technique, eliminate the prominent jointing altitude of the molding thickness on known substrate and POP encapsulation storehouse, and can be utilized the molding interconnection substrates technique repeating to implement reach POP encapsulation storehouse be ultra-thin with miniaturization kenel, and to encapsulate longitudinal guiding path of storehouse can be also micro- spacing arrangement.
A time purpose of the present invention is to provide a kind of capital of use molding interconnection substrates technique to interconnect (PTI) kenel semiconductor packaging structure and its manufacture method, and reach POP to encapsulate storehouse is zero clearance and the effect omitting package thickness on substrate.
The object of the invention to solve the technical problems employs the following technical solutions to realize.The present invention discloses capital interconnection (PTI) kenel semiconductor packaging structure of a kind of use molding interconnection substrates technique, comprises one first reconfiguration line layer, a plurality of first metal column, one first chip and one first molding substrate layer.This first reconfiguration line layer is formed in a support plate plane, and this first reconfiguration line layer comprises a plurality of first fan-in pads and a plurality of first fan-out pads.Those first metal columns are arranged on those the first fan-out pads.This first chip is arranged in this first reconfiguration line layer and is electrically connected to those the first fan-in pads.This the first molding substrate layer is formed in this support plate plane, this the first molding substrate layer has one first lower surface and one first upper surface, this first lower surface is defined in this support plate plane, so that this first reconfiguration line layer is depressed in this first lower surface of this first molding substrate layer, this the first molding substrate layer is more than one first chip rational height of this first chip by one first package thickness of this first upper surface to this first lower surface, so that this first chip is coated in this first molding substrate layer and those first metal columns are coated on the periphery of this first molding substrate layer.Those first metal columns have a plurality of the first tops not coated by this first molding substrate layer.Whereby, can reach POP and encapsulate the ultra-thin effect with miniaturization, longitudinal guiding path thin space of encapsulation storehouse of storehouse, and zero clearance or the microgap joint that POP encapsulates storehouse can be completed.The present invention separately discloses a kind of manufacture method of capital interconnection (PTI) kenel semiconductor packaging structure of use molding interconnection substrates technique.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In aforesaid semiconductor packaging structure, this first chip is by a plurality of first projection chip bondings to those the first fan-in pads.
In aforesaid semiconductor packaging structure, one first post rational height of those the first metal columns is less than this first package thickness of this first molding substrate layer but is not less than this first chip rational height of this first chip, to provide the engageable post jamb of interior miniature compared with many areas.
In aforesaid semiconductor packaging structure, this the first molding substrate layer has more a plurality of the first molding access openings being formed at this first upper surface, those first tops of those the first metal columns and the neighbouring post jamb of those the first metal columns are emerging in those the first molding access openings, therefore those first metal columns will not protrude from this first upper surface of this first molding substrate layer and provide the post composition surface inside contracting.
In aforesaid semiconductor packaging structure, those the first molding access openings are not through this first molding substrate layer, and the depth of those the first molding access openings is more than this first molding substrate layer cladding thickness on this first chip, to maintain the perpendicularity of those the first metal columns.
In aforesaid semiconductor packaging structure, a plurality of soldered balls can be additionally comprised, be engaged in those the first fan-out pads and protrude from this first lower surface, for outer engagement.
In aforesaid semiconductor packaging structure, one second reconfiguration line layer, a plurality of second metal column, one second chip and one second molding substrate layer can be additionally comprised.This second reconfiguration line layer is formed on this first upper surface of this first molding substrate layer, this second reconfiguration line layer comprises a plurality of second fan-in pads and a plurality of second fan-out pads, and wherein those the second fan-out pads are bonded to those first tops of those the first metal columns and the neighbouring post jamb of those the first metal columns.Those second metal columns are arranged on those the second fan-out pads.This second chip is arranged in this second reconfiguration line layer and is electrically connected to those the second fan-in pads.This second molding substrate layer is formed on this first upper surface of this first molding substrate layer, this first upper surface is in order to define one second lower surface of this second molding substrate layer, so that this second reconfiguration line layer is depressed in this second lower surface of this second molding substrate layer, one second package thickness of this second molding substrate layer is more than one second chip rational height of this second chip, so that this second chip is coated in this second molding substrate layer and those second metal columns are coated on the periphery of this second molding substrate layer.Those second metal columns have a plurality of the second tops not coated by this second molding substrate layer, reach the zero clearance that POP encapsulates storehouse whereby, can successively be assembled into more encapsulation storehouse bodies with substrate thickness.
In aforesaid semiconductor packaging structure, those the second fan-out pad systems are cover shape pad, and entangle those first tops of those those the first metal columns and the neighbouring post jamb of those the first metal columns, with those first tops avoiding those the first metal columns, bond breakage occur.
By above-mentioned technological means, the present invention can provide a kind of semiconductor packaging structure, it is made in MIS substrate by the first reconfiguration line layer and forms the integration technology of metal column to form molding substrate layer and copper plating (Cu plating), separately via laser drill (laser
Drill) upper end of metal column is emerging in the molding access opening of molding substrate layer mode, the connection on molding substrate layer can be routed in as the second reconfiguration line layer, can rejoin thereon chip and molding, to form zero clearance POP encapsulation storehouse, or the upper end that inside contracts of metal column is available for the soldered ball of another top semiconductor packaging structure and engages, to reach microgap POP encapsulation storehouse, achievable POP encapsulates the effect of the thin space longitudinal direction guiding path that storehouse is compact in size, POP encapsulates stack thickness slimming and POP encapsulation storehouse.Therefore, the present invention can make POP encapsulation storehouse body using the molding interconnection substrates technique repeating to implement.
Brief description
Fig. 1 can operate with, known in being, the schematic cross-section that POP encapsulates the base semiconductor packaging structure of storehouse.
Fig. 2 is according to the first embodiment of the present invention, and a kind of capital of use molding interconnection substrates technique interconnects the schematic cross-section of (PTI) kenel semiconductor packaging structure.
Fig. 3 A to Fig. 3 E is according to the first embodiment of the present invention, the schematic cross-section of this semiconductor packaging structure each element formed in the key step of first time molding interconnection substrates technique.
Fig. 4 is according to the second embodiment of the present invention, and a kind of capital of use molding interconnection substrates technique interconnects the schematic cross-section of (PTI) kenel semiconductor packaging structure.
Fig. 5 A to Fig. 5 E is according to the second embodiment of the present invention, the schematic cross-section of this semiconductor packaging structure each element formed in the key step of second molding interconnection substrates technique.
Fig. 6 is according to the second embodiment of the present invention, is combined into the schematic cross-section of a package stack stackware by this semiconductor packaging structure.
Description of reference numerals
T1 first package thickness
T2 second package thickness
H1 the first chip rational height H2 the first post rational height
H3 the second chip rational height H4 the second post rational height
10 temporary transient support plates
11 support plate planes
20 top storehouse packaging structure 21 substrates
22 adhesive bodies
23 soldered balls
100 semiconductor packaging structures
110 first reconfiguration line layer 111 first fan-in pad
112 first fan-out pads
120 first metal column 121 first top
130 first chip 131 first projection
132 first solders
140 first molding substrate layer 141 first lower surface
142 first upper surface 143 first molding access opening
190 soldered balls
200 semiconductor packaging structures
250 second reconfiguration line layer 251 second fan-in pad
252 second fan-out pads
260 second metal column 261 second top
270 second chip 271 second projection
272 second solders
280 second molding substrate layer 282 second upper surface
283 second molding access openings
300 semiconductor packaging structures
310 adhesive body 311 molding perforation
320 filling perforation solders
330 chip 331 projection
340 circuit base plate 341 lower surface
342 upper surface 343 line construction
390 soldered balls.
Specific embodiment
Describe embodiments of the invention below in conjunction with appended accompanying drawing in detail, so it should be noted that, those diagrams are the schematic diagram of simplification, basic framework or the implementation of the present invention to be only described with illustrative method, therefore only show the element relevant with this case and syntagmatic, element shown by figure is not done equal proportion and is drawn with the actual number implemented, shape, size, some dimension scales and other relative dimensions ratios or exaggerated or simplification is processed, to provide clearer description.The actual number implemented, shape and dimension scale are a kind of design of putting property of choosing, and detailed component placement is likely more complexity.
According to the first embodiment of the present invention, capital interconnection (PTI) kenel semiconductor packaging structure 100 of a kind of use molding interconnection substrates technique is illustrated in the schematic cross-section of Fig. 2 and the schematic cross-section of Fig. 3 A to Fig. 3 E each element formed in the key step of first time molding interconnection substrates technique.Capital interconnection (PTI) kenel semiconductor packaging structure 100 of a kind of use molding interconnection substrates technique, it comprises one first reconfiguration line layer 110, a plurality of first metal column 120, one first chip 130 and one first molding substrate layer 140.
As shown in Fig. 2 this first reconfiguration line layer 110 is formed in a support plate plane 11, this first reconfiguration line layer 110 comprises a plurality of first fan-in pads 111 and a plurality of first fan-out pads 112.This support plate plane 11 can provide (as shown in Figure 3A) by a temporary transient support plate 10, and completing for the first time or more times after molding interconnection substrates technique, this temporary transient support plate 10 should be removed.Those the first fan-in pads 111 belong to a part for this first reconfiguration line layer 110, the spacing of those the first fan-in pads 111 should be less than the spacing of those the first fan-out pads 112, but within non-exclusively the spacing of those the first fan-out pads 112 still can be controlled in 200 microns.Those the first fan-out pads 112 also belong to a part for this first reconfiguration line layer 110, connect those the first fan-in pads 111 and those the first fan-out pads 112 using the corresponding line of this first reconfiguration line layer 110.This first reconfiguration line layer 110 utilizes sputter (or physical vapour deposition (PVD)), plating and the integrated circuit technology of the semiconductor crystal wafers such as pattern etched (or quasiconductor panel) to be made.Generally this first reconfiguration line layer 110 is complex metal layer, such as the gold of the upper arrangement/nickel copper layer bottom of by.The primary conductive layer material of this first reconfiguration line layer 110 is copper, aluminum or its alloy.About below 50 microns, but because this first reconfiguration line layer 110 is the kenel being embedded into bottom surface in this first molding substrate layer 140, therefore the thickness of this first reconfiguration line layer 110 can be not limited the thickness of this first reconfiguration line layer 110.
Those first metal columns 120 are arranged on those the first fan-out pads 112.Those first metal columns 120 can be made using electro-plating method.The shape of those the first metal columns 120 can be circular cylinder, four sides cylinder, hexahedro cylinder or multi-faceted column.Those first metal columns 120 can be single layer structure or multiple structure.The main material of those the first metal columns 120 can be copper, aluminum or its alloy, is selected with copper post for preferable.The height of those the first metal columns 120 should be less than the thickness of this first molding substrate layer 140.The fusing point of those the first metal columns 120 should be higher than that solder melt point.
This first chip 130 is arranged in this first reconfiguration line layer 110 and is electrically connected to those the first fan-in pads 111.This first chip 130 is the semiconductor element with integrated circuit.Specifically, this first chip 130 by the chip bonding of a plurality of first projection 131 to those the first fan-in pads 111.A plurality of first solders 132 are can be utilized to engage those first projections 131 and those the first fan-in pads 111, so as to reaching being mechanically fixed and being electrically connected with of this first chip 130.Or, this first chip 130 can be utilized a viscous crystalline substance glue-line to be arranged in this first reconfiguration line layer 110, and is electrically connected to those the first fan-in pads 111 using the bonding wire that routing is formed.Under the obstruct of this first reconfiguration line layer 110, those first solders 132 or viscous crystalline substance glue-line will not be revealed in outside this first molding substrate layer 140.
This first molding substrate layer 140 is formed in this support plate plane 11, this the first molding substrate layer 140 has one first lower surface 141 and one first upper surface 142, this first lower surface 141 is defined in this support plate plane 11, so that this first reconfiguration line layer 110 is depressed in this first lower surface 141 of this first molding substrate layer 140.In other words, the upper surface of this first molding substrate layer 140 and side are coated by this first molding substrate layer 140.This first lower surface 141 copline of the lower surface of this first molding substrate layer 140 and this first molding substrate layer 140 is in this support plate plane 11.The material of this first molding substrate layer 140 is the heat-curable compounds of electric insulation, and the formation of this first molding substrate layer 140 can be using the method such as compression molding or transfer molding.The thickness of this first molding substrate layer 140 is equivalent to known package substrate thickness, about between 0.15 ~ 0.5 millimeter (mm).
And, this the first molding substrate layer 140 is more than one first chip rational height H1 of this first chip 130 by one first package thickness T1 of this first upper surface 142 to this first lower surface 141, so that this first chip 130 is coated in this first molding substrate layer 140 and those first metal columns 120 are coated on the periphery of this first molding substrate layer 140.Those first metal columns 120 have a plurality of the first tops 121 not coated by this first molding substrate layer 140.
Additionally, those the first fan-out pads 112 is partly or entirely ball pad, this semiconductor packaging structure 100 can additionally comprise a plurality of soldered balls 190, be engaged in those the first fan-out pads 112 and protrude from this first lower surface 141, for outer engagement.
Therefore, the present invention provides capital interconnection (PTI) kenel semiconductor packaging structure of a kind of use molding interconnection substrates technique, eliminate the prominent jointing altitude of the molding thickness on known substrate and POP encapsulation storehouse, and can be utilized molding interconnection substrates technique (being detailed later) repeating to implement can reach POP encapsulation storehouse be ultra-thin with miniaturization kenel, and to encapsulate longitudinal guiding path of storehouse can be also micro- spacing arrangement.
In the present embodiment, one first post rational height H2 of those the first metal columns 120 is less than this first package thickness T1 of this first molding substrate layer 140 but is not less than this first chip rational height H1 of this first chip 130, to provide the engageable post jamb of interior miniature compared with many areas.
Preferably, this the first molding substrate layer 140 has more a plurality of the first molding access openings 143 being formed at this first upper surface 142, those first tops 121 and the neighbouring post jamb of those the first metal columns 120 of those the first metal columns 120 are emerging in those the first molding access openings 143, therefore those first metal columns 120 will not protrude from this first upper surface 142 of this first molding substrate layer 140 and provide the post composition surface inside contracting.Therefore the composition surface of POP encapsulation storehouse is on-plane surface and bonding area can be expanded according to the depth of those the first molding access openings 143.Generally those first metal columns 120 are adjacent to appear that post jamb length is not more than the first post rational height H2 of those the first metal columns 120 1/2nd of those the first tops 121.
Preferably, those the first molding access openings 143 are not through this first molding substrate layer 140, and the depth of those the first molding access openings 143 be more than cladding thickness on this first chip 130 for this first molding substrate layer 140 (i.e. the first package thickness T1 of this first molding substrate layer 140 deduct this first chip 130 this first chip rational height H1 and deduct this first reconfiguration line layer 110 thickness gained residual value), to maintain the perpendicularity of those the first metal columns 120.In the present embodiment, those the first molding access opening 143 reverse taper hole.
Capital with regard to above-mentioned use molding interconnection substrates technique interconnects the schematic cross-section of each element formed in the key step in first time molding interconnection substrates technique that the manufacture method of (PTI) kenel semiconductor packaging structure 100 is found in as shown in Fig. 3 A to Fig. 3 E, the explanation of its key step as after.
First, as shown in Figure 3A, form this first reconfiguration line layer 110 using the integrated circuit technology of semiconductor crystal wafer (or quasiconductor panel) in this support plate plane 11, this first reconfiguration line layer 110 comprises those the first fan-in pads 111 and those the first fan-out pads 112, and this support plate plane 11 is provided by this temporary transient support plate 10.This temporary transient support plate 10 can for wafer carrying system (Wafer Support System,
WSS) or can be panel bearing system (Panel Support System, PSS), in device, there is no carrying board structure, in technique, be modeled as a semiconductor crystal wafer that can make PROCESS FOR TREATMENT or quasiconductor panel using this temporary transient support plate 10.
Afterwards, as shown in Figure 3 B, those first metal columns 120 are arranged on those the first fan-out pads 112 with plating mode.Afterwards, as shown in Figure 3 C, this first chip 130 is arranged in chip bonding mode and and be electrically connected to those the first fan-in pads 111 in this first reconfiguration line layer 110.
Afterwards，As shown in Figure 3 D，This first molding substrate layer 140 is formed in this support plate plane 11 with known wafer molding or panel molding mode，This first molding substrate layer 140 has this first lower surface 141 and this first upper surface 142，This first lower surface 141 is defined in this support plate plane 11，So that this first reconfiguration line layer 110 is depressed in this first lower surface 141 of this first molding substrate layer 140，This first molding substrate layer 140 is more than this first chip rational height H1 of this first chip 130 by this first package thickness T1 of this first upper surface 142 to this first lower surface 141，So that this first chip 130 is coated in this first molding substrate layer 140 and those first metal columns 120 are coated on the periphery of this first molding substrate layer 140.
Afterwards, as shown in FIGURE 3 E, execute one first perforate operation, available laser drill or not enough Exposure mode make those first metal columns 120 have the first top 121 that those are not coated by this first molding substrate layer 140.In the present embodiment, method for drilling holes is preferable, and this first molding substrate layer 140 can be selected for non-photo-sensing material.In this step, this the first molding substrate layer 140 has more a plurality of the first molding access openings 143 being formed at this first upper surface 142, and those first tops 121 and the neighbouring post jamb of those the first metal columns 120 of those the first metal columns 120 are emerging in those the first molding access openings 143.And, the position that appears of those the first metal columns 120 does not protrude from this first molding substrate layer 140.Afterwards, this first molding substrate layer 140 and this temporary transient support plate 10 are separated.Separation method can be selected for UV and irradiates, so that the viscosity of this temporary transient support plate 10 disappears, and then peels off this temporary transient support plate 10 and this first molding substrate layer 140.Finally, a plurality of soldered balls 190 are set in those fan-out pads 112 so as to protrude from this first lower surface 141 of this first molding substrate layer 140, just can produce semiconductor packaging structure 100 as shown in Figure 2.
In addition, a kind of capital of use molding interconnection substrates technique that the present invention discloses interconnects the manufacture method of (PTI) kenel semiconductor packaging structure 100, the molding interconnection substrates technique of one or more times also can be repeated on this first molding substrate layer 140, molding interconnection substrates technique comprises to form the electroforming step of reconfiguration line layer each time, the electroforming step of the metal column of setting such as copper post, the chip bonding step of setting chip, form the epoxy glue material pressing mold step of molding substrate layer and the opening step end of metal column being revealed using laser drill (Laser drill) mode.The molding interconnection substrates technique repeating can reach the ultrathin POP encapsulation stack structure of be intended to number of chips storehouse.The copper post end finally exposed, more can again with other semiconductor package body storehouses.
According to the second embodiment of the present invention, another kind of capital interconnection (PTI) kenel semiconductor packaging structure 200 using molding interconnection substrates technique is illustrated in the schematic cross-section of Fig. 4, Fig. 5 A to Fig. 5 E schematic cross-section of each element formed in the key step of second molding interconnection substrates technique and Fig. 6 is combined into the schematic cross-section of a package stack stackware by this semiconductor packaging structure 200, wherein represent, identical detail characteristic repeat no more with the element of function with the element figure number of first embodiment corresponding to first embodiment same names.A kind of capital of use molding interconnection substrates technique interconnects (PTI) kenel semiconductor packaging structure 200 except one first reconfiguration line layer 110, a plurality of first metal column 120, one first chip 130 and the one first molding substrate layer 140 being included in the formation of first time molding interconnection substrates technique, and this semiconductor packaging structure 200 further includes one second reconfiguration line layer 250, a plurality of second metal column 260, one second chip 270 and the one second molding substrate layer 280 being formed in second molding interconnection substrates technique.
As shown in Figure 4, this second reconfiguration line layer 250 is formed on this first upper surface 142 of this first molding substrate layer 140, this second reconfiguration line layer 250 comprises a plurality of second fan-in pads 251 and a plurality of second fan-out pads 252, and wherein those the second fan-out pads 252 are bonded to those first tops 121 of those the first metal columns 120.Those second metal columns 260 are arranged on those the second fan-out pads 252.This second chip 270 is arranged in this second reconfiguration line layer 250 and is electrically connected to those the second fan-in pads 251.It is preferred that those second metal columns 260 have one second post rational height H4, it is less than one first package thickness T2 of this second molding substrate layer 280 but the one first chip rational height H3 not less than this first chip 270.
As shown in Figure 4 again, this the second molding substrate layer 280 is formed on this first upper surface 142 of this first molding substrate layer 140, this first upper surface 142 is in order to define one second lower surface of this second molding substrate layer 280, so that this second reconfiguration line layer 250 is depressed in this second lower surface of this second molding substrate layer 280, second package thickness T2 of this second molding substrate layer 280 is more than the second chip rational height H3 of this second chip 270, so that this second chip 270 is coated in this second molding substrate layer 280 and those second metal columns 260 are coated on the periphery of this second molding substrate layer 280.Those second metal columns 260 have a plurality of the second tops 261 not coated by this second molding substrate layer 280, reach the zero clearance that POP encapsulates storehouse whereby, can successively be assembled into the encapsulation storehouse body of more substrate thickness.Specifically, this the first molding substrate layer 280 has more a plurality of the second molding access openings 283 being formed at this second upper surface 282, and those second tops 261 and the neighbouring post jamb of those the second metal columns 260 of those the second metal columns 260 are emerging in those the second molding access openings 283.Generally those second metal columns 260 are adjacent to appear that post jamb length is not more than the second post rational height H4 of those the second metal columns 260 1/2nd of those the second tops 261.
Therefore, can reach POP to encapsulate storehouse by above-mentioned semiconductor packaging structure 200 is zero clearance and the effect omitting package thickness on substrate.
It is preferred that those the second fan-out pads 252 are cover shape pad, and entangle those first tops 121 of those those the first metal columns 120 and the neighbouring post jamb of those the first metal columns 120, bond breakage is occurred with those first tops 121 avoiding those the first metal columns 120.The joint post jamb of those the first metal columns 120 can be by the severity control of this first molding access opening 143.
Manufacture method with regard to capital interconnection (PTI) kenel semiconductor packaging structure 200 of above-mentioned use molding interconnection substrates technique is found in the schematic cross-section of each element formed in the key step of second molding interconnection substrates technique as shown in Fig. 5 A to Fig. 5 E.Before the rear and first embodiment of second molding interconnection substrates process implementing step of the first perforate operation in first embodiment separates this first molding substrate layer 140 and the step of this temporary transient support plate 10, the key step explanation of second molding interconnection substrates technique as after.
First, as shown in Figure 5A, form this second reconfiguration line layer 250 on this first upper surface 142 of this first molding substrate layer 140, this second reconfiguration line layer 250 comprises those the second fan-in pads 251 and those the second fan-out pads 252, and wherein those the second fan-out pads 252 are bonded to those first tops 121 of those the first metal columns 120 and the neighbouring post jamb of those the first metal columns 120.Afterwards, as shown in Figure 5 B, those second metal columns 260 are set on those the second fan-out pads 252.Afterwards, as shown in Figure 5 C, this second chip 270 is set in this second reconfiguration line layer 250, and makes this second chip 270 be electrically connected to those the second fan-in pads 251.
Afterwards, as shown in Figure 5 D, form this second molding substrate layer 280 on this first upper surface 142 of this first molding substrate layer 140, this first upper surface 142 is in order to define one second lower surface of this second molding substrate layer 280, so that this second reconfiguration line layer 250 is depressed in this second lower surface of this second molding substrate layer 280, one second package thickness T2 of this second molding substrate layer 280 is more than one second chip rational height H3 of this second chip 270, so that this second chip 270 is coated in this second molding substrate layer 280 and those second metal columns 260 are coated on the periphery of this second molding substrate layer 280.
Afterwards, as shown in fig. 5e, execution one second perforate operation is so that those the second metal columns 260 have the second top 261 that those are not coated by this second molding substrate layer 280.In this step, this the second molding substrate layer 280 has more a plurality of the second molding access openings 283 being formed at this second upper surface 282, and those second tops 261 and the neighbouring post jamb of those the second metal columns 260 of those the second metal columns 260 are emerging in those the second molding access openings 283.Afterwards, this first molding substrate layer 140 and this temporary transient support plate 10 are separated.Finally, a plurality of soldered balls 190 are set in those fan-out pads 112, just can produce semiconductor packaging structure 200 as shown in Figure 4.
As shown in fig. 6, a top storehouse packaging structure 20 can be bonded on this semiconductor packaging structure 200 on surface.This top storehouse packaging structure 20 comprises envelope in a substrate 21, the adhesive body 22 of chip and a plurality of soldered ball 23 under this substrate 21.Those soldered balls 23 are in alignment with those those the second molding channel holes 283, and make those soldered balls 23 be bonded to those second tops 261 of those the second metal columns 260 and the neighbouring post jamb of those the second metal columns 260 using reflow mode.
Above disclosed be only present pre-ferred embodiments, certainly the interest field of the present invention, the equivalent variations therefore made according to the claims in the present invention can not be limited with this, still fall within the scope that the present invention is covered.
Claims (10)
1. a kind of capital interconnection kenel semiconductor packaging structure is it is characterised in that it comprises：
One first reconfiguration line layer, is formed in a support plate plane, and this first reconfiguration line layer comprises a plurality of first fan-in pads and a plurality of first fan-out pads；
A plurality of first metal columns, are arranged on those the first fan-out pads；
One first chip, is arranged in this first reconfiguration line layer and is electrically connected to those the first fan-in pads；And
One first molding substrate layer, it is formed in this support plate plane, this the first molding substrate layer has one first lower surface and one first upper surface, this first lower surface is defined in this support plate plane, so that this first reconfiguration line layer is depressed in this first lower surface of this first molding substrate layer, this the first molding substrate layer is more than one first chip rational height of this first chip by one first package thickness of this first upper surface to this first lower surface, so that this first chip is coated in this first molding substrate layer and those first metal columns are coated on the periphery of this first molding substrate layer；
Wherein, those first metal columns have a plurality of the first tops not coated by this first molding substrate layer.
2. capital as claimed in claim 1 interconnects kenel semiconductor packaging structure, it is characterized in that, this the first molding substrate layer has more a plurality of the first molding access openings being formed at this first upper surface, and those first tops of those the first metal columns and the neighbouring post jamb of those the first metal columns are emerging in those the first molding access openings.
3. capital as claimed in claim 2 interconnects kenel semiconductor packaging structure, it is characterized in that, those the first molding access openings are not through this first molding substrate layer, and the depth of those the first molding access openings is more than this first molding substrate layer cladding thickness on this first chip.
4. the capital interconnection kenel semiconductor packaging structure as described in claim 1,2 or 3, it is characterized in that, one first post rational height of those the first metal columns is less than this first package thickness of this first molding substrate layer but is not less than this first chip rational height of this first chip.
5. capital as claimed in claim 1 interconnection kenel semiconductor packaging structure it is characterised in that this first chip by a plurality of first projection chip bondings to those the first fan-in pads.
6. capital interconnection kenel semiconductor packaging structure as claimed in claim 1, it is characterised in that additionally comprising a plurality of soldered balls, is engaged in those the first fan-out pads and protrudes from this first lower surface.
7. capital interconnection kenel semiconductor packaging structure as claimed in claim 1 is it is characterised in that additionally comprise：
One second reconfiguration line layer, it is formed on this first upper surface of this first molding substrate layer, this second reconfiguration line layer comprises a plurality of second fan-in pads and a plurality of second fan-out pads, and wherein those the second fan-out pads are bonded to those first tops of those the first metal columns and the neighbouring post jamb of those the first metal columns；
A plurality of second metal columns, are arranged on those the second fan-out pads；
One second chip, is arranged in this second reconfiguration line layer and is electrically connected to those the second fan-in pads；And
One second molding substrate layer, it is formed on this first upper surface of this first molding substrate layer, this first upper surface is in order to define one second lower surface of this second molding substrate layer, so that this second reconfiguration line layer is depressed in this second lower surface of this second molding substrate layer, one second package thickness of this second molding substrate layer is more than one second chip rational height of this second chip, so that this second chip is coated in this second molding substrate layer and those second metal columns are coated on the periphery of this second molding substrate layer；
Wherein, those second metal columns have a plurality of the second tops not coated by this second molding substrate layer.
8. capital as claimed in claim 7 interconnects kenel semiconductor packaging structure it is characterised in that those the second fan-out pads are cover shape pad, and entangles those first tops of those those the first metal columns and the neighbouring post jamb of those the first metal columns.
9. a kind of capital interconnects the manufacture method of kenel semiconductor packaging structure it is characterised in that comprising：
Form one first reconfiguration line layer in a support plate plane, this first reconfiguration line layer comprises a plurality of first fan-in pads and a plurality of first fan-out pads, this support plate plane is provided by a temporary transient support plate；
A plurality of first metal columns are set on those the first fan-out pads；
One first chip is set and and is electrically connected to those the first fan-in pads in this first reconfiguration line layer；
Form one first molding substrate layer in this support plate plane, this the first molding substrate layer has one first lower surface and one first upper surface, this first lower surface is defined in this support plate plane, so that this first reconfiguration line layer is depressed in this first lower surface of this first molding substrate layer, this the first molding substrate layer is more than one first chip rational height of this first chip by one first package thickness of this first upper surface to this first lower surface, so that this first chip is coated in this first molding substrate layer and those first metal columns are coated on the periphery of this first molding substrate layer；And
Execute one first perforate operation so that those first metal columns have a plurality of the first tops not coated by this first molding substrate layer；And
Separate this first molding substrate layer and this temporary transient support plate.
10. capital as claimed in claim 9 interconnect kenel semiconductor packaging structure manufacture method it is characterised in that after the step of above-mentioned first perforate operation with above-mentioned separate the step that this first molding substrate layer is with this temporary transient support plate before, additionally comprise following steps：
Form one second reconfiguration line layer on this first upper surface of this first molding substrate layer, this second reconfiguration line layer comprises a plurality of second fan-in pads and a plurality of second fan-out pads, and wherein those the second fan-out pads are bonded to those first tops of those the first metal columns and the neighbouring post jamb of those the first metal columns；
A plurality of second metal columns are set on those the second fan-out pads；
One second chip is set in this second reconfiguration line layer, and makes this second chip be electrically connected to those the second fan-in pads；
Form one second molding substrate layer on this first upper surface of this first molding substrate layer, this first upper surface is in order to define one second lower surface of this second molding substrate layer, so that this second reconfiguration line layer is depressed in this second lower surface of this second molding substrate layer, one second package thickness of this second molding substrate layer is more than one second chip rational height of this second chip, so that this second chip is coated in this second molding substrate layer and those second metal columns are coated on the periphery of this second molding substrate layer；And
Execute one second perforate operation so that those second metal columns have a plurality of the second tops not coated by this second molding substrate layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109216204A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Ic package and forming method thereof |
Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101567355A (en) * | 2008-04-22 | 2009-10-28 | 全懋精密科技股份有限公司 | Semiconductor packaging base plate and manufacturing method thereof |
| TW201118963A (en) * | 2009-09-15 | 2011-06-01 | Stats Chippac Ltd | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
| CN102324418A (en) * | 2011-08-09 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor component packaging structure and its manufacturing approach |
| US20120013001A1 (en) * | 2010-07-19 | 2012-01-19 | Tessera Research Llc | Stackable molded microelectronic packages with area array unit connectors |
| US20120032340A1 (en) * | 2010-08-06 | 2012-02-09 | Stats Chippac, Ltd. | Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV |
| CN102386104A (en) * | 2010-09-01 | 2012-03-21 | 群成科技股份有限公司 | Quadrilateral flat pin-free encapsulation method |
| CN102487059A (en) * | 2010-12-02 | 2012-06-06 | 三星电子株式会社 | Stacked package structure |
| CN102867806A (en) * | 2011-07-08 | 2013-01-09 | 欣兴电子股份有限公司 | Package substrate and method for manufacturing the same |
| CN102931097A (en) * | 2012-11-08 | 2013-02-13 | 南通富士通微电子股份有限公司 | Method for forming semiconductor packaging structures |
| CN103109367A (en) * | 2010-07-19 | 2013-05-15 | 德塞拉股份有限公司 | Stackable molded microelectronic packages |
| CN103258807A (en) * | 2013-03-26 | 2013-08-21 | 威盛电子股份有限公司 | Circuit substrate, semiconductor packaging structure and circuit substrate manufacturing process |
| US20130241053A1 (en) * | 2012-03-16 | 2013-09-19 | KyungHoon Lee | Integrated circuit packaging system with conductive pillars and molded cavities and method of manufacture thereof |
| TW201401466A (en) * | 2012-06-21 | 2014-01-01 | Stats Chippac Ltd | Semiconductor device and method of forming an embedded sop fan-out package |
| TW201411791A (en) * | 2012-09-14 | 2014-03-16 | Stats Chippac Ltd | Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP |
| CN104241227A (en) * | 2013-06-13 | 2014-12-24 | 爱思开海力士有限公司 | Embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same |
| CN104241196A (en) * | 2013-06-18 | 2014-12-24 | 矽品精密工业股份有限公司 | Stacked package and fabrication method thereof |
| CN104517922A (en) * | 2013-09-27 | 2015-04-15 | 矽品精密工业股份有限公司 | Stacked package structure and method for fabricating the same |
-
2015
- 2015-08-25 CN CN201510525891.7A patent/CN106486453A/en active Pending
Patent Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101567355A (en) * | 2008-04-22 | 2009-10-28 | 全懋精密科技股份有限公司 | Semiconductor packaging base plate and manufacturing method thereof |
| TW201118963A (en) * | 2009-09-15 | 2011-06-01 | Stats Chippac Ltd | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
| US20120013001A1 (en) * | 2010-07-19 | 2012-01-19 | Tessera Research Llc | Stackable molded microelectronic packages with area array unit connectors |
| CN103109367A (en) * | 2010-07-19 | 2013-05-15 | 德塞拉股份有限公司 | Stackable molded microelectronic packages |
| US20120032340A1 (en) * | 2010-08-06 | 2012-02-09 | Stats Chippac, Ltd. | Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV |
| CN102386104A (en) * | 2010-09-01 | 2012-03-21 | 群成科技股份有限公司 | Quadrilateral flat pin-free encapsulation method |
| CN102487059A (en) * | 2010-12-02 | 2012-06-06 | 三星电子株式会社 | Stacked package structure |
| CN102867806A (en) * | 2011-07-08 | 2013-01-09 | 欣兴电子股份有限公司 | Package substrate and method for manufacturing the same |
| CN102324418A (en) * | 2011-08-09 | 2012-01-18 | 日月光半导体制造股份有限公司 | Semiconductor component packaging structure and its manufacturing approach |
| US20130241053A1 (en) * | 2012-03-16 | 2013-09-19 | KyungHoon Lee | Integrated circuit packaging system with conductive pillars and molded cavities and method of manufacture thereof |
| TW201401466A (en) * | 2012-06-21 | 2014-01-01 | Stats Chippac Ltd | Semiconductor device and method of forming an embedded sop fan-out package |
| TW201411791A (en) * | 2012-09-14 | 2014-03-16 | Stats Chippac Ltd | Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP |
| CN102931097A (en) * | 2012-11-08 | 2013-02-13 | 南通富士通微电子股份有限公司 | Method for forming semiconductor packaging structures |
| CN103258807A (en) * | 2013-03-26 | 2013-08-21 | 威盛电子股份有限公司 | Circuit substrate, semiconductor packaging structure and circuit substrate manufacturing process |
| CN104241227A (en) * | 2013-06-13 | 2014-12-24 | 爱思开海力士有限公司 | Embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same |
| CN104241196A (en) * | 2013-06-18 | 2014-12-24 | 矽品精密工业股份有限公司 | Stacked package and fabrication method thereof |
| CN104517922A (en) * | 2013-09-27 | 2015-04-15 | 矽品精密工业股份有限公司 | Stacked package structure and method for fabricating the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109216204A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Ic package and forming method thereof |
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